Tom Dang-Hsing Yiu

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Decoder arrangement of a memory cell array
- Patent number 7,123,537
- Issue date Oct 17, 2006
- Macronix International Co., Ltd.
- Tom D. Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast flash EPROM programming and pre-programming circuit design
- Patent number 6,166,956
- Issue date Dec 26, 2000
- Macronix International Co., Ltd.
- Tom Dang-Hsing Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory redundancy circuit using single polysilicon floating gate tr...
- Patent number 6,031,771
- Issue date Feb 29, 2000
- Macronix International Co., Ltd.
- Tom D. Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked read-only memory
- Patent number 5,949,704
- Issue date Sep 7, 1999
- Macronix International Co., Ltd.
- Fu-Chia Shone
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 5,866,940
- Issue date Feb 2, 1999
- Mega Chips Corporation
- Akira Takata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 5,847,449
- Issue date Dec 8, 1998
- Mega Chips Corporation
- Akira Takata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device
- Patent number 5,825,083
- Issue date Oct 20, 1998
- Mega Chips Corporation
- Akira Takata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fast flash EPROM programming and pre-programming circuit design
- Patent number 5,821,909
- Issue date Oct 13, 1998
- Macronix International Co., Ltd.
- Tom Dang-Hsing Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Block-level wordline enablement to reduce negative wordline stress
- Patent number 5,818,764
- Issue date Oct 6, 1998
- Macronix International Co., Ltd.
- Tom D. Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic test circuitry with non-volatile status write
- Patent number 5,818,848
- Issue date Oct 6, 1998
- Macronix International Co,, Ltd.
- Tien-Ler Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating gate memory device and method for terminating a program lo...
- Patent number 5,778,440
- Issue date Jul 7, 1998
- Macronix International Co., Ltd.
- Tom Dang-Hsing Yiu
- G08 - SIGNALLING
Information Patent Grant
Method and system for soft programming algorithm
- Patent number 5,745,410
- Issue date Apr 28, 1998
- Macronix International Co., Ltd.
- Tom Dang-Hsing Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 5,700,975
- Issue date Dec 23, 1997
- Mega Chips Corporation
- Akira Takata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory cell and array architecture
- Patent number 5,691,938
- Issue date Nov 25, 1997
- Macronix International Co., Ltd.
- Tom Dang-Hsing Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Technique for reconfiguring a high density memory
- Patent number 5,691,945
- Issue date Nov 25, 1997
- Macronix International Co., Ltd.
- Kong-Mou Liou
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoded wordline driver with positive and negative voltage modes
- Patent number 5,668,758
- Issue date Sep 16, 1997
- Macronix Int'l Co., Ltd.
- Tom Dang-Hsing Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of making a non-volatile memory cell
- Patent number 5,633,185
- Issue date May 27, 1997
- Macronix International Co., Ltd.
- Tom Dang-Hsing Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic test circuitry with non-volatile status write
- Patent number 5,627,838
- Issue date May 6, 1997
- Macronix International Co., Ltd.
- Tien-Ler Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of making flash EPROM with conductive sidewall spacer contac...
- Patent number 5,618,742
- Issue date Apr 8, 1997
- Macronix Internatioal, Ltd.
- Fuchia Shone
- G08 - SIGNALLING
Information Patent Grant
Fast flash EPROM programming and pre-programming circuit design
- Patent number 5,615,153
- Issue date Mar 25, 1997
- Tom D. Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture for accessing very high density memory device
- Patent number 5,563,844
- Issue date Oct 8, 1996
- Mega Chips Corporation
- Akira Takata
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast flash EPROM programming and pre-programming circuit design
- Patent number 5,563,822
- Issue date Oct 8, 1996
- Macronix International Co., Ltd.
- Tom D. Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast FLASH EPROM programming and pre-programming circuit design
- Patent number 5,563,823
- Issue date Oct 8, 1996
- Macronix International Co., Ltd.
- Tom D. Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase and program verification circuit for non-volatile memory
- Patent number 5,544,116
- Issue date Aug 6, 1996
- Macronix International Co., Ltd.
- Liang Chao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast pre-programming circuit for floating gate memory
- Patent number 5,539,688
- Issue date Jul 23, 1996
- Macronix International Co., Ltd.
- Tom D. Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase and program verification circuit for non-volatile memory
- Patent number 5,528,546
- Issue date Jun 18, 1996
- Macronix International Company, Ltd.
- Liang Chao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flash EPROM integrated circuit architecture
- Patent number 5,526,307
- Issue date Jun 11, 1996
- Macronix International Co., Ltd.
- Tom D. Yiu
- G08 - SIGNALLING
Information Patent Grant
Erase and program verification circuit for non-volatile memory
- Patent number 5,463,586
- Issue date Oct 31, 1995
- Macronix International Co., Ltd.
- Liang Chao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for manufacturing a contactless floating gate transistor array
- Patent number 5,453,391
- Issue date Sep 26, 1995
- Macronix International Co., Ltd.
- Tom D. Yiu
- G11 - INFORMATION STORAGE
Information Patent Grant
Supply voltage detection circuit
- Patent number 5,420,798
- Issue date May 30, 1995
- Macronix International Co., Ltd.
- Tien-Ler Lin
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
Decoder arrangement of a memory cell array
- Publication number 20030210583
- Publication date Nov 13, 2003
- Macronix International Co., Ltd.
- Tom D. Yiu
- G11 - INFORMATION STORAGE

Tom Dang-Hsing Yiu

Person

Patents Grantslast 30 patents

Decoder arrangement of a memory cell array

Fast flash EPROM programming and pre-programming circuit design

Memory redundancy circuit using single polysilicon floating gate tr...

Stacked read-only memory

Semiconductor device

Semiconductor device

Semiconductor device

Fast flash EPROM programming and pre-programming circuit design

Block-level wordline enablement to reduce negative wordline stress

Automatic test circuitry with non-volatile status write

Floating gate memory device and method for terminating a program lo...

Method and system for soft programming algorithm

Semiconductor device

Non-volatile memory cell and array architecture

Technique for reconfiguring a high density memory

Decoded wordline driver with positive and negative voltage modes

Method of making a non-volatile memory cell

Automatic test circuitry with non-volatile status write

Method of making flash EPROM with conductive sidewall spacer contac...

Fast flash EPROM programming and pre-programming circuit design

Architecture for accessing very high density memory device

Fast flash EPROM programming and pre-programming circuit design

Fast FLASH EPROM programming and pre-programming circuit design

Erase and program verification circuit for non-volatile memory

Fast pre-programming circuit for floating gate memory

Erase and program verification circuit for non-volatile memory

Flash EPROM integrated circuit architecture

Erase and program verification circuit for non-volatile memory

Method for manufacturing a contactless floating gate transistor array

Supply voltage detection circuit

Patents Applicationslast 30 patents

Decoder arrangement of a memory cell array