Wei Lu

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
CMP wafer edge control of dielectric
- Patent number 9,627,219
- Issue date Apr 18, 2017
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating integrated circuits with improved active re...
- Patent number 9,620,418
- Issue date Apr 11, 2017
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Liang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar passivation for pads
- Patent number 9,520,371
- Issue date Dec 13, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benfu Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMP head structure with retaining ring
- Patent number 9,511,470
- Issue date Dec 6, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benfu Lin
- B24 - GRINDING POLISHING
Information Patent Grant
CMP head structure with retaining ring
- Patent number 9,511,474
- Issue date Dec 6, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benfu Lin
- B24 - GRINDING POLISHING
Information Patent Grant
Methods for fabricating integrated circuits having device contacts
- Patent number 9,443,761
- Issue date Sep 13, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Wei Shao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Through silicon vias
- Patent number 9,437,547
- Issue date Sep 6, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benfu Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation for embedded devices
- Patent number 9,349,654
- Issue date May 24, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Liang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Through silicon vias
- Patent number 9,287,197
- Issue date Mar 15, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benfu Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMP head structure
- Patent number 9,242,341
- Issue date Jan 26, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benfu Lin
- B24 - GRINDING POLISHING
Information Patent Grant
CMP head structure
- Patent number 9,242,338
- Issue date Jan 26, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benfu Lin
- B24 - GRINDING POLISHING
Information Patent Grant
Integrated circuits with improved gap fill dielectric and methods f...
- Patent number 9,202,746
- Issue date Dec 1, 2015
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer processing
- Patent number 9,153,473
- Issue date Oct 6, 2015
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Liang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress liner for stress engineering
- Patent number 8,999,863
- Issue date Apr 7, 2015
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jae Gon Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high-k dielectric stop layer for contact hole ope...
- Patent number 8,354,347
- Issue date Jan 15, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jianhui Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planarized passivation layer for semiconductor devices
- Patent number 8,264,088
- Issue date Sep 11, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sin Leng Lim
- G02 - OPTICS
Information Patent Grant
Method and apparatus for automatically recognizing audio data
- Patent number 8,140,329
- Issue date Mar 20, 2012
- Sony Corporation
- Jian Zhang
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Reliable interconnection
- Patent number 8,035,201
- Issue date Oct 11, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reference circuit with reduced current startup
- Patent number 8,022,686
- Issue date Sep 20, 2011
- Texas Instruments Incorporated
- Wei Lu
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated circuit including a stressed dielectric layer with stabl...
- Patent number 8,013,372
- Issue date Sep 6, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planarized passivation layer for semiconductor devices
- Patent number 7,998,831
- Issue date Aug 16, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Sin Leng Lim
- G02 - OPTICS
Information Patent Grant
Method for reducing silicide defects in integrated circuits
- Patent number 7,960,283
- Issue date Jun 14, 2011
- Chartered Semiconductor Manufacturing, Ltd.
- Jeff Jianhui Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system employing sacrificial spacers
- Patent number 7,892,900
- Issue date Feb 22, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect capping layer and method of fabrication
- Patent number 7,855,143
- Issue date Dec 21, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of metal silicide layer over copper interconnect for reli...
- Patent number 7,790,617
- Issue date Sep 7, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing silicide defects in integrated circuits
- Patent number 7,745,320
- Issue date Jun 29, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Jeff Jianhui Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for providing void structures
- Patent number 7,566,656
- Issue date Jul 28, 2009
- Chartered Semiconductor Manufacturing, Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and systems for embedding and detecting watermarks in di...
- Patent number 7,496,209
- Issue date Feb 24, 2009
- Sony Corporation
- Wei Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local positioning system which operates based on reflected wireless...
- Patent number 7,400,291
- Issue date Jul 15, 2008
- Sony Corporation
- Jin Xu
- G01 - MEASURING TESTING
Information Patent Grant
Method for CuO reduction by using two step nitrogen oxygen and redu...
- Patent number 7,332,422
- Issue date Feb 19, 2008
- Chartered Semiconductor Manufacturing, Ltd.
- Wei Lu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND SYSTEMS FOR AUTOMATED TEXT CORRECTION
- Publication number 20170242840
- Publication date Aug 24, 2017
- National University of Singapore
- Wei Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROUGH SILICON VIAS
- Publication number 20160190066
- Publication date Jun 30, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benfu LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMP HEAD STRUCTURE
- Publication number 20160136781
- Publication date May 19, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benfu LIN
- B24 - GRINDING POLISHING
Information Patent Application
CMP HEAD STRUCTURE
- Publication number 20160136774
- Publication date May 19, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benfu LIN
- B24 - GRINDING POLISHING
Information Patent Application
METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED ACTIVE RE...
- Publication number 20160133524
- Publication date May 12, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Liang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLANAR PASSIVATION FOR PADS
- Publication number 20160118355
- Publication date Apr 28, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benfu LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIFORM POLISHING WITH FIXED ABRASIVE PAD
- Publication number 20160114457
- Publication date Apr 28, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Lup San LEONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS HAVING DEVICE CONTACTS AND METHODS FOR FABRICAT...
- Publication number 20160035623
- Publication date Feb 4, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Wei Shao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMP WAFER EDGE CONTROL OF DIELECTRIC
- Publication number 20150303068
- Publication date Oct 22, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Lei WANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION FOR EMBEDDED DEVICES
- Publication number 20150279743
- Publication date Oct 1, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Liang LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS F...
- Publication number 20150187641
- Publication date Jul 2, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Lei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMP HEAD STRUCTURE
- Publication number 20150111467
- Publication date Apr 23, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benfu LIN
- B24 - GRINDING POLISHING
Information Patent Application
CMP HEAD STRUCTURE
- Publication number 20150111469
- Publication date Apr 23, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benfu LIN
- B24 - GRINDING POLISHING
Information Patent Application
WAFER PROCESSING
- Publication number 20150087133
- Publication date Mar 26, 2015
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Liang LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH SILICON VIAS
- Publication number 20140264911
- Publication date Sep 18, 2014
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benfu LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and Systems for Automated Text Correction
- Publication number 20140163963
- Publication date Jun 12, 2014
- National University of Singapore
- Daniel Herman Richard Dahlmeier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Systems for Automated Text Correction
- Publication number 20130325442
- Publication date Dec 5, 2013
- National University of Singapore
- Daniel Herman Richard Dahlmeier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABL...
- Publication number 20110316085
- Publication date Dec 29, 2011
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Huang LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES
- Publication number 20110266688
- Publication date Nov 3, 2011
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Sin Leng LIM
- G02 - OPTICS
Information Patent Application
RELIABLE INTERCONNECTION
- Publication number 20100301461
- Publication date Dec 2, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REFERENCE CIRCUIT WITH REDUCED CURRENT STARTUP
- Publication number 20100283448
- Publication date Nov 11, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Wei Lu
- G05 - CONTROLLING REGULATING
Information Patent Application
METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
- Publication number 20100267236
- Publication date Oct 21, 2010
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jianhui YE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELIABLE INTERCONNECT INTEGRATION
- Publication number 20100109155
- Publication date May 6, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Huang LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING A MODIFIED ISOLATION STRUCTURE
- Publication number 20090325359
- Publication date Dec 31, 2009
- Chartered Semiconductor Manufacturing LTD.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STABLE STRESS DIELECTRIC LAYER
- Publication number 20090315121
- Publication date Dec 24, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Luona GOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS LINER FOR STRESS ENGINEERING
- Publication number 20090302391
- Publication date Dec 10, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jae Gon LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
- Publication number 20090289309
- Publication date Nov 26, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jianhui YE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High shrinkage stress silicon nitride (SiN) layer for NFET improvement
- Publication number 20090289284
- Publication date Nov 26, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Luona Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING SACRIFICIAL SPACERS
- Publication number 20090250762
- Publication date Oct 8, 2009
- Chartered Semiconductor Manufacturing LTD.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESSED DIELECTRIC LAYER WITH STABLE STRESS
- Publication number 20090250764
- Publication date Oct 8, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Huang LIU
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

CMP wafer edge control of dielectric

Methods for fabricating integrated circuits with improved active re...

Planar passivation for pads

CMP head structure with retaining ring

CMP head structure with retaining ring

Methods for fabricating integrated circuits having device contacts

Through silicon vias

Isolation for embedded devices

Through silicon vias

CMP head structure

CMP head structure

Integrated circuits with improved gap fill dielectric and methods f...

Wafer processing

Stress liner for stress engineering

Method of forming high-k dielectric stop layer for contact hole ope...

Planarized passivation layer for semiconductor devices

Method and apparatus for automatically recognizing audio data

Reliable interconnection

Reference circuit with reduced current startup

Integrated circuit including a stressed dielectric layer with stabl...

Planarized passivation layer for semiconductor devices

Method for reducing silicide defects in integrated circuits

Integrated circuit system employing sacrificial spacers

Interconnect capping layer and method of fabrication

Formation of metal silicide layer over copper interconnect for reli...

Method for reducing silicide defects in integrated circuits

Method and apparatus for providing void structures

Techniques and systems for embedding and detecting watermarks in di...

Local positioning system which operates based on reflected wireless...

Method for CuO reduction by using two step nitrogen oxygen and redu...

Patents Applicationslast 30 patents

METHODS AND SYSTEMS FOR AUTOMATED TEXT CORRECTION

THROUGH SILICON VIAS

CMP HEAD STRUCTURE

CMP HEAD STRUCTURE

METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED ACTIVE RE...

PLANAR PASSIVATION FOR PADS

UNIFORM POLISHING WITH FIXED ABRASIVE PAD

INTEGRATED CIRCUITS HAVING DEVICE CONTACTS AND METHODS FOR FABRICAT...

CMP WAFER EDGE CONTROL OF DIELECTRIC

ISOLATION FOR EMBEDDED DEVICES

INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS F...

CMP HEAD STRUCTURE

CMP HEAD STRUCTURE

WAFER PROCESSING

THROUGH SILICON VIAS

Methods and Systems for Automated Text Correction

Methods and Systems for Automated Text Correction

INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABL...

PLANARIZED PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES

RELIABLE INTERCONNECTION

REFERENCE CIRCUIT WITH REDUCED CURRENT STARTUP

METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS

RELIABLE INTERCONNECT INTEGRATION

INTEGRATED CIRCUIT SYSTEM EMPLOYING A MODIFIED ISOLATION STRUCTURE

STABLE STRESS DIELECTRIC LAYER

STRESS LINER FOR STRESS ENGINEERING

METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS

High shrinkage stress silicon nitride (SiN) layer for NFET improvement

INTEGRATED CIRCUIT SYSTEM EMPLOYING SACRIFICIAL SPACERS

STRESSED DIELECTRIC LAYER WITH STABLE STRESS