Patent Application
20090315121
The present invention relates generally to integrated circuits (ICs), and more particularly to forming stressed dielectric layers in ICs.
Integrated circuits (ICs) typically comprise numerous circuit components interconnected to perform the desired functions. Such circuit components include, for example, transistors such as field effect transistors (FETs). Dielectric materials have been employed to generate strain in the channel region of the transistor to enhance carrier mobility.
It is desirable to provide enhanced strain generation in channel regions of transistors to enhance carrier mobility.
The present invention relates to forming stressed dielectric layers. In one aspect, a device comprises a substrate having isolation regions. The isolation regions comprise isolation material which has a first stress. A cap layer disposed on the isolation material, wherein the cap layer reduces degradation of the first stress.
In another embodiment, an integrated circuit (IC) comprises a transistor disposed on a substrate. A dielectric layer is disposed on the substrate over the transistor, the dielectric layer comprises a first stress. A cap layer is disposed on the dielectric layer, wherein the cap layer reduces degradation of the first stress.
In yet another aspect, a method of fabricating a device is disclosed. The method includes providing a substrate prepared with isolation regions with an isolation material having a first stress. A cap layer is formed on the isolation material in the isolation regions, wherein the cap layer reduces degradation of the first stress.
In another embodiment, a method of fabricating an IC is disclosed. The method includes providing a substrate. A dielectric layer is formed on the substrate. The dielectric layer comprises a first stress. A cap layer is formed on the dielectric layer, wherein the cap layer reduces degradation of the first stress.
These and other objects, along with advantages and feature of the present invention herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:
a-e show a process for forming an IC in accordance with one embodiment of the invention;
a-b show a process for forming an IC in accordance with another embodiment of the invention; and
The present invention relates generally to semiconductor devices or ICs. More particularly, the present invention relates to stressed dielectric layers for strain generation in, for example, the channel region of a transistor. The invention can be applied to various types of ICs, such as memory devices including dynamic random access memories (DRAMs), static random access memories (SRAMs), non-volatile memories including programmable read-only memories (PROMs) and flash memories, optoelectronic devices, logic devices, communication devices, digital signal processors (DSPs), microcontrollers, system-on-chip, as well as other types of devices. The ICs can be incorporated in various types of products. Such products, for example, include cell phones, personal digital assistants, computers or other electronic products.
A transistor 140 is disposed in the active region. The transistor, for example, comprises a FET. The FET comprises a second charge carrier type. In one embodiment, the second charge carrier type comprises n-type. The transistor includes a gate stack 145. The gate stack can be gate conductor which forms a plurality of transistors having a common gate. The gate stack comprises a gate electrode over a gate dielectric. The gate electrode, for example, comprises polysilicon while the gate dielectric comprises silicon oxide. Other types of gate electrode and gate dielectric materials are also useful. Dielectric spacers 154 are typically provided on sidewalls of the gate stack.
Beneath the gate is a channel region of the transistor. First and second diffusion regions 147a-b are provided adjacent to the gate stack, separated by the channel region. The diffusion regions comprise second type or n-type dopants, such as phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. Silicide contacts 158 can be provided on the top of the gate and diffusion regions to reduce sheet resistance.
Isolation regions 130 are provided to isolate the active region from other device regions. The isolation regions, for example, comprise shallow trench isolations (STIs). STIs comprise trenches formed in the substrate and filled with a dielectric material. The isolation regions are used to isolate active device regions on the substrate. The depth of the STIs is generally about 1500-4500 Å. Other depths are also useful. The doped well typically overlaps the bottom of the STIs.
In one embodiment, the dielectric material filling the STIs induces a first stress on the channel region of the transistor. Inducing a first stress in the channel region improves the performance of the transistor. In one embodiment, the first stress comprises a tensile stress to improve the performance of the transistors. For example, the first stress improves the performance of n-type and p-type transistors.
The dielectric material, in a preferred embodiment, comprises an ozone-tetraethoxysilane (O3-TEOS) oxide. The O3-TEOS, for example, induces a tensile stress in the channel region of the transistor. To form the O3-TEOS, subatmospheric chemical vapor deposition (SACVD) can be employed. Other techniques are also useful.
In accordance with one embodiment of the invention, a cap layer 132 is provided on the STI trenches. The cap layer acts as a barrier layer to retard moisture absorption by the dielectric material filling the STIs, which can lead to stress degradation. The cap layer, for example, comprises a dielectric material which prevents or absorbs moisture.
In one embodiment, the cap layer comprises a doped O3-TEOS oxide. Preferably, the cap layer is formed from materials filling the trench. For example, the cap layer can be provided by treating the surface of the dielectric material filling the STIs. For example, dopant species are absorbed at the surface of the STI fill to form the cap layer. The dopant species, in one embodiment, comprises nitrogen (N). Other dopant species such as NH3, N2O, NO2, NCl3, NF3, I3N and N2O3 may also be useful. The concentration of dopants in the STI cap layer should be sufficient to enable the cap layer to retard moisture absorption by the STI dielectric. In one embodiment, the N dopant concentration in the STI cap layer is about 1E6-1E15 c/s (using SIMs measurement), and preferably about 1E10 c/s. Other concentrations are also useful. In general, the higher the N concentration in the O3-TEOS, the higher its resistance to moisture absorption, and the more stable its stress. The STI cap layer should be sufficiently thick to act as an effective moisture barrier. In one embodiment, the thickness of the STI cap layer is about 100-4000 Å, and preferably about 200-1000 Å. Other thicknesses are also useful.
A pre-metal dielectric (PMD) 290 layer is provided over the substrate, covering the transistor and the isolation regions. The PMD layer comprises a dielectric material. The PMD layer, for example, is about 400-6000 Å thick. Other thicknesses are also useful.
In one embodiment, the PMD layer induces a first stress on the channel region of the transistor. In one embodiment, the first stress comprises a tensile stress to improve performance of n-type transistors. The dielectric material, in a preferred embodiment, comprises O3-TEOS oxide. The O3-TEOS oxide can be deposited by SACVD. Other techniques are also useful.
In accordance with one embodiment of the invention, a PMD cap layer 268 is provided over the PMD layer. The PMD cap layer acts as a barrier layer to retard moisture absorption by the PMD layer which can lead to stress degradation. In one embodiment, the PMD cap layer comprises a dielectric cap layer similar to the cap layer which covers the STIs as described in
Alternatively, the PMD cap layer comprises a silicon nitride layer. The thickness of the silicon nitride layer can be about 100-4000 Å or about 200-1000 Å. Other thicknesses are also useful. The silicon nitride layer, in one embodiment, comprises a stressed silicon nitride layer. Preferably, the silicon nitride layer comprises a tensile stress silicon nitride layer.
a-e show a process for forming an IC 300 in accordance with one embodiment of the invention. Referring to
A mask 380 is formed on the surface of the substrate. The mask is patterned to form openings corresponding to locations where STI trenches are to be formed. The mask, for example, comprises a soft mask such as photoresist. The photoresist can be patterned by conventional lithographic techniques. An antireflective coating (ARC) is typically provided beneath the photoresist.
Preferably, the mask comprises a hard mask and a soft mask. The hard mask can include a pad oxide layer under a silicon nitride layer. Other types of hard masks are also useful. An ARC can be disposed between the hard mask and soft mask. The soft mask is patterned using conventional lithographical techniques to form openings. The soft mask is then used to pattern the hard mask using, for example, an anisotropic etch such as reactive ion etching (RIE). The soft mask can be removed after patterning the hard mask.
Referring to
Referring to
The dielectric layer, in one embodiment, comprises a dielectric material which applies a first stress. The dielectric material, in one embodiment, applies a tensile stress. Preferably, the dielectric material comprises high tensile O3-TEOS. Other types of dielectric materials are also useful. In one embodiment, the O3-TEOS oxide is formed by a conventional SACVD process. Other types of processes are also useful. The O3-TEOS oxide film, in one embodiment, has a tensile stress of about 0.2-3.5 G dyne/cm2.
The process continues to form a cap layer 332. The cap layer acts as a barrier to prevent moisture absorption by the dielectric material, thereby retarding tensile stress degradation thereof. The cap layer, in one embodiment, comprises an upper portion of the dielectric layer.
In one embodiment, forming the cap layer comprises subjecting the substrate to a thermal treatment with a dopant source. The thermal treatment can comprise microwave, UV curing treatment or rapid thermal anneal (RTA). Other types of thermal treatment are also useful. The dopant source, in one embodiment, comprises nitrogen. The nitrogen dopant source, for example, comprises N2, NH3 or a combination thereof. Other types of dopant sources for nitrogen, such as NO2, NCl3, NF3, T3N and N2O3, are also useful. Furthermore a combination of nitrogen sources is also useful.
The thermal treatment serves to drive out moisture from the dielectric material. Preferably, the thermal treatment reduces the water content of the dielectric material to about 0.01-5 wt %. Additionally, the thermal treatment causes the dopants to react with the upper portion of the dielectric layer to form a N-doped cap layer. The dopant concentration of the cap layer is preferably about 1E6-1E15 c/s (using SIMS measurement). The thickness of the cap layer is about 100-4000 Å below the surface of the substrate in the trenches. For a microwave thermal treatment, it can be performed at about HRF 300-1000 W. For a RTA thermal treatment, it can be performed at a temperature of about 350-480° C. with a pressure of about 1-9 torr for about 15-180 sec with N2 as the dopant source.
Referring to
In an alternative embodiment, the cap layer comprises silicon nitride. The silicon nitride is deposited on the substrate surface by, for example, chemical vapor deposition (CVD). For example, low pressure CVD (LPCVD) can be used. Other techniques, such as PECVD, are also useful. In one embodiment, the substrate is placed into the CVD chamber to deposit the cap layer. The substrate is heated until the substrate temperature is stabilized. In doing so, the moisture in the O3-TEOS is purged from the film. Thereafter, the cap layer is deposited on the substrate, preventing further moisture absorption by the O3-TEOS. This enables the O3-TEOS to maintain its stress. Preferably, the silicon nitride cap layer comprises a tensile silicon nitride cap layer. Providing a tensile silicon nitride cap layer enhances or increases the tensile stress applied to the channel.
The silicon nitride cap layer, in one embodiment, can be formed by partially filling the STI trenches with, for example, O3-TEOS. A silicon nitride layer is then deposited over the O3-TEOS to fill the trenches. The CMP removes excess O3-TEOS and silicon nitride over the substrate, leaving the trenches filled with O3-TEOS with a silicon nitride cap layer. Other techniques for forming the silicon nitride cap layer are also useful.
Next, a doped well 311 is formed. The doped well comprises first type dopants. In one embodiment, the first type dopants comprise p-type dopants which form a p-type doped well. The p-type dopants can include, for example, B. Typically, the dopant concentration of the doped well is about 1E10-1E14/cm2. Conventional ion implantation techniques, such as implantation with a mask can be used to form the doped well. Other techniques are also useful. Optionally, the doped well can be formed prior to forming the STIs.
Referring to
Source/drain diffusion regions 347a-b are then formed in the active region of the substrate adjacent to the gate. In one embodiment, the source/drain diffusion regions comprise dopants of second carrier type. For example, the source/drain diffusion regions comprise n-type dopants, such as P, As, Sb or a combination thereof, to form n-type diffusion regions.
Dielectric spacers 354 are formed on the sidewalls of the gate stack. The dielectric spacers, for example, comprise silicon nitride. Other types of dielectric materials are also useful to form the spacers. To form the spacers, a spacer layer is deposited on the substrate which covers the gate and substrate surface. An etch removes the horizontal components of the spacer layer, leaving spacers on the sidewalls of the gate stack.
The diffusion regions can include shallow source/drain extensions (not shown) and deep source/drain portions. The source/drain extensions can be formed before forming the sidewall spacers, while the deep source/drain portions are formed after the spacers are formed. Metal silicide contacts 358 can be formed on the gate and diffusion regions. The metal silicide contacts, for example, comprise nickel silicide contacts. Other types of metal silicide contacts are also useful. To form the metal silicide contacts, a metal layer is formed on the substrate and annealed to cause a reaction with the silicon substrate. Unreacted metal is removed, leaving the silicide contacts.
The process continues to complete fabricating the IC. For example, the process continues to form pre-metal dielectrics, interconnects, additional interconnect levels, passivation layer, dicing, assembly and packaging.
a-b show a process of forming an IC 300 in accordance with another embodiment of the invention. As shown in
Referring to
In the embodiment where RTA is employed to treat the PMD dielectric material to form the cap layer, the RTA can be integrated with the process of forming the metal silicide contacts. Typically, in forming metal silicide contacts, first and second RTA steps (RTA-1 and RTA-2) are performed. In one embodiment, RTA-2 can be integrated with the step of forming the PMD cap layer. In another embodiment, the PMD cap layer can be formed by depositing a silicon nitride layer on the PMD layer.
Optionally, a cap layer can also be provided over the STI as previously described. The process continues to complete forming the IC.
As described, O3-TEOS oxide is provided in the STI and/or PMD layer to apply a tensile stress to the channel of n-type transistors to enhance carrier mobility of electrons in the channel. A cap layer is formed over the O3-TEOS oxide in the STI and/or PMD layer, acting as a barrier to retard tensile stress degradation caused by moisture absorption. In alternative embodiments, the cap layer comprises doped SACVD O3-TEOS or SiN.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
