Yang Zhang

Person

Rio Rancho, NM, US

People

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENT NANORIBBON THICKNESSES
- Publication number 20250169130
- Publication date May 22, 2025
- Intel Corporation
- Tao Chu
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES
- Publication number 20250140649
- Publication date May 1, 2025
- Intel Corporation
- Feng Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS
- Publication number 20250142948
- Publication date May 1, 2025
- Intel Corporation
- Robin Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
- Publication number 20250112120
- Publication date Apr 3, 2025
- Intel Corporation
- Tao CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH INTERNAL SPACERS FOR 2D CHANNEL...
- Publication number 20250113547
- Publication date Apr 3, 2025
- Intel Corporation
- Chia-Ching LIN
Information Patent Application
MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL...
- Publication number 20250113595
- Publication date Apr 3, 2025
- Intel Corporation
- Tao CHU
Information Patent Application
TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER
- Publication number 20250113559
- Publication date Apr 3, 2025
- Intel Corporation
- Guowei XU
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS
- Publication number 20250107175
- Publication date Mar 27, 2025
- Intel Corporation
- Tao CHU
Information Patent Application
DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS
- Publication number 20250107156
- Publication date Mar 27, 2025
- Intel Corporation
- Chiao-Ti Huang
Information Patent Application
AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT
- Publication number 20250107212
- Publication date Mar 27, 2025
- Intel Corporation
- Yang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
- Publication number 20250096114
- Publication date Mar 20, 2025
- Intel Corporation
- Robin Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
- Publication number 20250098260
- Publication date Mar 20, 2025
- Intel Corporation
- Guowei XU
Information Patent Application
LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES
- Publication number 20250087530
- Publication date Mar 13, 2025
- Intel Corporation
- Chiao-Ti Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE
- Publication number 20250089310
- Publication date Mar 13, 2025
- Intel Corporation
- Ting-Hsiang Hung
Information Patent Application
PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES...
- Publication number 20250006734
- Publication date Jan 2, 2025
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT
- Publication number 20240321887
- Publication date Sep 26, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH BACKSIDE FIN TRIM ISOLATION
- Publication number 20240304619
- Publication date Sep 12, 2024
- Guowei Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL GATE FABRICATION FOR NANORIBBON-BASED TRANSISTORS
- Publication number 20240290788
- Publication date Aug 29, 2024
- Intel Corporation
- Guowei Xu
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENT NANORIBBON THICKNESSES

INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES

INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS

INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING

INTEGRATED CIRCUIT STRUCTURES WITH INTERNAL SPACERS FOR 2D CHANNEL...

MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL...

TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER

INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS

DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS

AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT

VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING

INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS

LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES

THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE

PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES...

INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT

INTEGRATED CIRCUIT DEVICE WITH BACKSIDE FIN TRIM ISOLATION

METAL GATE FABRICATION FOR NANORIBBON-BASED TRANSISTORS