Yeow Kheng Lim

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Slot designs in wide metal lines
- Patent number 9,318,378
- Issue date Apr 19, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric posts in metal layers
- Patent number 8,957,523
- Issue date Feb 17, 2015
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Fan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crack-arresting structure for through-silicon vias
- Patent number 8,860,185
- Issue date Oct 14, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shaoning Yuan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with self-aligned line and via
- Patent number 8,766,454
- Issue date Jul 1, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back-side MOM/MIM devices
- Patent number 8,759,947
- Issue date Jun 24, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Juan Boon Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device with integrated power supply
- Patent number 8,716,856
- Issue date May 6, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Juan Boon Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
TSV backside processing using copper damascene interconnect technology
- Patent number 8,466,062
- Issue date Jun 18, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yue Kang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system employing low-k dielectrics and method of...
- Patent number 8,358,007
- Issue date Jan 22, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Dong Kyun Sohn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of metal silicide layer over copper interconnect for reli...
- Patent number 7,790,617
- Issue date Sep 7, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate aligned dual damascene openings
- Patent number 7,372,156
- Issue date May 13, 2008
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system using dual damascene process
- Patent number 7,253,097
- Issue date Aug 7, 2007
- Chartered Semiconductor Manufacturing, Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with self-aligned line and via and manufacturing...
- Patent number 7,119,010
- Issue date Oct 10, 2006
- Chartered Semiconductor Manfacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate aligned dual damascene openings
- Patent number 6,967,156
- Issue date Nov 22, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicon-on-insulator device wafer die
- Patent number 6,849,928
- Issue date Feb 1, 2005
- Chartered Semiconductor Manufacturing, Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate elevated source/drain transistor with large are...
- Patent number 6,780,691
- Issue date Aug 24, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating SOI devices with option of incorporating air...
- Patent number 6,613,652
- Issue date Sep 2, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicon-on-insulator device wafer die
- Patent number 6,558,994
- Issue date May 6, 2003
- Chartered Semiconductors Maufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a small dimensional gate with elevated sourc...
- Patent number 6,518,133
- Issue date Feb 11, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assorted aluminum wiring design to enhance chip-level performance f...
- Patent number 6,472,697
- Issue date Oct 29, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating complementary silicon on insulator devices u...
- Patent number 6,468,880
- Issue date Oct 22, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified method to reduce or eliminate STI oxide divots
- Patent number 6,432,797
- Issue date Aug 13, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assorted aluminum wiring design to enhance chip-level performance f...
- Patent number 6,399,471
- Issue date Jun 4, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form high performance copper damascene interconnects by d...
- Patent number 6,380,084
- Issue date Apr 30, 2002
- Chartered Semiconductor Manufacturing Inc.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Versatile copper-wiring layout design with low-k dielectric integra...
- Patent number 6,355,563
- Issue date Mar 12, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to eliminate top metal corner shaping during bottom metal pa...
- Patent number 6,319,767
- Issue date Nov 20, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SLOT DESIGNS IN WIDE METAL LINES
- Publication number 20160233157
- Publication date Aug 11, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Yeow Kheng LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH INTEGRATED PASSIVE COMPONENT
- Publication number 20140264733
- Publication date Sep 18, 2014
- GLOBALFOUNDERS Singapore Pte. Ltd.
- Shaoning YUAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC POSTS IN METAL LAYERS
- Publication number 20140191407
- Publication date Jul 10, 2014
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Fan ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH INTEGRATED POWER SUPPLY
- Publication number 20140035155
- Publication date Feb 6, 2014
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Juan Boon TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS
- Publication number 20130277810
- Publication date Oct 24, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Juan Boon Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACK-SIDE MOM/MIM DEVICES
- Publication number 20130256834
- Publication date Oct 3, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Juan Boon TAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Crack-Arresting Structure for Through-Silicon Vias
- Publication number 20130187280
- Publication date Jul 25, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Shaoning Yuan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TSV Backside Processing Using Copper Damascene Interconnect Technology
- Publication number 20130105968
- Publication date May 2, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yue Kang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF...
- Publication number 20100314763
- Publication date Dec 16, 2010
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Dong Kyun Sohn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of metal silicide layer over copper interconnect for reli...
- Publication number 20070111522
- Publication date May 17, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH SELF-ALIGNED LINE AND VIA
- Publication number 20070075371
- Publication date Apr 5, 2007
- Chartered Semiconductor Manufacturing LTD.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS
- Publication number 20070001303
- Publication date Jan 4, 2007
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Slot designs in wide metal lines
- Publication number 20060040491
- Publication date Feb 23, 2006
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to fabricate aligned dual damacene openings
- Publication number 20060003573
- Publication date Jan 5, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to fabricate aligned dual damascene openings
- Publication number 20050090095
- Publication date Apr 28, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to fabricate elevated source/drain transistor with large are...
- Publication number 20040033668
- Publication date Feb 19, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with self-aligned line and via and manufacturing...
- Publication number 20030197279
- Publication date Oct 23, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual silicon-on-insulator device wafer die
- Publication number 20030107083
- Publication date Jun 12, 2003
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating SOI devices with option of incorporating air...
- Publication number 20020132448
- Publication date Sep 19, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Assorted aluminum wiring design to enhance chip-level performance f...
- Publication number 20020127834
- Publication date Sep 12, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual silicon-on-insulator device wafer die
- Publication number 20020127816
- Publication date Sep 12, 2002
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIMPLIFIED METHOD TO REDUCE OR ELIMINATE STI OXIDE DIVOTS
- Publication number 20020098661
- Publication date Jul 25, 2002
- Randall Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS

Yeow Kheng Lim

Person

Patents Grantslast 30 patents

Slot designs in wide metal lines

Dielectric posts in metal layers

Crack-arresting structure for through-silicon vias

Integrated circuit with self-aligned line and via

Back-side MOM/MIM devices

Device with integrated power supply

TSV backside processing using copper damascene interconnect technology

Integrated circuit system employing low-k dielectrics and method of...

Formation of metal silicide layer over copper interconnect for reli...

Method to fabricate aligned dual damascene openings

Integrated circuit system using dual damascene process

Integrated circuit with self-aligned line and via and manufacturing...

Method to fabricate aligned dual damascene openings

Dual silicon-on-insulator device wafer die

Method to fabricate elevated source/drain transistor with large are...

Method for fabricating SOI devices with option of incorporating air...

Dual silicon-on-insulator device wafer die

Method for fabricating a small dimensional gate with elevated sourc...

Assorted aluminum wiring design to enhance chip-level performance f...

Method for fabricating complementary silicon on insulator devices u...

Simplified method to reduce or eliminate STI oxide divots

Assorted aluminum wiring design to enhance chip-level performance f...

Method to form high performance copper damascene interconnects by d...

Versatile copper-wiring layout design with low-k dielectric integra...

Method to eliminate top metal corner shaping during bottom metal pa...

Patents Applicationslast 30 patents

SLOT DESIGNS IN WIDE METAL LINES

DEVICE WITH INTEGRATED PASSIVE COMPONENT

DIELECTRIC POSTS IN METAL LAYERS

DEVICE WITH INTEGRATED POWER SUPPLY

METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS

BACK-SIDE MOM/MIM DEVICES

Crack-Arresting Structure for Through-Silicon Vias

TSV Backside Processing Using Copper Damascene Interconnect Technology

INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF...

Formation of metal silicide layer over copper interconnect for reli...

INTEGRATED CIRCUIT WITH SELF-ALIGNED LINE AND VIA

INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS

Slot designs in wide metal lines

Method to fabricate aligned dual damacene openings

Method to fabricate aligned dual damascene openings

Method to fabricate elevated source/drain transistor with large are...

Integrated circuit with self-aligned line and via and manufacturing...

Dual silicon-on-insulator device wafer die

Method for fabricating SOI devices with option of incorporating air...

Assorted aluminum wiring design to enhance chip-level performance f...

Dual silicon-on-insulator device wafer die

SIMPLIFIED METHOD TO REDUCE OR ELIMINATE STI OXIDE DIVOTS