Patent Application
20140264733
This application cross-references to co-pending U.S. patent application Ser. No. 13/565,748, entitled “Device with Integrated Power Supply” (Attorney Docket Number GFSP2012NAT19US0), filed on Aug. 2, 2012, which is herein incorporated by reference for all purposes.
As technology evolves into era of sub-micron, there is a desire to integrate different circuit elements into a single chip or integrated circuit (IC). There is also a desire to integrate different chips both vertically and horizontally in a single package to form a 2.5D or 3D IC package. Nevertheless, it is difficult to integrate these different types of elements in a single chip or a single package. Particularly, some of these elements may require large feature size for optimum or enhanced performance. For example, for RF applications, passive elements, such as high Q value inductors are required. However, the high Q value inductor is formed by ultra thick metal (UTM) process which introduces big feature size, such as >1.5 μm in width and >2 μm in thickness, in the front end of line (FEOL) or back end of line (BEOL) processes. This undesirably consumes a lot of chip space and chip thickness in these device levels. Moreover, such process is performed in the processing of advanced technode chips which is not cost effective.
From the foregoing discussion, it is desirable to provide a device with high circuit performance which requires reduced chip or package size. It is also desirable to provide a smaller product which enhances portability. In addition, it is desirable to provide a cost effective process for forming a device which is fully compatible with the process for forming 2.5D and 3D IC or package in the future.
Embodiments generally relate to semiconductor devices. In one embodiment, a semiconductor device is disclosed. In one embodiment, a semiconductor device is presented. The semiconductor device includes a die which includes a die substrate having first and second major surfaces. The semiconductor device includes a passive component disposed below the second major surface of the die substrate. The passive component is electrically coupled to the die through through silicon via (TSV) contacts.
In another embodiment, a method for forming a semiconductor device is disclosed. The method includes providing a die which includes a die substrate having first and second major surfaces. A passive component is provided below the second major surface of the die substrate. The passive component is electrically coupled to the die through through silicon via (TSV) contacts.
In yet another embodiment, a method for forming a semiconductor device is presented. The method includes providing a wafer having first and second major surfaces. A passive component is provided below the second major surface of the wafer. The passive component is electrically coupled to the wafer through through silicon via (TSV) contacts.
These and other advantages and features of the embodiments herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. Various embodiments of the invention are described with reference to the following drawings, in which:
a shows a simplified cross-sectional view of an embodiment of a semiconductor device;
b shows enlarged view of a portion of the semiconductor device of
c shows a top view of an embodiment of an inductor;
a-b show other embodiments of a semiconductor device; and
Embodiments relate to semiconductor devices or integrated circuits (ICs). The semiconductor devices may include one or more dies. For the case of more than one die, the dies may be arranged in a planar arrangement, vertical arrangement, or a combination thereof. The die, for example, may include memory device, logic device, communication device, RF device, optoelectronic device, digital signal processor (DSP), microcontroller, system-on-chip (SOC) as well as other types of device or a combination thereof. Such semiconductor device may be incorporated into electronic products or equipment, such as phones, computers, mobile smart products, etc.
a shows a simplified cross-sectional view of an embodiment of a semiconductor device 100 while
The die includes a die substrate 115. The die substrate may be a semiconductor substrate. For example, the die substrate may be a silicon substrate. Other types of semiconductor substrates may also be useful. For example, the die substrate may be a silicon-on-insulator, silicon germanium or other types of semiconductor substrates. The die substrate includes first and second major substrate surfaces 116a-b. The first major substrate surface 116a, for example, may be referred to as the front or active substrate surface and the second major surface 116b, for example, may be referred to as the back or inactive substrate surface. Other designations for the surfaces may also be useful.
The inactive substrate surface may serve as a bottom die surface 110b. The bottom die surface may be provided with a dielectric layer 170. The active surface is the surface of the substrate on which circuit components 140 are formed. The components, for example, include transistors having gate and source/drain (s/d) regions. Providing other types of circuit components may also be useful. For example, the substrate may include a combination of active and passive components.
A dielectric layer 131 is disposed over the components. The dielectric layer serves as a pre-metal dielectric (PMD) layer. The PMD layer, for example, includes silicon oxide, tetraethylorthosilicate (TEOS) or low-k dielectric. Other suitable types of dielectric material may also be used as the PMD layer. Typically, contacts 152 are provided through the PMD layer and are used to connect the front end devices, such as source/drain and gate of the transistor, to an interconnect metal layer disposed thereover. The contacts, for example, include tungsten contacts. Other suitable types of conductive materials can serve as contacts.
The components may be interconnected by interconnects 164 disposed on one or more metal levels 160. The metal levels, for example, are disposed over the PMD layer. A first metal level (e.g., M0) is disposed on the PMD layer. The first metal level includes interconnects 164 formed in an intra-metal dielectric (IMD) layer. The interconnects, for example, include copper or copper alloy interconnects. Other suitable types of conductive materials, such as Aluminum (Al), etc., may be used to form the interconnects.
Additional metal levels may be disposed over the first metal level. A metal level is formed in an interconnect dielectric (ICD) layer. An ICD layer 135, for example, includes lower and upper portions. The lower portion serves as an inter-level dielectric (ILD) layer while the upper portion serves as an intra-metal IMD layer. The IMD layer includes interconnects 164 of metal level Mx and the ILD includes via contact 162 of via level Vx, where x corresponds to a number of the metal level. For example, x is from 1 to the top metal level. Via contacts of via level Vx couples interconnects of Mx to interconnects of metal level Mx-1 below. Other configurations or designations of levels or layers may also be useful.
The ILD layer can be a single layer or a multi-layered dielectric stack. For example, a single layer can be used to serve as both the ILD and IMD or separate layers are used for the ILD and IMD. An etch stop layer may be provided between the ILD and IMD layers as well as between ICD layers. For multi-layered ICD, the ILD and IMD can include the same or different materials.
The dielectric material of the ICD may include a low-k (LK) or ultra low-k (ULK) dielectric material. Various types of low-k or ultra low-k materials, such as organo-silicate glass (OSG), fluorine-doped silicate glass (FSG) or SiCOH can be employed. Other types of dielectric materials are also useful. For example, the dielectric layer can include silicon oxide, doped silicon oxide such as fluorinated silicon oxide (FSG), undoped or doped silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), undoped or doped thermally grown silicon oxide, undoped or doped TEOS deposited silicon oxide.
Die contact pads 168 are disposed over the ICD and are coupled to the interconnects in the metal levels. A passivation layer 137 having openings 171 is disposed over the ICD. As shown, the openings expose portions of the die contact pads. A top surface of the passivation layer, for example, may be referred to as a top die surface 110a. Under bump metallization and ball bumps (not shown) may be provided over the die contact pads, forming a flip chip.
The die, in one embodiment, includes a plurality of through silicon via (TSV) contacts 150. The TSV contacts are formed in through silicon vias (TSVs). The TSV contacts, for example, extend from the top surface of the PMD layer to the second major substrate surface 116b. The first surface 150a of the TSV contacts may be coupled to the die contact pads in the passivation layer via the interconnections through, for example, the ICD layers or metal levels. Other configurations of TSV contacts may also be useful. An insulating liner 157 may be provided to line the sidewalls of the TSVs. In some cases, the liner may also line the surface of the PMD. Other configurations of the liner may also be useful.
In one embodiment, a passive component/element 120 is integrated into the device package. The passive component, in one embodiment, includes an inductor. Other suitable types of passive components, such as transformers, may also be useful. For illustration purposes, an inductor is shown as the passive component. The inductor, in one embodiment, is disposed over the second major substrate surface 116b. In one embodiment, the inductor is disposed in a dielectric layer 170. For example, the inductor is disposed in a first plane or a metal level of the dielectric layer 170 disposed over the second major substrate surface 116b. The dielectric layer or liner separates the metal level from the substrate.
The outer loop, for example, includes first and second segments 121a-b. The first and second segments are, for example, about the same length. Forming first and second segments having unequal lengths are also useful. The inner loop includes first and second ends, forming an open loop. The inductor includes first and second terminals 125a-b. The first and second terminals of the inductor are coupled to first ends of the outer segments. The second ends of the outer inductor segments are coupled to first and second ends of the inner loop via a cross-over coupling 127. The first ends are located on a first portion of the inductor circuit while the second ends are located on a second portion. The first and second portions are opposite portions of the inductor circuit.
The cross-over coupling, for example, is provided on a second plane of the dielectric layer which is different than first plane where the loops of the inductor are formed. For example, the cross-over coupling is provided on a plane below the inductor. Forming the cross-over coupling in a plane above the inductor is also useful.
The inductor, as described above, is for purpose of illustration and should not be limited thereto. The inductor may include other suitable types of configurations. For example, the inductor may be formed on multiple metal levels. It is also understood that the device package may include other types of inductor disposed over the second major substrate surface or inactive surface 116b of the die.
In one embodiment, the terminals 125a-b of the inductor disposed on the second substrate surface or backside of the die are directly coupled to the other components via some of the TSV contacts 150. In one embodiment, the terminals of the inductor are directly coupled to the second surfaces 150b of some of the TSV contacts as shown in
The dies, for example, include a combination of TSV contacts 150 which are coupled to terminals of the passive components 120, such as inductors, and TSV contacts 150 which are coupled to RDLs for die stacking. For example, the passive components are disposed on the bottom or the second substrate surface of the dies. The RDLs of a die provide connections to TSV contacts of a die below. For example, the RDL of the ith+1 die provides connections to the TSV contacts of the ith die. Moreover, it is understood that not all dies need to have the same configurations. For example, the bottom die may include a combination of TSV contacts which are used for connecting to the passive component as well as TSV contacts which are used for die stacking, while the other dies include TSV contacts which are coupled to RDLs for connecting an ith+1 die to die pads of ith die.
a-b illustrate other embodiments of a semiconductor device 300. Referring to
The interposer includes first and second interposer surfaces 380a-b. A dielectric layer may line each of the first and second surfaces of the interposer. As shown, the passive device 120 is disposed on the second interposer surface 380a while the die is disposed on the first interposer surface. In one embodiment, the interposer includes interposer contacts 350 formed in through silicon vias formed in the interposer substrate. The interposer contacts 350, for example, are similar to the TSV contacts 150 described in
The die 310, for example, may include TSV contacts (not shown) which provide connections on its bottom surface 310b to die pads (not shown) which are coupled to RDLs (not shown) disposed on the top interposer surface 380a. RDLs may be disposed on the first and second major surfaces of the interposer, providing connections between the interposer contacts 350 to the TSV contacts (not shown) of the die 310 and the package substrate below 390.
As shown, a single die 310 is provided on the first major surface of the interposer. It is understood that a die stack, as described in
In an alternative embodiment, as shown in
As described, the die or a set of dies is provided with TSV contacts. The TSV contacts enable the passive component 120, such as an inductor with high Q value with big feature size, to be disposed on the back or second substrate surface. The TSV contacts, in one embodiment, enables coupling of the inductor which is disposed on the second substrate surface to the circuit components on the first substrate surface. Moreover, the remaining TSV contacts also enable coupling to the RDLs for chip stacking or for connection to the package substrate. Since the inductor is coupled to the back or second surface of the substrate, capacitance and crosstalk concern is reduced. Such configuration also avoids the use of an additional shield, reducing the cost of production.
The process continues by thinning the second surface or inactive surface of the wafer to reduce the thickness of the wafer. The second surface of the wafer, for example, is thinned by processes such as grinding, CMP, RIE, etc., or a combination thereof. The backgrinding process, for example, exposes the bottom of the TSV contacts at step 412.
At step 414, a passive component and RDLs are formed on the second major surface of the wafer. The passive component, in one embodiment, includes an inductor. Providing other types of passive component may also be useful. For illustration, the passive component includes an inductor similar to that described with respect to
The process may include further or additional processing steps to complete the fabrication of the semiconductor device. For example, the wafer can be diced or singulated to separate the wafer into individual dies with integrated passive component, such as inductor, and further processed to form a device package as shown in
As described, the TSV contacts enable the passive component, such as an inductor with high Q value having big feature size, to be disposed on the back or second substrate surface. The TSV contacts, in one embodiment, enables coupling of the inductor which is disposed on the second substrate surface to the circuit components on the first substrate surface. As such, the process of forming the passive component, such as the inductor with high Q value, can be separated from other front end of line (FEOL) and back end of line (BEOL) processes. This enables the inductor having big feature size to be processed in low technode fab or outsourced semiconductor assembly and test. Moreover, the remaining TSV contacts also enable coupling to the RDLs for chip stacking or for connection to a package substrate. Since the inductor is coupled to the back or second surface of the substrate, capacitance and crosstalk concern is reduced. Such configuration also avoids the use of an additional shield, reducing the cost of production. In addition, the embodiment as described with respect to
The second or bottom surface of the interposer wafer is thinned to reduce the thickness of the wafer. The second surface of the interposer wafer, for example, is thinned by processes such as grinding, CMP, RIE, etc., or a combination thereof. The backgrinding process, for example, exposes the bottom of the interposer contacts at step 512.
At step 514, a passive component and RDLs are provided on the second major surface of the interposer wafer. The passive component includes an inductor similar to that described with respect to
The process also includes providing a die or a plurality of dies at step 514 on the first surface of the interposer wafer. In one embodiment, the die may include TSV type of die similar or the same as that described with respect to
The process may include further or additional processing steps to complete the fabrication of the semiconductor device. For example, the interposer wafer can be diced or singulated to separate the wafer and further processed to form the individual device package with integrated passive component, such as inductor, as shown in
The embodiment as described with respect to
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments, therefore, are to be considered in all respects illustrative rather than limiting the invention described herein. Scope of the invention is thus indicated by the appended claims, rather than by the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
