YU SUN

Person

SARATOGA, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Charge trapping split gate embedded flash memory and associated met...
- Patent number 9,922,833
- Issue date Mar 20, 2018
- Cypress Semiconductor Corporation
- Mark Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming edge wordline implants adjacent edge wordlines
- Patent number 9,466,489
- Issue date Oct 11, 2016
- Cypress Semiconductor Corporation
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual storage node memory
- Patent number 9,461,151
- Issue date Oct 4, 2016
- Cyress Semiconductor Corporation
- Fred T. K. Cheung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory manufacturing process with bitline isolation
- Patent number 8,673,716
- Issue date Mar 18, 2014
- Spansion LLC
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual storage node memory
- Patent number 8,564,042
- Issue date Oct 22, 2013
- Spansion LLC
- Fred Cheung
- G11 - INFORMATION STORAGE
Information Patent Grant
Applying negative gate voltage to wordlines adjacent to wordline as...
- Patent number 7,995,386
- Issue date Aug 9, 2011
- Spansion LLC
- Yuji Mizuguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Thin oxide dummy tiling as charge protection
- Patent number 7,977,218
- Issue date Jul 12, 2011
- Spansion LLC
- Cinti Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device
- Patent number 7,759,745
- Issue date Jul 20, 2010
- Fujitsu Limited
- Hideki Komori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device
- Patent number 7,683,440
- Issue date Mar 23, 2010
- Fujitsu Limited
- Hideki Komori
Information Patent Grant
Semiconductor device having a pad metal layer and a lower metal lay...
- Patent number 7,632,749
- Issue date Dec 15, 2009
- Spansion LLC
- Hiroyuki Ogawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device
- Patent number 7,482,226
- Issue date Jan 27, 2009
- Fujitsu Limited
- Hideki Komori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation approach for improved STI corner rounding
- Patent number 7,439,141
- Issue date Oct 21, 2008
- Spansion, LLC
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bit line implant
- Patent number 7,432,178
- Issue date Oct 7, 2008
- Advanced Micro Devices, Inc.
- Angela T. Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for coupling to a common line in an array
- Patent number 7,323,726
- Issue date Jan 29, 2008
- Spansion LLC
- Kuo-Tung Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-critical complementary masking method for poly-1 definition in...
- Patent number 7,307,002
- Issue date Dec 11, 2007
- Spansion LLC
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned STI SONOS
- Patent number 7,303,964
- Issue date Dec 4, 2007
- Spansion LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for low Vss resistance and reduced DIBL in a f...
- Patent number 7,301,193
- Issue date Nov 27, 2007
- Spansion LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for improving the topography of a memory array
- Patent number 7,226,839
- Issue date Jun 5, 2007
- Spansion LLC
- King Wai Kelwin Ko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device
- Patent number 7,202,540
- Issue date Apr 10, 2007
- Fujitsu Limited
- Hideki Komori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and device for reducing interface area of a memory device
- Patent number 7,151,027
- Issue date Dec 19, 2006
- Spansion LLC
- Hiroyuki Ogawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device having improved periphery and core isolation
- Patent number 7,078,314
- Issue date Jul 18, 2006
- Advanced Micro Devices, Inc.
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device and method of simultaneous fabrication of core and pe...
- Patent number 7,060,564
- Issue date Jun 13, 2006
- Advanced Micro Devices, Inc.
- Inkuk Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge performance of a silicon structure and effi...
- Patent number 7,019,366
- Issue date Mar 28, 2006
- FASL LLC
- Nian Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual spacer process for non-volatile memory devices
- Patent number 7,012,008
- Issue date Mar 14, 2006
- Advanced Micro Devices, Inc.
- Jeffrey A. Shields
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with core and periphery regions
- Patent number 6,995,437
- Issue date Feb 7, 2006
- Advanced Micro Devices, Inc.
- Hiroyuki Kinoshita
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming nitrogen-rich regions in non-volatile semicondu...
- Patent number 6,989,319
- Issue date Jan 24, 2006
- Advanced Micro Devices, Inc.
- Mark Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for forming dual gate structures in a nonvolatile...
- Patent number 6,974,995
- Issue date Dec 13, 2005
- Advanced Micro Devices, Inc.
- Angela Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a memory device having reverse LDD
- Patent number 6,936,515
- Issue date Aug 30, 2005
- FASL LLP
- Hiroyuki Ogawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Narrow wide spacer
- Patent number 6,927,129
- Issue date Aug 9, 2005
- Advanced Micro Devices
- Yu Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD implant following spacer deposition
- Patent number 6,900,085
- Issue date May 31, 2005
- Advanced Micro Devices, Inc.
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHARGE TRAPPING SPLIT GATE EMBEDDED FLASH MEMORY AND ASSOCIATED MET...
- Publication number 20160111292
- Publication date Apr 21, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Mark RAMSBEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR FORMING EDGE WORDLINE IMPLANTS ADJACENT EDGE WORDLINES
- Publication number 20150171100
- Publication date Jun 18, 2015
- SPANSION LLC
- Timothy THURGATE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Charge Trapping Split Gate Embedded Flash Memory and Associated Met...
- Publication number 20140167141
- Publication date Jun 19, 2014
- SPANSION LLC
- Mark RAMSBEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL STORAGE NODE MEMORY
- Publication number 20140024190
- Publication date Jan 23, 2014
- SPANSION LLC
- Fred CHEUNG
- G11 - INFORMATION STORAGE
Information Patent Application
APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE AS...
- Publication number 20100128521
- Publication date May 27, 2010
- SPANSION LLC
- Yuji Mizuguchi
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE S...
- Publication number 20090256242
- Publication date Oct 15, 2009
- SPANSION LLC
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin oxide dummy tiling as charge protection
- Publication number 20080153269
- Publication date Jun 26, 2008
- Cinti Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual storage node memory
- Publication number 20070205454
- Publication date Sep 6, 2007
- Fred Cheung
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device (as amended)
- Publication number 20070117303
- Publication date May 24, 2007
- FUJITSU LIMITED
- Hideki Komori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor memory device
- Publication number 20070114617
- Publication date May 24, 2007
- Fujitsu Limited
- Hideki Komori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bit line implant
- Publication number 20070093042
- Publication date Apr 26, 2007
- Angela T. Hui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned STI SONOS
- Publication number 20060240635
- Publication date Oct 26, 2006
- Spansion LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-critical complementary masking method for poly-1 definition in...
- Publication number 20060223278
- Publication date Oct 5, 2006
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor memory device and manufacturing method thereof
- Publication number 20050230714
- Publication date Oct 20, 2005
- FUJITSU LIMITED
- Hideki Komori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method for low Vss resistance and reduced dibl in a f...
- Publication number 20050164450
- Publication date Jul 28, 2005
- FASL, LLC, a limited liability company
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Efficient use of wafer area with device under the pad approach
- Publication number 20050151265
- Publication date Jul 14, 2005
- Nian Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and system for reducing short channel effects in a memory de...
- Publication number 20040082127
- Publication date Apr 29, 2004
- Advanced Micro Devices, Inc.
- Tommy Hsiao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory manufacturing process with bitline isolation
- Publication number 20030190786
- Publication date Oct 9, 2003
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow trench isolation approach for improved STI corner rounding
- Publication number 20030176043
- Publication date Sep 18, 2003
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
- Publication number 20030085417
- Publication date May 8, 2003
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming nitridated tunnel oxide barriers for flash memory...
- Publication number 20030073288
- Publication date Apr 17, 2003
- Tuan Duc Pham
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Manufacture of semiconductor device with spacing narrower than lith...
- Publication number 20030064585
- Publication date Apr 3, 2003
- Yider Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD implant following spacer deposition
- Publication number 20020195663
- Publication date Dec 26, 2002
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Tungsten gate MOS transistor and memory cell and method of making same
- Publication number 20020137284
- Publication date Sep 26, 2002
- Advanced Micro Devices, Inc.
- Chi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM FOR REDUCING SHORT CHANNEL EFFECTS IN A MEMORY DE...
- Publication number 20010050400
- Publication date Dec 13, 2001
- YU SUN
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Charge trapping split gate embedded flash memory and associated met...

Process for forming edge wordline implants adjacent edge wordlines

Dual storage node memory

Memory manufacturing process with bitline isolation

Dual storage node memory

Applying negative gate voltage to wordlines adjacent to wordline as...

Thin oxide dummy tiling as charge protection

Semiconductor memory device

Semiconductor memory device

Semiconductor device having a pad metal layer and a lower metal lay...

Semiconductor memory device

Shallow trench isolation approach for improved STI corner rounding

Bit line implant

Method and apparatus for coupling to a common line in an array

Non-critical complementary masking method for poly-1 definition in...

Self-aligned STI SONOS

Structure and method for low Vss resistance and reduced DIBL in a f...

Method and system for improving the topography of a memory array

Semiconductor memory device

Method and device for reducing interface area of a memory device

Memory device having improved periphery and core isolation

Memory device and method of simultaneous fabrication of core and pe...

Electrostatic discharge performance of a silicon structure and effi...

Dual spacer process for non-volatile memory devices

Semiconductor device with core and periphery regions

Methods for forming nitrogen-rich regions in non-volatile semicondu...

Method and system for forming dual gate structures in a nonvolatile...

Method for fabricating a memory device having reverse LDD

Narrow wide spacer

ESD implant following spacer deposition

Patents Applicationslast 30 patents

CHARGE TRAPPING SPLIT GATE EMBEDDED FLASH MEMORY AND ASSOCIATED MET...

PROCESS FOR FORMING EDGE WORDLINE IMPLANTS ADJACENT EDGE WORDLINES

Charge Trapping Split Gate Embedded Flash Memory and Associated Met...

DUAL STORAGE NODE MEMORY

APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE AS...

METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE S...

Thin oxide dummy tiling as charge protection

Dual storage node memory

Semiconductor memory device (as amended)

Semiconductor memory device

Bit line implant

Self-aligned STI SONOS

Non-critical complementary masking method for poly-1 definition in...

Semiconductor memory device and manufacturing method thereof

Structure and method for low Vss resistance and reduced dibl in a f...

Efficient use of wafer area with device under the pad approach

Method and system for reducing short channel effects in a memory de...

Memory manufacturing process with bitline isolation

Shallow trench isolation approach for improved STI corner rounding

SALICIDED GATE FOR VIRTUAL GROUND ARRAYS

Method of forming nitridated tunnel oxide barriers for flash memory...

Manufacture of semiconductor device with spacing narrower than lith...

ESD implant following spacer deposition

Tungsten gate MOS transistor and memory cell and method of making same

METHOD AND SYSTEM FOR REDUCING SHORT CHANNEL EFFECTS IN A MEMORY DE...