by means of an encapsulation layer or foil

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H01L2224/81904

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

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H01L2224/81904by means of an encapsulation layer or foil

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Patents Grantslast 30 patents

Information Patent Grant
Package substrate, semiconductor package and method of manufacturin...
- Patent number 9,640,503
- Issue date May 2, 2017
- Siliconware Precision Industries Co., Ltd.
- Ming-Chen Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure and its fabrication method
- Patent number 9,536,864
- Issue date Jan 3, 2017
- PHOENIX PIONEER TECHNOLOGY CO., LTD.
- Shih-Ping Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip support substrate, chip support method, three-dimensional inte...
- Patent number 9,449,948
- Issue date Sep 20, 2016
- Tohoku University
- Mitsumasa Koyanagi
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device with semiconductor chips mounted on mounting b...
- Patent number 7,633,148
- Issue date Dec 15, 2009
- Fujitsu Limited
- Yuji Awano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with heat sink
- Patent number 7,166,914
- Issue date Jan 23, 2007
- Tessera, Inc.
- Thomas H. DiStefano
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and system for chip-to-package interconnection
- Patent number 6,953,707
- Issue date Oct 11, 2005
- Texas Instruments Incorporated
- Manjula N. Variyam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for providing void-free layers for semiconductor assemblies
- Patent number 6,780,747
- Issue date Aug 24, 2004
- Tessera, Inc.
- Thomas H. Distefano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for providing void-free layers for semiconductor assemblies
- Patent number 6,653,172
- Issue date Nov 25, 2003
- Tessera, Inc.
- Thomas H. Distefano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing void free layer for semiconductor assemblies
- Patent number 6,458,681
- Issue date Oct 1, 2002
- Tessera, Inc.
- Thomas H. Distefano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out semiconductor chip assembly
- Patent number 6,265,765
- Issue date Jul 24, 2001
- Tessera, Inc.
- Thomas H. DiStefano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for providing void-free layers for semiconductor assemblies
- Patent number 6,107,123
- Issue date Aug 22, 2000
- Tessera, Inc.
- Thomas H. Distefano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for providing void-free layers for semiconductor assemblies
- Patent number 5,834,339
- Issue date Nov 10, 1998
- Tessera, Inc.
- Thomas H. Distefano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out semiconductor chip assembly
- Patent number 5,688,716
- Issue date Nov 18, 1997
- Tessera, Inc.
- Thomas H. DiStefano
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURIN...
- Publication number 20160155716
- Publication date Jun 2, 2016
- Siliconware Precision Industries Co., Ltd.
- Ming-Chen Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP SUPPORT SUBSTRATE, CHIP SUPPORT METHOD, THREE-DIMENSIONAL INTE...
- Publication number 20150228622
- Publication date Aug 13, 2015
- TOHOKU UNIVERSITY
- Mitsumasa Koyanagi
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Semiconductor device with semiconductor chips mounted on mounting b...
- Publication number 20070267735
- Publication date Nov 22, 2007
- FUJITSU LIMITED
- Yuji Awano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package with heat sink
- Publication number 20040262742
- Publication date Dec 30, 2004
- Tessera, Inc.
- Thomas H. DiStefano
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and system for chip-to-package interconnection
- Publication number 20040241909
- Publication date Dec 2, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Manjula N. Variyam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for providing void-free layers for semiconductor assemblies
- Publication number 20030027373
- Publication date Feb 6, 2003
- Tessera, Inc.
- Thomas H. DiStefano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for providing void-free layers for semiconductor assemblies
- Publication number 20020094671
- Publication date Jul 18, 2002
- Thomas H. Distefano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-out semiconductor chip assembly
- Publication number 20010022396
- Publication date Sep 20, 2001
- Thomas H. Distefano
- H01 - BASIC ELECTRIC ELEMENTS

by means of an encapsulation layer or foil

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Package substrate, semiconductor package and method of manufacturin...

Package structure and its fabrication method

Chip support substrate, chip support method, three-dimensional inte...

Semiconductor device with semiconductor chips mounted on mounting b...

Semiconductor package with heat sink

Method and system for chip-to-package interconnection

Methods for providing void-free layers for semiconductor assemblies

Methods for providing void-free layers for semiconductor assemblies

Method for providing void free layer for semiconductor assemblies

Fan-out semiconductor chip assembly

Methods for providing void-free layers for semiconductor assemblies

Methods for providing void-free layers for semiconductor assemblies

Fan-out semiconductor chip assembly

Patents Applicationslast 30 patents

PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURIN...

CHIP SUPPORT SUBSTRATE, CHIP SUPPORT METHOD, THREE-DIMENSIONAL INTE...

Semiconductor device with semiconductor chips mounted on mounting b...

Semiconductor package with heat sink

Method and system for chip-to-package interconnection

Methods for providing void-free layers for semiconductor assemblies

Methods for providing void-free layers for semiconductor assemblies

Fan-out semiconductor chip assembly