Covering only the peripheral area of the surface to be connected

Industry

CPC
H01L2224/14165

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/14165Covering only the peripheral area of the surface to be connected

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
System in package process flow
- Patent number 10,163,877
- Issue date Dec 25, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tsung-Ding Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus for routing die signals using external interco...
- Patent number 9,871,012
- Issue date Jan 16, 2018
- QUALCOMM Incorporated
- Vaishnav Srinivas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Display device
- Patent number 9,818,771
- Issue date Nov 14, 2017
- Japan Display Inc.
- Yohei Iwai
- G02 - OPTICS
Information Patent Grant
Semiconductor device including asymmetric electrode arrangement
- Patent number 9,585,197
- Issue date Feb 28, 2017
- Samsung Electronics Co., Ltd.
- Chin-sung Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed circuit board and semiconductor package using the same
- Patent number 9,502,341
- Issue date Nov 22, 2016
- Samsung Electronics Co., Ltd.
- Jik-Ho Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package and method thereof
- Patent number 9,373,597
- Issue date Jun 21, 2016
- Xintec Inc.
- Yen-Shih Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming IPD in fan-out wafer lev...
- Patent number 9,343,396
- Issue date May 17, 2016
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire-based methodology of widening the pitch of semiconductor chip...
- Patent number 8,674,504
- Issue date Mar 18, 2014
- Texas Systems Incorporated
- Charles Anthony Odegard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming IPD in fan-out level chi...
- Patent number 8,241,952
- Issue date Aug 14, 2012
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for aligning IC die to package substrate
- Patent number 7,052,968
- Issue date May 30, 2006
- Advanced Micro Devices, Inc.
- Swee Peng Lee
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR ROUTING DIE SIGNALS USING EXTERNAL INTERCO...
- Publication number 20140061642
- Publication date Mar 6, 2014
- QUALCOMM Incorporated
- Vaishnav Srinivas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wire-Based Methodology of Widening the Pitch of Semiconductor Chip...
- Publication number 20130307141
- Publication date Nov 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Charles Anthony Odegard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Lev...
- Publication number 20120267800
- Publication date Oct 25, 2012
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOUNTING STRUCTURE OF CHIP AND MODULE USING THE SAME
- Publication number 20120133042
- Publication date May 31, 2012
- Panasonic Electric Works Co., Ltd.
- Shintarou Hayashi
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Semiconductor Device and Method of Forming IPD in Fan-Out Level Chi...
- Publication number 20110204509
- Publication date Aug 25, 2011
- STATS ChipPAC, Ltd.
- Yaojian Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Chip Package System Vertical Interconnect
- Publication number 20100084755
- Publication date Apr 8, 2010
- Mark Allen Gerber
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR

Covering only the peripheral area of the surface to be connected

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

System in package process flow

Method and apparatus for routing die signals using external interco...

Display device

Semiconductor device including asymmetric electrode arrangement

Printed circuit board and semiconductor package using the same

Chip package and method thereof

Semiconductor device and method of forming IPD in fan-out wafer lev...

Wire-based methodology of widening the pitch of semiconductor chip...

Semiconductor device and method of forming IPD in fan-out level chi...

Method and system for aligning IC die to package substrate

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR ROUTING DIE SIGNALS USING EXTERNAL INTERCO...

Wire-Based Methodology of Widening the Pitch of Semiconductor Chip...

Semiconductor Device and Method of Forming IPD in Fan-Out Wafer Lev...

MOUNTING STRUCTURE OF CHIP AND MODULE USING THE SAME

Semiconductor Device and Method of Forming IPD in Fan-Out Level Chi...

Semiconductor Chip Package System Vertical Interconnect