involving a chemical process

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H01L2224/11831

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

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H01L2224/11831involving a chemical process

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Package structure with a barrier layer
- Patent number 11,984,419
- Issue date May 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Cheng-Hung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure and method for preparing the same
- Patent number 11,973,046
- Issue date Apr 30, 2024
- SJ Semiconductor (Jiangyin) Corporation
- Jiashan Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package structure, chip structure and method for forming chip...
- Patent number 11,894,331
- Issue date Feb 6, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chien-Cheng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 11,502,057
- Issue date Nov 15, 2022
- Kioxia Corporation
- Soichi Homma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming package structure with a barrier layer
- Patent number 11,469,203
- Issue date Oct 11, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Cheng-Hung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect using nanoporous metal locking structures
- Patent number 11,469,199
- Issue date Oct 11, 2022
- Meta Platforms Technologies, LLC
- John Michael Goward
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced adhesive materials and processes for 3D applications
- Patent number 11,168,234
- Issue date Nov 9, 2021
- International Business Machines Corporation
- James L. Hedrick
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for forming bump structure
- Patent number 11,145,613
- Issue date Oct 12, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd
- Li-Guo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D packaging with low-force thermocompression bonding of oxidizable...
- Patent number 11,134,598
- Issue date Sep 28, 2021
- SET North America, LLC
- Eric Frank Schulte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Porous Cu on Cu surface for semiconductor packages
- Patent number 10,914,018
- Issue date Feb 9, 2021
- Infineon Technologies AG
- Norbert Pielmeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packages
- Patent number 10,872,861
- Issue date Dec 22, 2020
- ADVANCED SEMICONDUCTOR ENGINEERING, INC. KAOHSIUNG, TAIWAN
- Yong-Da Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure with a barrier layer and method for forming the same
- Patent number 10,811,377
- Issue date Oct 20, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd
- Cheng-Hung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced adhesive materials and processes for 3D applications
- Patent number 10,767,084
- Issue date Sep 8, 2020
- International Business Machines Corporation
- James L. Hedrick
- B82 - NANO-TECHNOLOGY
Information Patent Grant
High density package interconnects
- Patent number 10,658,279
- Issue date May 19, 2020
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density package interconnects
- Patent number 10,204,851
- Issue date Feb 12, 2019
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bump structure and method for forming the same
- Patent number 10,090,267
- Issue date Oct 2, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Li-Guo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density package interconnects
- Patent number 9,922,916
- Issue date Mar 20, 2018
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper pillar sidewall protection
- Patent number 9,875,980
- Issue date Jan 23, 2018
- Amkor Technology, Inc.
- Glenn Rinne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with embedded die and its methods of fabrication
- Patent number 9,780,054
- Issue date Oct 3, 2017
- Intel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Improving the strength of micro-bump joints
- Patent number 9,768,138
- Issue date Sep 19, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Wei Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power semiconductor device with a double metal contact and related...
- Patent number 9,761,550
- Issue date Sep 12, 2017
- Infineon Technologies Americas Corp.
- Robert Montgomery
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method of manufacturing the same
- Patent number 9,698,028
- Issue date Jul 4, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Hsiung Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure to prevent solder extrusion
- Patent number 9,613,921
- Issue date Apr 4, 2017
- GLOBALFOUNDRIES Inc.
- Timothy H. Daubenspeck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of manufactures
- Patent number 9,583,420
- Issue date Feb 28, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jing-Cheng Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaging structures and methods with a metal pillar
- Patent number 9,508,666
- Issue date Nov 29, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bump structures in semiconductor packages and methods of fabricatin...
- Patent number 9,437,563
- Issue date Sep 6, 2016
- SK hynix Inc.
- Taek Joong Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Treating copper surfaces for packaging
- Patent number 9,425,180
- Issue date Aug 23, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chih-Horng Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming interconnect structure w...
- Patent number 9,373,578
- Issue date Jun 21, 2016
- STATS ChipPAC Pte. Ltd.
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low fabrication cost, high performance, high reliability chip scale...
- Patent number 9,369,175
- Issue date Jun 14, 2016
- QUALCOMM Incorporated
- Jin-Yuan Lee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method of forming bump pad structure having buffer pattern
- Patent number 9,368,465
- Issue date Jun 14, 2016
- Samsung Electronics Co., Ltd.
- Soo-Jae Park
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUITS WITH CONDUCTIVE POSTS HAVING ROUGH SIDEWALLS
- Publication number 20240363570
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Jose Daniel Carlos Torres
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE WITH A BARRIER LAYER
- Publication number 20240297138
- Publication date Sep 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheng-Hung CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALLOY FOR METAL UNDERCUT REDUCTION
- Publication number 20240290735
- Publication date Aug 29, 2024
- TEXAS INSTRUMENTS INCORPORATED
- RAFAEL JOSE GUEVARA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE AND CHIP STRUCTURE
- Publication number 20240178173
- Publication date May 30, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chien-Cheng CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED METAL PADS
- Publication number 20240088072
- Publication date Mar 14, 2024
- Micron Technology, Inc.
- Tsung Han Chiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH ELECTRICAL CONTACTS ON MULTIPLE SUR...
- Publication number 20230395549
- Publication date Dec 7, 2023
- Hewlett-Packard Development Company, L.P.
- DAVID WAYNE GEORGE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
- Publication number 20230307419
- Publication date Sep 28, 2023
- KIOXIA Corporation
- Soichi HOMMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE HAVING CHEMICALLY COATED BUMP BONDS
- Publication number 20230123307
- Publication date Apr 20, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Nazila Dadvand
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE, CHIP STRUCTURE AND METHOD FOR FORMING CHIP...
- Publication number 20230060457
- Publication date Mar 2, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chien-Cheng CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE WITH A BARRIER LAYER AND METHOD FOR MANUFACTURING...
- Publication number 20220367398
- Publication date Nov 17, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheng-Hung CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME
- Publication number 20220077092
- Publication date Mar 10, 2022
- SJ Semiconductor(Jiangyin) Corporation
- Jiashan Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW TEMPERATURE DIRECT COPPER-COPPER BONDING
- Publication number 20220018036
- Publication date Jan 20, 2022
- LAM RESEARCH CORPORATION
- Stephen J. Banik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20210257332
- Publication date Aug 19, 2021
- KIOXIA Corporation
- Soichi HOMMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT USING NANOPOROUS METAL LOCKING STRUCTURES
- Publication number 20210098402
- Publication date Apr 1, 2021
- Facebook Technologies, LLC
- John Michael Goward
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING PACKAGE STRUCTURE WITH A BARRIER LAYER
- Publication number 20210035937
- Publication date Feb 4, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Cheng-Hung CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Porous Cu on Cu Surface for Semiconductor Packages
- Publication number 20200291538
- Publication date Sep 17, 2020
- INFINEON TECHNOLOGIES AG
- Norbert Pielmeier
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
SEMICONDUCTOR DEVICE WITH ELECTROPLATED COPPER STRUCTURES
- Publication number 20200286844
- Publication date Sep 10, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Keith Edward Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT USING NANOPOROUS METAL LOCKING STRUCTURES
- Publication number 20190237420
- Publication date Aug 1, 2019
- Facebook Technologies, LLC
- John Michael Goward
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING A BUMP STRUCTURE AND METHOD FOR MANUFAC...
- Publication number 20190214357
- Publication date Jul 11, 2019
- Chipbond Technology Corporation
- Chun-Te Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY PACKAGE INTERCONNECTS
- Publication number 20190172778
- Publication date Jun 6, 2019
- Intel Corporation
- Sanka GANESAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING BUMP STRUCTURE
- Publication number 20190019772
- Publication date Jan 17, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Li-Guo LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED ADHESIVE MATERIALS AND PROCESSES FOR 3D APPLICATIONS
- Publication number 20180340100
- Publication date Nov 29, 2018
- International Business Machines Corporation
- James L. Hedrick
- B82 - NANO-TECHNOLOGY
Information Patent Application
HIGH DENSITY PACKAGE INTERCONNECTS
- Publication number 20180182696
- Publication date Jun 28, 2018
- Intel Corporation
- Sanka GANESAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermocompression Bonding with Passivated Gold Contacting Metal
- Publication number 20180132397
- Publication date May 10, 2018
- SET NORTH AMERICA, LLC
- Eric Frank Schulte
- B32 - LAYERED PRODUCTS
Information Patent Application
Thermocompression Bonding with Passivated Silver-Based Contacting M...
- Publication number 20180132398
- Publication date May 10, 2018
- SET NORTH AMERICA, LLC
- Eric Frank Schulte
- B32 - LAYERED PRODUCTS
Information Patent Application
Thermocompression Bonding with Passivated Indium-Based Contacting M...
- Publication number 20180132395
- Publication date May 10, 2018
- SET NORTH AMERICA, LLC
- Eric Frank Schulte
- B32 - LAYERED PRODUCTS
Information Patent Application
Thermocompression Bonding with Passivated Copper-Based Contacting M...
- Publication number 20180132396
- Publication date May 10, 2018
- SET NORTH AMERICA, LLC
- Eric Frank Schulte
- B32 - LAYERED PRODUCTS
Information Patent Application
Thermocompression Bonding Using Metastable Gas Atoms
- Publication number 20180132394
- Publication date May 10, 2018
- SET NORTH AMERICA, LLC
- Eric Frank Schulte
- B32 - LAYERED PRODUCTS
Information Patent Application
System for Low-Force Thermocompression Bonding
- Publication number 20180132393
- Publication date May 10, 2018
- SET NORTH AMERICA, LLC
- Eric Frank Schulte
- B32 - LAYERED PRODUCTS
Information Patent Application
Thermocompression Bonding with Passivated Nickel-Based Contacting M...
- Publication number 20180132399
- Publication date May 10, 2018
- SET NORTH AMERICA, LLC
- Eric Frank Schulte
- B32 - LAYERED PRODUCTS

involving a chemical process

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Package structure with a barrier layer

Semiconductor structure and method for preparing the same

Chip package structure, chip structure and method for forming chip...

Semiconductor device and manufacturing method thereof

Method for forming package structure with a barrier layer

Interconnect using nanoporous metal locking structures

Enhanced adhesive materials and processes for 3D applications

Method for forming bump structure

3D packaging with low-force thermocompression bonding of oxidizable...

Porous Cu on Cu surface for semiconductor packages

Semiconductor packages

Package structure with a barrier layer and method for forming the same

Enhanced adhesive materials and processes for 3D applications

High density package interconnects

High density package interconnects

Bump structure and method for forming the same

High density package interconnects

Copper pillar sidewall protection

Semiconductor package with embedded die and its methods of fabrication

Improving the strength of micro-bump joints

Power semiconductor device with a double metal contact and related...

Semiconductor package and method of manufacturing the same

Structure to prevent solder extrusion

Semiconductor device and method of manufactures

Packaging structures and methods with a metal pillar

Bump structures in semiconductor packages and methods of fabricatin...

Treating copper surfaces for packaging

Semiconductor device and method of forming interconnect structure w...

Low fabrication cost, high performance, high reliability chip scale...

Method of forming bump pad structure having buffer pattern

Patents Applicationslast 30 patents

INTEGRATED CIRCUITS WITH CONDUCTIVE POSTS HAVING ROUGH SIDEWALLS

PACKAGE STRUCTURE WITH A BARRIER LAYER

ALLOY FOR METAL UNDERCUT REDUCTION

CHIP PACKAGE STRUCTURE AND CHIP STRUCTURE

EMBEDDED METAL PADS

INTEGRATED CIRCUIT DEVICES WITH ELECTRICAL CONTACTS ON MULTIPLE SUR...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

ELECTRONIC DEVICE HAVING CHEMICALLY COATED BUMP BONDS

CHIP PACKAGE STRUCTURE, CHIP STRUCTURE AND METHOD FOR FORMING CHIP...

PACKAGE STRUCTURE WITH A BARRIER LAYER AND METHOD FOR MANUFACTURING...

SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME

LOW TEMPERATURE DIRECT COPPER-COPPER BONDING

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

INTERCONNECT USING NANOPOROUS METAL LOCKING STRUCTURES

METHOD FOR FORMING PACKAGE STRUCTURE WITH A BARRIER LAYER

Porous Cu on Cu Surface for Semiconductor Packages

SEMICONDUCTOR DEVICE WITH ELECTROPLATED COPPER STRUCTURES

INTERCONNECT USING NANOPOROUS METAL LOCKING STRUCTURES

SEMICONDUCTOR DEVICE HAVING A BUMP STRUCTURE AND METHOD FOR MANUFAC...

HIGH DENSITY PACKAGE INTERCONNECTS

METHOD FOR FORMING BUMP STRUCTURE

ENHANCED ADHESIVE MATERIALS AND PROCESSES FOR 3D APPLICATIONS

HIGH DENSITY PACKAGE INTERCONNECTS

Thermocompression Bonding with Passivated Gold Contacting Metal

Thermocompression Bonding with Passivated Silver-Based Contacting M...

Thermocompression Bonding with Passivated Indium-Based Contacting M...

Thermocompression Bonding with Passivated Copper-Based Contacting M...

Thermocompression Bonding Using Metastable Gas Atoms

System for Low-Force Thermocompression Bonding

Thermocompression Bonding with Passivated Nickel-Based Contacting M...