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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/2512Layout

Industries

Patents Grantslast 30 patents

Information Patent Grant
High density substrate routing in package
- Patent number 12,051,667
- Issue date Jul 30, 2024
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Display device
- Patent number 11,855,055
- Issue date Dec 26, 2023
- Samsung Display Co., Ltd.
- Seung Lyong Bok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Display device
- Patent number 11,848,335
- Issue date Dec 19, 2023
- Samsung Display Co., Ltd.
- Won Sik Oh
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
High density substrate routing in package
- Patent number 11,810,884
- Issue date Nov 7, 2023
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 11,251,150
- Issue date Feb 15, 2022
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method of fabricating semiconductor package
- Patent number 11,031,371
- Issue date Jun 8, 2021
- SanDisk Information Technology (Shanghai) Co., Ltd.
- Chin Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Organic interposers for integrated circuit packages
- Patent number 10,998,272
- Issue date May 4, 2021
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 10,861,815
- Issue date Dec 8, 2020
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package structure having a second encapsulant extendi...
- Patent number 10,510,705
- Issue date Dec 17, 2019
- Advanced Semiconductor Engineering, Inc.
- Wen-Long Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 10,438,915
- Issue date Oct 8, 2019
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor package
- Patent number 10,340,259
- Issue date Jul 2, 2019
- Mediatek Inc.
- Shiann-Tsong Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in package
- Patent number 10,199,346
- Issue date Feb 5, 2019
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in BBUL package
- Patent number 9,929,119
- Issue date Mar 27, 2018
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in BBUL package
- Patent number 9,437,569
- Issue date Sep 6, 2016
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate routing in BBUL package
- Patent number 9,171,816
- Issue date Oct 27, 2015
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip assembly having via interconnects joined by plating
- Patent number 8,685,793
- Issue date Apr 1, 2014
- Tessera, Inc.
- Vage Oganesian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,653,639
- Issue date Feb 18, 2014
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite layered chip package
- Patent number 8,426,979
- Issue date Apr 23, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layered chip package and method of manufacturing same
- Patent number 8,358,015
- Issue date Jan 22, 2013
- Headway Technologies, Inc.
- Yoshitaka Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with pattern leads and method for manufacturi...
- Patent number 7,061,125
- Issue date Jun 13, 2006
- Samsung Electronics, Co. Ltd.
- Sung-Dae Cho
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
- Publication number 20240339428
- Publication date Oct 10, 2024
- Intel Corporation
- Weng Hong TEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE
- Publication number 20240170433
- Publication date May 23, 2024
- LG ELECTRONICS INC.
- Bongseok CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER TO WAFER HIGH DENSITY INTERCONNECTS
- Publication number 20230207523
- Publication date Jun 29, 2023
- International Business Machines Corporation
- Timothy J. Chainer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LIGHT-EMITTING DIODE AND DISPLAY DEVICE COMPRISING SAME
- Publication number 20230006095
- Publication date Jan 5, 2023
- SAMSUNG DISPLAY CO., LTD.
- Hoo Keun PARK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIVERSAL HYBRID BONDING SURFACE LAYER USING AN ADAPTABLE INTERCONN...
- Publication number 20220415839
- Publication date Dec 29, 2022
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ORGANIC INTERPOSERS FOR INTEGRATED CIRCUIT PACKAGES
- Publication number 20210082822
- Publication date Mar 18, 2021
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO ELECTRICALLY CONNECT CHIP WITH TOP CONNECTORS USING 3D PR...
- Publication number 20200350275
- Publication date Nov 5, 2020
- IO TECH GROUP LTD.
- Michael Zenou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
- Publication number 20190393180
- Publication date Dec 26, 2019
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20190206824
- Publication date Jul 4, 2019
- Advanced Semiconductor Engineering, Inc.
- Wen-Long LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
- Publication number 20180145047
- Publication date May 24, 2018
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE
- Publication number 20170053887
- Publication date Feb 23, 2017
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE
- Publication number 20160079196
- Publication date Mar 17, 2016
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE
- Publication number 20150194406
- Publication date Jul 9, 2015
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE
- Publication number 20140159228
- Publication date Jun 12, 2014
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING
- Publication number 20140131892
- Publication date May 15, 2014
- Tessera, Inc.
- Vage Oganesian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPOSITE LAYERED CHIP PACKAGE
- Publication number 20130020723
- Publication date Jan 24, 2013
- SAE MAGNETICS (H. K) LTD.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120313260
- Publication date Dec 13, 2012
- HEADWAY TECHNOLOGIES, INC.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20120313259
- Publication date Dec 13, 2012
- SAE Magnetics (H.K.) Ltd.
- Yoshitaka SASAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layered Integrated Circuit Apparatus
- Publication number 20120091595
- Publication date Apr 19, 2012
- MAO BANG ELECTRONIC CO., LTD.
- Sung Chuan MA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING
- Publication number 20120068351
- Publication date Mar 22, 2012
- Tessera Research LLC
- Vage Oganesian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package with pattern leads and method for manufacturi...
- Publication number 20040155322
- Publication date Aug 12, 2004
- Sung-Dae Cho
- H01 - BASIC ELECTRIC ELEMENTS

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

High density substrate routing in package

Display device

Display device

High density substrate routing in package

High density substrate routing in package

Semiconductor package and method of fabricating semiconductor package

Organic interposers for integrated circuit packages

High density substrate routing in package

Semiconductor package structure having a second encapsulant extendi...

High density substrate routing in package

Method for fabricating a semiconductor package

High density substrate routing in package

High density substrate routing in BBUL package

High density substrate routing in BBUL package

High density substrate routing in BBUL package

Chip assembly having via interconnects joined by plating

Layered chip package and method of manufacturing same

Composite layered chip package

Layered chip package and method of manufacturing same

Semiconductor package with pattern leads and method for manufacturi...

Patents Applicationslast 30 patents

HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE

LIGHT EMITTING DEVICE PACKAGE AND DISPLAY DEVICE

WAFER TO WAFER HIGH DENSITY INTERCONNECTS

LIGHT-EMITTING DIODE AND DISPLAY DEVICE COMPRISING SAME

UNIVERSAL HYBRID BONDING SURFACE LAYER USING AN ADAPTABLE INTERCONN...

ORGANIC INTERPOSERS FOR INTEGRATED CIRCUIT PACKAGES

METHOD TO ELECTRICALLY CONNECT CHIP WITH TOP CONNECTORS USING 3D PR...

HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE

HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE

HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE

HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE

HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE

CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING

COMPOSITE LAYERED CHIP PACKAGE

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME

Layered Integrated Circuit Apparatus

CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING

Semiconductor package with pattern leads and method for manufacturi...