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Y10S148/103

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YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S148/00Metal treatment

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Y10S148/103Mask, dual function

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Patents Grantslast 30 patents

Information Patent Grant
Method of producing sheets of crystalline material and devices made...
- Patent number 5,676,752
- Issue date Oct 14, 1997
- Massachusetts Institute of Technology
- Carl O. Bozler
- C30 - CRYSTAL GROWTH
Information Patent Grant
Method of producing sheets of crystalline material and devices made...
- Patent number 5,362,682
- Issue date Nov 8, 1994
- Massachusetts Institute of Technology
- Carl O. Bozler
- C30 - CRYSTAL GROWTH
Information Patent Grant
Silicide interconnection with Schottky barrier diode isolation
- Patent number 5,336,637
- Issue date Aug 9, 1994
- International Business Machines Corporation
- Edward J. Nowak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bright field wafer target
- Patent number 5,316,984
- Issue date May 31, 1994
- VLSI Technology, Inc.
- Pierre Leourx
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Self-aligned low resistance buried contact process
- Patent number 5,292,676
- Issue date Mar 8, 1994
- Micron Semiconductor, Inc.
- Monte Manning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid circuit structures and methods of fabrication
- Patent number 5,282,922
- Issue date Feb 1, 1994
- Polycon Corporation
- John J. Reche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single mask process for forming both n-type and p-type gates in a p...
- Patent number 5,278,085
- Issue date Jan 11, 1994
- Micron Semiconductor, Inc.
- Roy L. Maddox
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide interconnection with schottky barrier diode isolation
- Patent number 5,250,834
- Issue date Oct 5, 1993
- International Business Machines Corporation
- Edward J. Nowak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor device with reduced packaging...
- Patent number 5,171,716
- Issue date Dec 15, 1992
- North American Philips Corp.
- Myron R. Cagan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing minimum counterdoping in twin well process
- Patent number 5,132,241
- Issue date Jul 21, 1992
- Industrial Technology Research Institute
- Wen-Doe Su
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor optoelectric integrated cir...
- Patent number 5,051,372
- Issue date Sep 24, 1991
- Sumitomo Electric Industries, Ltd.
- Goro Sasaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etched back edge isolation process for heterojunction bipolar trans...
- Patent number 5,028,549
- Issue date Jul 2, 1991
- Rockwell International
- Mau-Chung F. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing process for high-frequency bipolar transistors
- Patent number 5,013,672
- Issue date May 7, 1991
- SGS Thomson Microelectronics S.r.l.
- Raffaele Zambrano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making a self aligned vertical field effect transistor...
- Patent number 4,960,723
- Issue date Oct 2, 1990
- Motorola, Inc.
- Robert B. Davies
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a DMOS
- Patent number 4,879,254
- Issue date Nov 7, 1989
- Nippondenso Co., Ltd.
- Yukio Tsuzuki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making twin tub CMOS devices
- Patent number 4,806,501
- Issue date Feb 21, 1989
- SGS Microelettronica S.p.A.
- Livio Baldi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device
- Patent number 4,689,872
- Issue date Sep 1, 1987
- U.S. Philips Corporation
- Johannes A. Appels
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device utilizing self-alig...
- Patent number 4,591,398
- Issue date May 27, 1986
- Sony Corporation
- Norikazu Ouchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and process for manufacturing the same
- Patent number 4,557,036
- Issue date Dec 10, 1985
- Nippon Telegraph and Telephone Public Corp.
- Hakaru Kyuragi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of making composite conductive structures in integrated cir...
- Patent number 4,227,944
- Issue date Oct 14, 1980
- General Electric Company
- Dale M. Brown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite conductive structures in integrated circuits
- Patent number 4,228,212
- Issue date Oct 14, 1980
- General Electric Company
- Dale M. Brown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistors with polycrystalline silicon gate self-ali...
- Patent number 4,160,987
- Issue date Jul 10, 1979
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a MOS device
- Patent number 4,113,533
- Issue date Sep 12, 1978
- Matsushita Electronics Corporation
- Tomisaburo Okumura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor field effort transistor
- Patent number 3,967,981
- Issue date Jul 6, 1976
- Shumpei Yamazaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of producing semiconductor devices
- Patent number 3,966,501
- Issue date Jun 29, 1976
- Mitsubishi Denki Kabushiki Kaisha
- Kousi Nomura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three mask self aligned IGFET fabrication process
- Patent number 3,958,323
- Issue date May 25, 1976
- International Business Machines Corporation
- Francisco H. De La Moneda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including a conductor surrounded by an insulator
- Patent number 3,936,859
- Issue date Feb 3, 1976
- RCA Corporation
- Andrew Gordon Francis Dingwall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3881242
- Patent number 3,881,242
- Issue date May 6, 1975
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3755001
- Patent number 3,755,001
- Issue date Aug 28, 1973
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3752711
- Patent number 3,752,711
- Issue date Aug 14, 1973
- H01 - BASIC ELECTRIC ELEMENTS

Mask, dual function

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method of producing sheets of crystalline material and devices made...

Method of producing sheets of crystalline material and devices made...

Silicide interconnection with Schottky barrier diode isolation

Bright field wafer target

Self-aligned low resistance buried contact process

Hybrid circuit structures and methods of fabrication

Single mask process for forming both n-type and p-type gates in a p...

Silicide interconnection with schottky barrier diode isolation

Method of manufacturing semiconductor device with reduced packaging...

Method of manufacturing minimum counterdoping in twin well process

Method of manufacturing a semiconductor optoelectric integrated cir...

Etched back edge isolation process for heterojunction bipolar trans...

Manufacturing process for high-frequency bipolar transistors

Process for making a self aligned vertical field effect transistor...

Method of manufacturing a DMOS

Method for making twin tub CMOS devices

Method of manufacturing a semiconductor device

Method for manufacturing a semiconductor device utilizing self-alig...

Semiconductor device and process for manufacturing the same

Methods of making composite conductive structures in integrated cir...

Composite conductive structures in integrated circuits

Field effect transistors with polycrystalline silicon gate self-ali...

Method of making a MOS device

Method for manufacturing a semiconductor field effort transistor

Process of producing semiconductor devices

Three mask self aligned IGFET fabrication process

Semiconductor device including a conductor surrounded by an insulator

3881242

3755001

3752711

Patents Applicationslast 30 patents