of patterns for devices arranged in a network

Industry

CPC
G01R31/318378

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Parent Industries

GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Current Industry

G01R31/318378of patterns for devices arranged in a network

Industries

Patents Grantslast 30 patents

Information Patent Grant
Method and device for testing system-on-chip, electronic device usi...
- Patent number 11,846,672
- Issue date Dec 19, 2023
- Hon Hai Precision Industry Co., Ltd.
- Jun-Kui Huang
- G01 - MEASURING TESTING
Information Patent Grant
Equivalent time network analyzer
- Patent number 11,016,146
- Issue date May 25, 2021
- Massachusetts Institute of Technology
- Eric Judson VanWyk
- G01 - MEASURING TESTING
Information Patent Grant
Test network for a network on a chip and a configuration network
- Patent number 10,502,785
- Issue date Dec 10, 2019
- Xilinx, Inc.
- Rafael C. Camarota
- G01 - MEASURING TESTING
Information Patent Grant
Panel driving circuit that generates panel test pattern and panel t...
- Patent number 8,972,811
- Issue date Mar 3, 2015
- Samsung Electronics Co., Ltd.
- Won-Sik Kang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Panel driving circuit that generates panel test pattern and panel t...
- Patent number 8,621,306
- Issue date Dec 31, 2013
- Samsung Electronics Co., Ltd.
- Won-Sik Kang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Panel driving circuit that generates panel test pattern and panel t...
- Patent number 8,055,968
- Issue date Nov 8, 2011
- Samsung Electronics Co., Ltd.
- Won-Sik Kang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Panel driving circuit that generates panel test pattern and panel t...
- Patent number 7,627,799
- Issue date Dec 1, 2009
- Samsung Electronics Co., Ltd.
- Won-Sik Kang
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Testing system and method of using same
- Patent number 7,401,271
- Issue date Jul 15, 2008
- EMC Corporation
- Christopher S. MacLellan
- G11 - INFORMATION STORAGE
Information Patent Grant
Verification environment creation infrastructure for bus-based syst...
- Patent number 7,315,803
- Issue date Jan 1, 2008
- Xilinx, Inc.
- Jorge Ernesto Carrillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measuring microprocessor susceptibility to internal noise generation
- Patent number 7,313,747
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Sungjun Chun
- G01 - MEASURING TESTING
Information Patent Grant
Single-pass methods for generating test patterns for sequential cir...
- Patent number 7,231,571
- Issue date Jun 12, 2007
- Yardstick Research, L.L.C.
- Delmas R. Buckley, Jr.
- G01 - MEASURING TESTING
Information Patent Grant
Generating an abbreviated netlist including pseudopin inputs and ou...
- Patent number 7,203,880
- Issue date Apr 10, 2007
- Texas Instruments Incorporated
- Srinivasa Chakravarthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary scan analysis
- Patent number 7,188,043
- Issue date Mar 6, 2007
- Xilinx, Inc.
- Mikhail A. Wolf
- G01 - MEASURING TESTING
Information Patent Grant
Identifying specific netlist gates for use in code coverage testing
- Patent number 7,117,458
- Issue date Oct 3, 2006
- Unisys Corporation
- Steven T Hurlock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in functional tester for search engines
- Patent number 7,082,561
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Alexander E. Andreev
- G01 - MEASURING TESTING
Information Patent Grant
Scan insertion with bypass login in an IC design
- Patent number 6,973,631
- Issue date Dec 6, 2005
- Incentia Design Systems Corp.
- Steve C. Huang
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for modeling and circuits with asynchronous be...
- Patent number 6,973,422
- Issue date Dec 6, 2005
- Intel Corporation
- Sitaram Yadavalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced fault coverage
- Patent number 6,745,358
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Daniel R. Watkins
- G01 - MEASURING TESTING
Information Patent Grant
Generating netlist test vectors by stripping references to a pseudo...
- Patent number 6,697,982
- Issue date Feb 24, 2004
- Texas Instruments Incorporated
- Srinivasa Chakravarthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated system for inserting and reading of probe points in silic...
- Patent number 6,654,919
- Issue date Nov 25, 2003
- LSI Logic Corporation
- Daniel Watkins
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to descramble the data mapping in memory circuits
- Patent number 6,601,205
- Issue date Jul 29, 2003
- Infineon Technologies AG
- Gunther Lehmann
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to improve a testability analysis of a hierarchical design
- Patent number 6,532,571
- Issue date Mar 11, 2003
- International Business Machines Corporation
- Richard M. Gabrielson
- G01 - MEASURING TESTING
Information Patent Grant
METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL...
- Patent number 6,470,482
- Issue date Oct 22, 2002
- LSI Logic Corporation
- Michael D. Rostoker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for creating and validating low level description...
- Patent number 6,324,678
- Issue date Nov 27, 2001
- LSI Logic Corporation
- Carlos Dangelo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated test vector generation and verification
- Patent number 6,304,837
- Issue date Oct 16, 2001
- Adaptec, Inc.
- Thomas Kennith Geiger
- G01 - MEASURING TESTING
Information Patent Grant
Insertion of test points in RTL designs
- Patent number 6,301,688
- Issue date Oct 9, 2001
- Agere Systems Optoelectronics Guardian Corp.
- Subrata Roy
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for automatically determining transparency behavi...
- Patent number 6,269,463
- Issue date Jul 31, 2001
- Synopsys, Inc.
- Suryanarayana Duggirala
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for transforming scan-based sequential circuits w...
- Patent number 6,195,776
- Issue date Feb 27, 2001
- Synopsys, Inc.
- Robert Ruiz
- G01 - MEASURING TESTING
Information Patent Grant
Method for improving fault coverage of an electric circuit
- Patent number 6,059,451
- Issue date May 9, 2000
- Texas Instruments Incorporated
- Kyl W. Scott
- G01 - MEASURING TESTING
Information Patent Grant
Identification and test generation for primitive faults
- Patent number 6,018,813
- Issue date Jan 25, 2000
- NEC USA, Inc.
- Srimat T. Chakradhar
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Equivalent Time Network Analyzer
- Publication number 20180284191
- Publication date Oct 4, 2018
- Massachusetts Institute of Technology
- Eric Judson VanWyk
- G01 - MEASURING TESTING
Information Patent Application
PANEL DRIVING CIRCUIT THAT GENERATES PANEL TEST PATTERN AND PANEL T...
- Publication number 20140089753
- Publication date Mar 27, 2014
- Samsung Electronics Co., Ltd.
- Won-Sik Kang
- G01 - MEASURING TESTING
Information Patent Application
Panel Driving Circuit That Generates Panel Test Pattern and Panel T...
- Publication number 20120072773
- Publication date Mar 22, 2012
- Won-Sik Kang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Panel Driving Circuit That Generates Panel Test Pattern and Panel T...
- Publication number 20110219278
- Publication date Sep 8, 2011
- Won-Sik Kang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Panel Driving Circuit that Generates Panel Test Pattern and Panel T...
- Publication number 20100053334
- Publication date Mar 4, 2010
- Won-Sik Kang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACT...
- Publication number 20090235130
- Publication date Sep 17, 2009
- International Business Machines Corporation
- Brian J. Cagno
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generating scan test vectors for proprietary cores using pseudo pins
- Publication number 20070288797
- Publication date Dec 13, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Chakravarthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Measuring microprocessor susceptibility to internal noise generation
- Publication number 20070236299
- Publication date Oct 11, 2007
- Sungjun Chun
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR TESTING A NAS
- Publication number 20070011545
- Publication date Jan 11, 2007
- HON HAI Precision Industry CO., LTD.
- CHAO-TSUNG FAN
- G01 - MEASURING TESTING
Information Patent Application
Panel driving circuit that generates panel test pattern and panel t...
- Publication number 20050168458
- Publication date Aug 4, 2005
- SAMSUNG ELECTRONICS CO., LTD.
- Won-Sik Kang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Single-Pass Methods for Generating Test Patterns for Sequential Cir...
- Publication number 20050166114
- Publication date Jul 28, 2005
- YARDSTICK RESEARCH, LLC
- Delmas R. Buckley
- G01 - MEASURING TESTING
Information Patent Application
Generating test patterns for testing an integrated circuit
- Publication number 20040187060
- Publication date Sep 23, 2004
- John G. Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Application
Using pseudo-pins in generating scan test vectors for testing an em...
- Publication number 20040158789
- Publication date Aug 12, 2004
- Srinivasa Chakravarthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan insertion with bypass login in an IC design
- Publication number 20040015788
- Publication date Jan 22, 2004
- Steve C. Huang
- G01 - MEASURING TESTING
Information Patent Application
Built-in functional tester for search engines
- Publication number 20030204799
- Publication date Oct 30, 2003
- Alexander E. Andreev
- G01 - MEASURING TESTING
Information Patent Application
Method, apparatus and computer product to organize data on a displa...
- Publication number 20030160826
- Publication date Aug 28, 2003
- SUN MICROSYSTEMS, INC.
- Trung M. Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using pseudo-pins in generating scan test vectors for testing an em...
- Publication number 20030014703
- Publication date Jan 16, 2003
- Srinivasa Chakravarthy
- G01 - MEASURING TESTING

of patterns for devices arranged in a network

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method and device for testing system-on-chip, electronic device usi...

Equivalent time network analyzer

Test network for a network on a chip and a configuration network

Panel driving circuit that generates panel test pattern and panel t...

Panel driving circuit that generates panel test pattern and panel t...

Panel driving circuit that generates panel test pattern and panel t...

Panel driving circuit that generates panel test pattern and panel t...

Testing system and method of using same

Verification environment creation infrastructure for bus-based syst...

Measuring microprocessor susceptibility to internal noise generation

Single-pass methods for generating test patterns for sequential cir...

Generating an abbreviated netlist including pseudopin inputs and ou...

Boundary scan analysis

Identifying specific netlist gates for use in code coverage testing

Built-in functional tester for search engines

Scan insertion with bypass login in an IC design

Method and apparatus for modeling and circuits with asynchronous be...

Enhanced fault coverage

Generating netlist test vectors by stripping references to a pseudo...

Automated system for inserting and reading of probe points in silic...

Method to descramble the data mapping in memory circuits

Method to improve a testability analysis of a hierarchical design

METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL...

Method and system for creating and validating low level description...

Automated test vector generation and verification

Insertion of test points in RTL designs

Method and system for automatically determining transparency behavi...

Method and system for transforming scan-based sequential circuits w...

Method for improving fault coverage of an electric circuit

Identification and test generation for primitive faults

Patents Applicationslast 30 patents

Equivalent Time Network Analyzer

PANEL DRIVING CIRCUIT THAT GENERATES PANEL TEST PATTERN AND PANEL T...

Panel Driving Circuit That Generates Panel Test Pattern and Panel T...

Panel Driving Circuit That Generates Panel Test Pattern and Panel T...

Panel Driving Circuit that Generates Panel Test Pattern and Panel T...

TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACT...

Generating scan test vectors for proprietary cores using pseudo pins

Measuring microprocessor susceptibility to internal noise generation

SYSTEM AND METHOD FOR TESTING A NAS

Panel driving circuit that generates panel test pattern and panel t...

Single-Pass Methods for Generating Test Patterns for Sequential Cir...

Generating test patterns for testing an integrated circuit

Using pseudo-pins in generating scan test vectors for testing an em...

Scan insertion with bypass login in an IC design

Built-in functional tester for search engines

Method, apparatus and computer product to organize data on a displa...

Using pseudo-pins in generating scan test vectors for testing an em...