Read-write (R-W) circuits

Industry

CPC
G11C11/409

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

Current Industry

G11C11/409Read-write (R-W) circuits

Industries

Patents Grantslast 30 patents

Information Patent Grant
Circuitry borrowing for memory arrays
- Patent number 12,340,832
- Issue date Jun 24, 2025
- Micron Technology, Inc.
- Andrea Martinelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Recognition system and SRAM cell thereof
- Patent number 12,340,837
- Issue date Jun 24, 2025
- NCKU Research and Development Foundation
- Wei-Li He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaling out architecture for dram-based processing unit (DPU)
- Patent number 12,340,101
- Issue date Jun 24, 2025
- Samsung Electronics Co., Ltd.
- Dimin Niu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for performing read protection operation of limiting...
- Patent number 12,340,836
- Issue date Jun 24, 2025
- SK hynix Inc.
- Byung Goo Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory devices having adjustable I/O signal line load...
- Patent number 12,334,140
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Seung-Jun Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Write timing compensation
- Patent number 12,334,141
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having merged banks on substrate, and method for oper...
- Patent number 12,334,139
- Issue date Jun 17, 2025
- AP Memory Technology Corporation
- Wenliang Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Sacrificial strings in a memory device to detect read disturb
- Patent number 12,334,142
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Independent multi-page read operation enhancement technology
- Patent number 12,334,136
- Issue date Jun 17, 2025
- SK Hynix NAND Product Solutions Corp.
- Naveen Prabhu Vittal Prabhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maximum memory clock estimation procedures
- Patent number 12,334,137
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Erik V. Pohlmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit line sense amplifier of semiconductor memory device and semicon...
- Patent number 12,327,584
- Issue date Jun 10, 2025
- Samsung Electronics Co., Ltd.
- Donggeon Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid volatile and non-volatile memory device
- Patent number 12,327,590
- Issue date Jun 10, 2025
- RAMBUS INC.
- Scott C. Best
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for refresh of memory devices
- Patent number 12,322,432
- Issue date Jun 3, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hiroki Noguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Power and performance optimization in a memory subsystem
- Patent number 12,322,433
- Issue date Jun 3, 2025
- Intel Corporation
- Vijay Anand Mathiyalagan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory package and a memory module including the memory package
- Patent number 12,322,436
- Issue date Jun 3, 2025
- SK Hynix Inc.
- Won Ha Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with read circuit for compute-in-memory
- Patent number 12,322,435
- Issue date Jun 3, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chieh Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory devices, operating methods thereof and memory sy...
- Patent number 12,322,457
- Issue date Jun 3, 2025
- Samsung Electronics Co., Ltd.
- Sun-Il Shim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory chip and memory system including the same
- Patent number 12,322,437
- Issue date Jun 3, 2025
- Samsung Electronics Co., Ltd.
- Kwangsook Noh
- G11 - INFORMATION STORAGE
Information Patent Grant
Vehicle memory system based on 3D memory and method operating thereof
- Patent number 12,322,463
- Issue date Jun 3, 2025
- Hyundai Motor Company
- Hong Yeol Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method for manufacturing the same
- Patent number 12,315,556
- Issue date May 27, 2025
- NANYA TECHNOLOGY CORPORATION
- Kuo-Chiang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor element memory device
- Patent number 12,315,558
- Issue date May 27, 2025
- Unisantis Electronics Singapore Pte. Ltd.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor-element-including memory device
- Patent number 12,315,544
- Issue date May 27, 2025
- Unisantis Electronics Singapore Pte. Ltd.
- Koji Sakui
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal control circuit, signal control method for blocking activati...
- Patent number 12,315,546
- Issue date May 27, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Enpeng Gao
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line delay interlock circuit for write operation
- Patent number 12,315,552
- Issue date May 27, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Atul Katoch
- G11 - INFORMATION STORAGE
Information Patent Grant
Amplification circuit, control method, and memory
- Patent number 12,315,555
- Issue date May 27, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Weibing Shang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory and method of operation with dummy and loaded route
- Patent number 12,315,557
- Issue date May 27, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Kangling Ji
- G11 - INFORMATION STORAGE
Information Patent Grant
Look-up table write
- Patent number 12,314,720
- Issue date May 27, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, devices, and methods of cache memory
- Patent number 12,315,545
- Issue date May 27, 2025
- ARM Limited
- Divya Madapusi Srinivas Prasad
- G11 - INFORMATION STORAGE
Information Patent Grant
Selectable row hammer mitigation
- Patent number 12,315,553
- Issue date May 27, 2025
- Micron Technology, Inc.
- Edmund J. Gieske
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor element memory device
- Patent number 12,317,475
- Issue date May 27, 2025
- Unisantis Electronics Singapore Pte. Ltd.
- Koji Sakui
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY, BIT LINE CONTROL METHOD, AND ELECTRONIC DEVICE
- Publication number 20250210098
- Publication date Jun 26, 2025
- CXMT CORPORATION
- Shufang SI
- G11 - INFORMATION STORAGE
Information Patent Application
BACKGROUND DATA REFRESH USING SOFT READS
- Publication number 20250210127
- Publication date Jun 26, 2025
- SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Zion KWOK
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT DEVICE
- Publication number 20250210092
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Minho Choi
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING T...
- Publication number 20250210096
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Kyoungmin Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MICROELECTRONIC DEVICES AND MEMORY DEVICES
- Publication number 20250210101
- Publication date Jun 26, 2025
- Micron Technology, Inc.
- Fatma Arzum Simsek-Ege
- G11 - INFORMATION STORAGE
Information Patent Application
DELAY CONTROL CIRCUIT AND A MEMORY MODULE INCLUDING THE SAME
- Publication number 20250211216
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Bumsoo LEE
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE WITH SHARED BIT LINE SENSE AMPLIFIERS
- Publication number 20250210095
- Publication date Jun 26, 2025
- SAMSUNG ELECTRONICS CO,. LTD.
- Keonhee PARK
- G11 - INFORMATION STORAGE
Information Patent Application
3D DRAM WITH CMOS-BETWEEN-ARRAY ARCHITECTURE
- Publication number 20250210093
- Publication date Jun 26, 2025
- IMEC vzw
- Hyungrock Oh
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE HAVING CONTROLLABLE BACK GATES AND SHIELDING BIT LINES
- Publication number 20250212394
- Publication date Jun 26, 2025
- Samsung Electronics Co., Ltd.
- Changyoung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE THREADING WITH STAGGERED DATA TRANSFERS
- Publication number 20250209018
- Publication date Jun 26, 2025
- Rambus Inc.
- Hongzhong Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT CIRCUIT AND STORAGE DEVICE
- Publication number 20250210088
- Publication date Jun 26, 2025
- SK HYNIX INC.
- Min Soon HWANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD FOR OPERATING THE SAME
- Publication number 20250210097
- Publication date Jun 26, 2025
- NANYA TECHNOLOGY CORPORATION
- Chien Yu CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC TRANSMITTER CALIBRATION
- Publication number 20250210099
- Publication date Jun 26, 2025
- QUALCOMM Incorporated
- Jaseem AHAMMED
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY STRUCTURE, MANUFACTURING METHOD THEREOF, AND OPERATING METHO...
- Publication number 20250210100
- Publication date Jun 26, 2025
- Macronix International Co., Ltd.
- Feng-Min LEE
- G11 - INFORMATION STORAGE
Information Patent Application
RANDOMIZED REFRESH OPERATIONS
- Publication number 20250201294
- Publication date Jun 19, 2025
- Micron Technology, Inc.
- Michele Scaravilli
- G11 - INFORMATION STORAGE
Information Patent Application
SEPARATED READ BL SCHEME IN 3T DRAM FOR READ SPEED IMPROVEMENT
- Publication number 20250201296
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONDUCTIVE COUPLING OF BIT LINES USING...
- Publication number 20250201299
- Publication date Jun 19, 2025
- Micron Technology, Inc.
- Jiyun Li
- G11 - INFORMATION STORAGE
Information Patent Application
BOOSTED WRITEBACK VOLTAGE
- Publication number 20250201293
- Publication date Jun 19, 2025
- Rambus Inc.
- Thomas Vogelsang
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS
- Publication number 20250201769
- Publication date Jun 19, 2025
- SK HYNIX INC.
- Seong Ju LEE
- G11 - INFORMATION STORAGE
Information Patent Application
CRYOGENIC QUASI-STATIC EMBEDDED DRAM (CQS-eDRAM) FOR ENERGY-EFFICIE...
- Publication number 20250201292
- Publication date Jun 19, 2025
- Shanghaitech University
- Yuhao SHU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROWHAMMER MITIGATION FOR A MEMORY DIE
- Publication number 20250201295
- Publication date Jun 19, 2025
- Rambus Inc.
- Wendy Elsasser
- G11 - INFORMATION STORAGE
Information Patent Application
Sub-Word Line Driver Placement For Memory Device
- Publication number 20250201297
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
- Publication number 20250201298
- Publication date Jun 19, 2025
- Samsung Electronics Co., Ltd.
- Sunyoung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE HAVING DQS COUNTER CIRCUIT
- Publication number 20250191638
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- SHINGO MITSUBORI
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR ACCESS OPERATIONS DURING VOLTAGE TRANSI...
- Publication number 20250191640
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- HIROKI TAKAHASHI
- G11 - INFORMATION STORAGE
Information Patent Application
Overlapping a Page Operation with a Processing-in-Memory Computation
- Publication number 20250191642
- Publication date Jun 12, 2025
- Google LLC
- Hongil Yoon
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF
- Publication number 20250191645
- Publication date Jun 12, 2025
- WINBOND ELECTRONICS CORP.
- Takuya KADOWAKI
- G11 - INFORMATION STORAGE
Information Patent Application
3D DRAM WITH BIT LINE SELECT AND PRE-CHARGE TRANSISTORS
- Publication number 20250191646
- Publication date Jun 12, 2025
- IMEC vzw
- Hyungrock Oh
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20250191644
- Publication date Jun 12, 2025
- Samsung Electronics Co., Ltd.
- Sang-Hoon Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SMOOTH RTT TRANSITION
- Publication number 20250191647
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- Ryo Fujimaki
- G11 - INFORMATION STORAGE

Read-write (R-W) circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Circuitry borrowing for memory arrays

Recognition system and SRAM cell thereof

Scaling out architecture for dram-based processing unit (DPU)

Memory device for performing read protection operation of limiting...

Semiconductor memory devices having adjustable I/O signal line load...

Write timing compensation

Memory device having merged banks on substrate, and method for oper...

Sacrificial strings in a memory device to detect read disturb

Independent multi-page read operation enhancement technology

Maximum memory clock estimation procedures

Bit line sense amplifier of semiconductor memory device and semicon...

Hybrid volatile and non-volatile memory device

Method and system for refresh of memory devices

Power and performance optimization in a memory subsystem

Memory package and a memory module including the memory package

Sense amplifier with read circuit for compute-in-memory

Nonvolatile memory devices, operating methods thereof and memory sy...

Memory chip and memory system including the same

Vehicle memory system based on 3D memory and method operating thereof

Semiconductor device and method for manufacturing the same

Semiconductor element memory device

Semiconductor-element-including memory device

Signal control circuit, signal control method for blocking activati...

Word line delay interlock circuit for write operation

Amplification circuit, control method, and memory

Memory and method of operation with dummy and loaded route

Look-up table write

Systems, devices, and methods of cache memory

Selectable row hammer mitigation

Semiconductor element memory device

Patents Applicationslast 30 patents

MEMORY, BIT LINE CONTROL METHOD, AND ELECTRONIC DEVICE

BACKGROUND DATA REFRESH USING SOFT READS

INTEGRATED CIRCUIT DEVICE

SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING T...

MICROELECTRONIC DEVICES AND MEMORY DEVICES

DELAY CONTROL CIRCUIT AND A MEMORY MODULE INCLUDING THE SAME

SEMICONDUCTOR DEVICE WITH SHARED BIT LINE SENSE AMPLIFIERS

3D DRAM WITH CMOS-BETWEEN-ARRAY ARCHITECTURE

MEMORY DEVICE HAVING CONTROLLABLE BACK GATES AND SHIELDING BIT LINES

MEMORY MODULE THREADING WITH STAGGERED DATA TRANSFERS

POWER MANAGEMENT CIRCUIT AND STORAGE DEVICE

MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

DYNAMIC TRANSMITTER CALIBRATION

MEMORY STRUCTURE, MANUFACTURING METHOD THEREOF, AND OPERATING METHO...

RANDOMIZED REFRESH OPERATIONS

SEPARATED READ BL SCHEME IN 3T DRAM FOR READ SPEED IMPROVEMENT

APPARATUSES AND METHODS FOR CONDUCTIVE COUPLING OF BIT LINES USING...

BOOSTED WRITEBACK VOLTAGE

COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS

CRYOGENIC QUASI-STATIC EMBEDDED DRAM (CQS-eDRAM) FOR ENERGY-EFFICIE...

ROWHAMMER MITIGATION FOR A MEMORY DIE

Sub-Word Line Driver Placement For Memory Device

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

SEMICONDUCTOR DEVICE HAVING DQS COUNTER CIRCUIT

APPARATUSES AND METHODS FOR ACCESS OPERATIONS DURING VOLTAGE TRANSI...

Overlapping a Page Operation with a Processing-in-Memory Computation

SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF

3D DRAM WITH BIT LINE SELECT AND PRE-CHARGE TRANSISTORS

MEMORY DEVICE

SMOOTH RTT TRANSITION