Devices and methods consistent with example embodiments relate to semiconductor devices having a conductive pillar and methods of manufacturing the same.
As semiconductor devices are becoming highly integrated, a technique for integrating and miniaturizing a semiconductor chip and a semiconductor package on which a semiconductor chip is mounted is being highlighted. A fan-out wafer-level packaging technology in which a redistribution layer is formed below a semiconductor chip instead of a printed circuit board in order to make a semiconductor package thinner has been developed. As a semiconductor chip is becoming miniaturized, an interval between solder balls is reduced so that there is a problem in that handling of the solder balls becomes difficult. In order to address this problem, a fan-out wafer-level package has been proposed.
One or more example embodiments provide a semiconductor device having a conductive pillar whose upper surface is located at a lower level than an upper surface of a semiconductor chip.
The example embodiments of the disclosure are directed to providing a method of manufacturing a semiconductor package which includes grinding an encapsulant and forming an opening in an upper portion of the encapsulant such that a conductive pillar is exposed.
According to example embodiments, there is provided a method of manufacturing a semiconductor package which includes forming a first redistribution structure on a first carrier, forming a plurality of conductive pillars on the first redistribution structure by using a mask pattern, mounting a first semiconductor chip on the first redistribution structure to be adjacent to the plurality of conductive pillars, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant such that an upper surface of the first semiconductor chip is exposed, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure on the first semiconductor chip and the encapsulant, the second redistribution structure being connected to the plurality of conductive pillars. Upper surfaces of the plurality of conductive pillars may be located at a lower level than the upper surface of the first semiconductor chip. The second redistribution structure may include an interconnection pattern and a connection via configured to connect the interconnection pattern to the plurality of conductive pillars, and an upper surface of the connection via has a width greater than a width of a lower surface of the connection via.
According to example embodiments, there is provided a method of manufacturing a semiconductor package which includes forming a first redistribution structure on a first carrier, forming a plurality of conductive pillars on the first redistribution structure by using a mask pattern, mounting a first semiconductor chip on the first redistribution structure to be adjacent to the plurality of conductive pillars, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant such that an upper surface of the first semiconductor chip is exposed, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, forming a corrosion preventive layer on the plurality of exposed conductive pillars, and forming a second redistribution structure on the encapsulant, the second redistribution structure being connected to the plurality of conductive pillars. Upper surfaces of the plurality of conductive pillars may be located at a lower level than the upper surface of the first semiconductor chip. The second redistribution structure may include an interconnection pattern and a connection via configured to connect the interconnection pattern to the plurality of conductive pillars, and an upper surface of the connection via has a width greater than a width of a lower surface of the connection via.
According to example embodiments, there is provided a semiconductor package which includes a first redistribution structure, a first semiconductor chip disposed on the first redistribution structure chip, a plurality of conductive pillars disposed on the first redistribution structure to be adjacent to the first semiconductor chip, an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and side surfaces of the first semiconductor chip, and a second redistribution structure disposed on the encapsulant and connected to the plurality of conductive pillars. Upper surfaces of the plurality of conductive pillars may be located at a lower level than the upper surface of the first semiconductor chip. The second redistribution structure may include an interconnection pattern and a connection via configured to connect the interconnection pattern to the plurality of conductive pillars, and an upper surface of the connection via has a width greater than a width of a lower surface of the connection via.
These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawing, in which:
Hereinafter, a method of manufacturing the semiconductor package 100 according to the example embodiment configured as described above will be described with reference to the accompanying drawings. Aspects of example embodiments will be more clearly understood from the following embodiments described in detail with reference to the accompanying drawings. Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The relative size and depiction of these elements may be exaggerated for clarity, illustration, and convenience.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Any references to singular may include plural unless expressly stated otherwise. In addition, unless explicitly described to the contrary, an expression such as “comprising” or “including” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. Also, the terms, such as ‘part’, ‘unit’ or ‘module’, etc., should be understood as a unit that performs at least one function or operation and that may be embodied as hardware, software, or a combination thereof.
The method of manufacturing the semiconductor package according to the example embodiment may include providing a first carrier, forming a first redistribution structure on the first carrier, forming conductive pillars on the first redistribution structure by using a mask pattern, mounting a first semiconductor chip on the first redistribution structure to be adjacent to the plurality of conductive pillars, forming an encapsulant surrounding an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant such that an upper surface of the first semiconductor chip is exposed, exposing the plurality of conductive pillars by forming an opening in an upper portion of the planarized encapsulant, and forming a second redistribution structure connected to the conductive pillars on the first semiconductor chip and the encapsulant. Further, the method of manufacturing the semiconductor package according to the example embodiment may further include mounting a second semiconductor chip on the second redistribution structure and forming an encapsulant covering an upper surface of the second redistribution structure and the second semiconductor chip. This is merely an example embodiment and the disclosure is not limited to.
Hereinafter, a method of manufacturing the semiconductor package 100 according to the example embodiment configured as described above will be described with reference to
Referring to
Referring to
The interlayer insulating layer 112 and the interconnection pattern 114 may be stacked in at least one layer. The via 116 may electrically connect interconnection patterns 114 of different layers to each other and may have various shapes such as, for example but not limited to, a cylindrical shape and/or a tapered shape. Further, the via 116 may be disposed to be integrated with the interconnection pattern 114. The interlayer insulating layer 112 may electrically insulate the interconnection pattern 114 and the via 116 from the outside.
The interlayer insulating layer 112 may include a photosensitive material that can be patterned by using a photolithography process. For example, the interlayer insulating layer 112 may include a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In an example embodiment, the interlayer insulating layer 112 may include silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or a combination thereof. The interlayer insulating layer 112 may be formed by processes such as a chemical vapor deposition (CVD) process, a lamination process, a spin coating process, and the like.
The process of forming the first redistribution structure 110 may include forming the interconnection pattern 114 on the release film 104. The forming of the interconnection pattern 114 may include forming a barrier layer and a seed layer (not shown) on the interlayer insulating layer 112, forming a patterned mask (not shown) such as a photoresist or the like on the seed layer, and forming a conductive material on the exposed seed layer. The forming of the conductive material may include a plating process. Thereafter, the patterned mask and portions of the barrier layer and the seed layer which are covered by the patterned mask are removed, and the interconnection pattern 114 is formed. The first redistribution structure 110 may be formed as shown in
The barrier layer may include at least one selected from Ta, Ti, W, Ru, V, Co, and Nb. The seed layer may include at least one selected from Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au, and Ag. In an example embodiment, the barrier layer may include Ti and the seed layer may include Cu. The barrier layer and the seed layer may be formed by a physical vapor deposition (PVD) process, a CVD process, or an atomic layer deposition (ALD) process.
The interconnection pattern 114 and the via 116 may include a metal such as Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au, or Ag. In an example embodiment, the interconnection pattern 114 and the via 116 may include copper. The interconnection pattern 114 and the via 116 may be formed by an electrochemical plating process, an electroless plating process, a PVD process, a CVD process, a spin-on process, or a combination thereof. In an example embodiment, the interconnection pattern 114 and the via 116 may be formed by a damascene process.
Referring to
Referring to
The forming of the conductive pillar 122 may include forming a barrier layer and a seed layer (not shown), forming the mask pattern 120 on the seed layer, and filling the portion exposed by the mask pattern 120 with a conductive material. Thereafter, the mask pattern 120 and portions of the barrier layer and the seed layer which are covered by the mask pattern 120 may be removed.
Although not shown, the barrier layer and the seed layer may be formed on the upper surface of the first redistribution structure 110. In an example embodiment, the barrier layer may include Ti and the seed layer may include Cu. The barrier layer and the seed layer may be formed by a PVD process, a CVD process, an ALD process, or the like.
The mask pattern 120 may be formed on the seed layer. The mask pattern 120 may be formed by a spin coating process or the like and may be exposed to light for patterning. The mask pattern 120 may define a region in which the conductive pillar 122 will be disposed. The conductive material may be formed in an opening of the mask pattern 120 and on the exposed portion of the seed layer. The conductive material may be formed, for example, by plating such as electroplating, electroless plating, or the like. The conductive material may include a metal such as Cu, Ti, W, Al, or the like. In an example embodiment, the conductive material may include Cu. The mask pattern 120 and a portion of the seed layer on which the conductive material is not formed may be removed. The mask pattern 120 may be removed by a release process in which an oxygen plasma or the like is used. After the mask pattern 120 is removed, the barrier layer and the exposed portion of the seed layer may be removed by wet or dry etching. The barrier layer, a remaining portion of the seed layer, and the conductive material may form the conductive pillar 122.
As shown in
Referring to
The first semiconductor chip 130 may include bonding pads 132 disposed therebelow and bumps 134 disposed below the bonding pads 132. The bonding pad 132 may be electrically connected to the interconnection pattern 114 of the first redistribution structure 110 through the bump 134. In an example embodiment, the bonding pad 132 may include Cu and the bump 134 may include Sn.
An upper surface of the first semiconductor chip 130 may be located at a higher level than an upper surface of the conductive pillar 122. In
Referring to
The encapsulant 140 may be a resin including an epoxy or polyimide. For example, the encapsulant 140 may include a bisphenol-based epoxy resin, a polycyclic aromatic epoxy resin, an o-cresol novolac epoxy resin, a biphenyl-based epoxy resin, a naphthalene-based epoxy resin, or the like.
Referring to
Generally, in a grinding process, when the conductive pillar 122 is simultaneously planarized with the semiconductor chip, the upper surface of the conductive pillar 122 may be partially removed and a residue and/or a burr may be formed. The residue and/or the burr may cause a reduction in the reliability of the redistribution layer formed on the semiconductor chip. In the method of manufacturing the semiconductor package of the disclosure, since the conductive pillar 122 is not exposed to the outside in the planarization process of the encapsulant 140, a contamination problem due to the residue and/or the burr may be prevented or suppressed.
Since the upper surface of the conductive pillar 122 is located at a lower level than the upper surface of the first semiconductor chip 130, the encapsulant 140 and upper silicon of the first semiconductor chip 130 may be removed during the grinding process. In the method of manufacturing the semiconductor package according to an example embodiment of the disclosure, since the conductive pillar 122 is not removed during the grinding process, the upper surface of the encapsulant 140 may be uniformly cut during the grinding process. For example, a surface roughness Ra of the upper surface of the encapsulant 142 may be 0.1 μm or less.
Referring to
Referring to
The interlayer insulating layer 152 may be formed on the first semiconductor chip 130 and the encapsulant 142. The interlayer insulating layer 152 may be patterned and may define positions at which the interconnection patterns 154 and 155, the via 156, and the connection via 157 are formed. Although not shown, a barrier layer and a seed layer may be formed on the interlayer insulating layer 152 and the conductive pillar 122. The interconnection patterns 154 and 155 and the connection via 157 may be formed by filling the seed layer with a conductive material. The interconnection patterns 154 and 155, the via 156, and the connection via 157 may be formed by processes such as CVD, ALD, plating, and the like.
The connection via 157 may fully fill the opening 145 and may connect the conductive pillar 122 to the interconnection pattern 155. The interconnection pattern 155 and the connection via 157 may be integrally formed. For example, the interconnection pattern 155 and the connection via 157 may be formed by a damascene process. The connection via 157 may have a shape of a truncated cone. For example, a first diameter D1 may be greater than a second diameter D2. Here, the first diameter D1 may refer to a diameter of an upper surface of the connection via 157 shown in
In the method of manufacturing the semiconductor package according to the example embodiment of the disclosure, since the upper surface of the conductive pillar 122 is formed at a lower level than the upper surface of the first semiconductor chip 130, a first thickness T1 may be greater than a second thickness T2. Here, the first thickness T1 may refer to a distance from a lower surface of the conductive pillar 122 to the upper surface of the encapsulant 142, and the second thickness T2 may refer to a distance from the lower surface of the conductive pillar 122 to the lower end of the connection via 157. A ratio of the second thickness T2 to the first thickness T1 may be 0.8 or less.
In the method of manufacturing the semiconductor package according to the example embodiment of the disclosure, since the conductive pillar 122, which connects the first redistribution structure 110 to the second redistribution structure 150, is formed on the first redistribution structure 110 by using the mask pattern 120, the conductive pillar 122 may have a columnar shape. Further, the diameter of the conductive pillar 122 may be substantially constant, and the conductive pillar 122 may not have a protrusion which protrudes in a radial direction.
Referring to
The second carrier 160 may be formed before the first carrier 102 is separated. A release film 162 may further be disposed between the second carrier 160 and the second redistribution structure 150. The second carrier 160 may be located on a surface opposite to a surface on which the second redistribution structure 150 is in contact with the first semiconductor chip 130. The second carrier 160 and the release film 162 may include the same material as the first carrier 102 and the release film 104, respectively.
Referring to
The external connecting member 170 may include tin (Sn), silver (Ag), copper (Cu), palladium (Pd), bismuth (Bi), or antimony (Sb). The interlayer insulating layer 172 may include the same material as the interlayer insulating layer 112 and may include, for example, a polymer such as PBO, polyimide, BCB, or the like. The via 174 may include a metal such as Al, Ti, Cr, Fe, Co, Ni, Cu, Zn, Pd, Pt, Au, or Ag. In an example embodiment, the via 174 may include Cu. The under bump metal 176 may include chromium/chromium-copper alloy/copper (Cr/Cr—Cu/Cu), titanium-tungsten/alloy copper (Ti—W/Cu), aluminum/nickel/copper (Al/Ni/Cu), or nickel. The under bump metal 176 may be formed by a sputtering process, an electrolytic plating process, an electroless plating process, or the like.
Referring to
Referring to
The second semiconductor chip 180 may function differently from the first semiconductor chip 130. For example, the first semiconductor chip 130 may be a logic chip such as an application process, and the second semiconductor chip 180 may be a memory chip such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a not AND (NAND) flash memory, or the like.
Referring to
The semiconductor package 100 according to the example embodiment of the disclosure may be completed by covering the second semiconductor chip 180 with the encapsulant 185. The semiconductor package 100 may include a lower package 10 and an upper package 20. The lower package 10 may include the first redistribution structure 110, the conductive pillar 122, the first semiconductor chip 130, the encapsulant 142, and the second redistribution structure 150. The upper package 20 may include the second semiconductor chip 180 and the encapsulant 185.
Referring to
The interconnection patterns 254 and 255, the via 256, and the connection via 257 of the second redistribution structure 250 may include a conductive material different from that of the conductive pillar 122. In an example embodiment, the conductive pillar 122 may include copper, and the interconnection patterns 254 and 255, the via 256, and the connection via 257 may include aluminum. However, the disclosure is not limited thereto.
Generally, an aluminum interconnection may form a film that is denser than a copper interconnection and has no problem of being diffused into silicon or an insulating film. However, the aluminum interconnection may have a disadvantage in that corrosion may be easily caused due to poor electron mobility. Specifically, galvanic corrosion may be easily caused at a portion of the aluminum interconnection in which aluminum is in contact with a dissimilar metal. As shown in
Referring to
Referring to
According to the example embodiments of the disclosure, since an upper surface of a conductive pillar is located at a lower level than an upper surface of a first semiconductor chip, the conductive pillar may not be exposed during grinding of an encapsulant, and thus a contamination problem and a problem of reduction in reliability can be prevented.
While the example embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the disclosure. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.
Number | Date | Country | Kind |
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10-2018-0157071 | Dec 2018 | KR | national |
This is a continuation application based on U.S. application Ser. No. 16/415,058 filed May 17, 2019, which claims priority from Korean Patent Application No. 10-2018-0157071, filed on Dec. 7, 2018, in the Korean Intellectual Property Office, the disclosures of which are herein incorporated by reference in their entireties.
Number | Name | Date | Kind |
---|---|---|---|
8980691 | Lin | Mar 2015 | B2 |
9368438 | Lin et al. | Jun 2016 | B2 |
9397080 | Hsu et al. | Jul 2016 | B2 |
9825005 | Yeh et al. | Nov 2017 | B2 |
9831142 | Baek et al. | Nov 2017 | B2 |
10049964 | Shim et al. | Aug 2018 | B2 |
20110068427 | Paek et al. | Mar 2011 | A1 |
20110278736 | Lin et al. | Nov 2011 | A1 |
20130037929 | Essig et al. | Feb 2013 | A1 |
20140048906 | Shim et al. | Feb 2014 | A1 |
20140103527 | Marimuthu et al. | Apr 2014 | A1 |
20140183731 | Lin et al. | Jul 2014 | A1 |
20140264808 | Wolter | Sep 2014 | A1 |
20150001708 | Lin | Jan 2015 | A1 |
20150187746 | Hsu et al. | Jul 2015 | A1 |
20160197057 | Umemoto et al. | Jul 2016 | A1 |
20170053898 | Yeh et al. | Feb 2017 | A1 |
20170133288 | Baek et al. | May 2017 | A1 |
20170179033 | West et al. | Jun 2017 | A1 |
20170323868 | Park et al. | Nov 2017 | A1 |
20180061805 | Fang et al. | Mar 2018 | A1 |
20190319000 | Lin | Oct 2019 | A1 |
20200273804 | Jeon et al. | Aug 2020 | A1 |
Number | Date | Country | |
---|---|---|---|
20210280562 A1 | Sep 2021 | US |
Number | Date | Country | |
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Parent | 16415058 | May 2019 | US |
Child | 17316044 | US |