Patent Application
20250183152
Disclosed implementations relate generally to the field of integrated circuits (ICs) and IC fabrication. More particularly, but not exclusively, the disclosed implementations relate to an IC including a high voltage isolation device.
Galvanic isolation is a principle of isolating functional sections of electrical systems or integrated circuits to prevent current flow while energy or information can still be exchanged between the sections by other means, such as capacitance, induction or electromagnetic waves, or by optical, acoustic or mechanical means. Galvanic isolation is typically used where two or more electric circuits communicate but their grounds or reference nodes may be at different potentials. It is an effective method of breaking ground loops by preventing unwanted current from flowing between two units sharing a reference conductor. Galvanic isolation is also used for safety, preventing accidental current flows from reaching ground though a person's body.
Isolators are devices designed to minimize direct current (DC) and unwanted transient currents between two systems or circuits, while allowing data and power transmission between the two. In most applications, isolators also act as a barrier against high voltage in addition to allowing the system to function properly. Where capacitive elements are used as isolators, dielectric breakdown is a key concern, especially in high voltage (HV) applications.
As the advances in the design of integrated circuits and semiconductor fabrication continue to take place, improvements in microelectronic devices, including galvanic isolators, are also being concomitantly pursued.
The following presents a simplified summary in order to provide a basic understanding of some examples of the present disclosure. This summary is not an extensive overview of the examples, and is neither intended to identify key or critical elements of the examples, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the present disclosure in a simplified form as a prelude to a more detailed description that is presented in subsequent sections further below.
Examples of the present disclosure are directed to an IC (also referred to as an electronic device, IC device, semiconductor device, etc.) including a capacitive HV isolation component where defectivity levels may be minimized while continuing to maintain the breakdown performance of the device. In various examples, a silicon nitride (SiN) bilayer is provided directly underneath a top electrode of the HV isolation component in order to ensure sufficient HV isolation, where the SiN bilayer includes a top SiN layer having suitable refractive index (RI) characteristics different from the RI characteristics of the underlying SiN layers, the differential RI characteristics of the top SiN layer facilitating a reduction in processing defects that may be caused by certain back-end-of-line (BEOL) stages of a fabrication flow.
In one example, an IC device is disclosed, which comprises, among others, a semiconductor substrate, a metal bottom plate over the semiconductor substrate, a metal top plate over the metal bottom plate, and a dielectric structure disposed between the top and bottom plates, the dielectric structure including a silicon nitride (SiN) bilayer underlying the top plate, where the SiN bilayer includes a first SiN layer directly contacting the top plate and having a first refractive index (RI), and a second SiN layer underneath the first SiN and having a second RI greater than the first RI. In some examples, the first SiN layer may have an RI of about 2.0 to 2.15 whereas the second SiN layer may have an RI of about 2.2 to 2.4. In some examples, the first SiN layer may have a thickness less than about 20% of a total thickness of the SiN bilayer.
In one example, a method of fabricating an IC device including an isolation component is disclosed. The method may comprise, among others, forming a bottom electrode of the isolation component over a semiconductor substrate, and forming a dielectric structure between the bottom electrode and a top electrode of the isolation component, where the dielectric structure includes a SiN bilayer underlying the top electrode, the SiN bilayer including a first SiN layer directly contacting the top electrode and having a first RI, and a second SiN layer underneath the first SiN and having a second RI greater than the first RI. In some examples, the method may further comprise forming an isolation break region in a portion of the SiN bilayer extending beyond the top electrode. In some examples, the SiN bilayer is formed over an oxynitride layer (e.g., a SiON layer) overlying a main dielectric component of the dielectric structure, the main dielectric component overlying the bottom electrode and having a thickness of at least 4 microns (μm). In some examples, the top electrode may be formed from a topmost metal layer of a multilevel metal interconnect formed over the semiconductor substrate. In some examples, the bottom electrode may be formed from an intermediate metal layer of the multilevel metal interconnect formed over the semiconductor substrate.
Implementations of the present disclosure are illustrated by way of example, and not by way of limitation, in the Figures of the accompanying drawings. Different references to “an” or “one” implementation in this disclosure are not necessarily to the same implementation, and such references may mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an implementation, such feature, structure, or characteristic in connection with other implementations may be feasible whether or not explicitly described.
The accompanying drawings are incorporated into and form a part of the specification to illustrate one or more example implementations of the present disclosure. Various advantages and features of the disclosure will be understood from the following Detailed Description taken in connection with the appended claims and with reference to the attached drawing Figures in which:
Examples of the disclosure are described with reference to the attached Figures where like reference numerals are generally utilized to refer to like elements. The Figures are not drawn to scale and they are provided merely to illustrate examples. Numerous specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, some examples may be practiced without such specific details. In other instances, well-known subsystems, components, structures and techniques have not been shown in detail in order not to obscure the understanding of the examples. Accordingly, the examples of the present disclosure may be practiced without such specific components.
Additionally, terms such as “coupled” and “connected,” along with their derivatives, may be used in the following description, claims, or both. It should be understood that these terms are not necessarily intended as synonyms for each other. “Coupled” may be used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other. “Connected” may be used to indicate the establishment of communication, i.e., a communicative relationship, between two or more elements that are coupled with each other. Further, in one or more examples set forth herein, generally speaking, an element, component or module may be configured to perform a function if the element may be programmed for performing or otherwise structurally arranged to perform that function.
Without limitation, examples of a high voltage isolation device and a method of manufacturing the same will be set forth below in the context of capacitive isolation devices formed in the interconnect levels of an IC during back-end-of-line (BEOL) fabrication.
Circuit isolation, also known as galvanic isolation, may prevent direct current (DC) and unwanted alternating current (AC) signals from passing from one area of a system or a circuit to another area or circuit that needs to be protected, as previously noted. Among its uses, isolation may maintain signal integrity of the system or circuit by preventing high-frequency noise from propagating, protecting sensitive circuitry from high-voltage surges and spikes, and providing safety for human operators.
The high voltages present in factory automation, motor drives, grid infrastructure and electric vehicles (EVs), etc., can be several hundred or even thousands of volts. Galvanic isolation helps resolve the challenge of designing a safe human interface in the presence of such high voltages.
In some example implementations, galvanic isolators may be created by forming a parallel-plate capacitor using electrodes in different metallization layers of the integrated circuit, such as different metallization layers in the BEOL interconnect levels. The dielectric layers of the BEOL levels separate the electrodes to form the capacitor. For HV applications, the thickness of BEOL dielectric layers and/or the number of BEOL dielectric layers may be increased to provide a higher breakdown voltage. In some examples, a composite dielectric layer comprising silicon nitride (SiN) and silicon oxynitride (SiON) may be provided under the top electrode for improving HV isolation performance.
Chemical-mechanical polishing/planarization (CMP), including electrochemical-mechanical polishing (eCMP), may be used to smooth, or planarize a material layer prior to forming vias through the material layer. In some examples the planarized layer includes composite SiON/SiN layers formed in the fabrication of HV isolation devices. The CMP process uses an abrasive and corrosive slurry together with a polishing pad and retaining ring, typically of a greater diameter than the wafer. The pad and wafer are pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head is rotated with different axes of rotation which removes material from the surface of the wafer and tends to even out any irregular topography, making the wafer surface planar.
CMP, a tribochemical and electrochemical process based on the synergy between various mechanical and electrochemical mechanisms, uses a variety of slurry materials and electrolytes for polishing and planarization. The slurry often contains particles composed of alumina, silica, and/or cerium oxide (ceria), etc., suspended in an acidic or basic solution. During the manufacturing process the suspended particles can settle and form what are known as large particle counts, which can be difficult to remove in a post-CMP cleaning process due to the complex interaction of the different materials involved that are often extant in multiple phases, e.g., gas, liquid, and/or solid phases. Because of the difficulty in the removal of particulate matter generated and/or introduced in CMP, any entrapped particulate matter may increase the risk of defectivity in the device, which can compromise the device's HV breakdown performance.
Examples of the present disclosure recognize the foregoing challenges and accordingly provide a technical solution for fabricating IC devices, including those implementing a capacitive HV isolation component, where CMP-associated defectivity may be advantageously reduced prior to or during via formation without significantly reducing the HV breakdown/isolation performance of the device. Depending on application, examples herein include forming a SiN bilayer directly underneath a top electrode of a capacitive HV component, where an upper portion of the SiN bilayer comprises nitride material having predetermined refractive index (RI) characteristics configured to enhance protection against defect formation as will be set forth in detail further below. While such examples and variations may be expected to reduce manufacturing defects that could otherwise reduce yields, reliability or electrical performance, no particular result is a requirement of the present disclosure unless explicitly recited in a particular claim.
Turning to
The capacitor 102 includes a first electrode 104 and a second electrode 105. Without limitation, implied or otherwise, the first electrode 104 may be referred to as bottom plate/electrode or lower plate/electrode 104, and the second electrode 105 may be referred to as top plate/electrode or upper plate/electrode 105. In various examples the top plate 105 and the bottom plate 104 are about the same size and shape, although it is not a necessary requirement for purposes of the present disclosure. Further, in an example implementation, the bottom plate 104 may be disposed directly between the top plate 105 and the substrate 101 along a surface normal, e.g., with or without varying amounts of overlap between the two plates. The top plate 105 may be connected to a high-voltage circuit node, while the bottom plate 104 and the transistor 103 may be connected to a low-voltage circuit node in some arrangements.
In some examples, the bottom plate 104 and/or the top plate 105 may have a minimum length along a longest axis of about 30 μm. Likewise, the bottom plate 104 and/or the top plate 105 may each have a minimum length along an orthogonal shortest axis of about 30 μm. In some examples, each of the bottom plate 104 and the top plate 105 may have an aspect ratio (e.g., length of longest axis divided by length of orthogonal shortest axis) of in a range between about one and about five. The plates 104 and 105 are not limited to any particular shape, which may comprise a variety of geometrical shapes, e.g., squares, circles, ovals, ellipses, rectangles, ovoids, coils/serpentines, racetracks, obrounds, trapezoids, rhomboids, regular or irregular polygons, etc. In some further examples, the plates 104 and 105 may have a minimum lateral width (parallel to the substrate 101 surface) sufficient to facilitate the formation of a wire bond, e.g., bond 197, with respect to the top plate 105, in order to provide connectivity with external circuitry (not shown in this Figure). Such minimum width may depend on the wire bonding technology, and without any limitation, may be about 80 μm. In one non-limiting example, the plates 104 and 105 each have a short axis length of about 120 μm and a long axis length of about 160 μm. In another non-limiting example, the plates 104 and 105 are both of a circular shape, with a diameter of about 100 μm. In some examples, one of the bottom plate 104 and the top plate 105 may be implemented as a plurality of plates, e.g., two plates. Thus, in one non-limiting example, the bottom plate 104 may be a single continuous metal plate, while the top plate 105 may be two noncontiguous metal plates. In such examples, the two or more plates need not be a same shape, or have a same area.
The example of
An optional isolation structure 106, e.g., a shallow trench isolation (STI) structure, may be disposed between the PMD layer 114, e.g., comprising (sub) layers 112, 115, and the substrate 101. In some examples, the isolation structure 106 may be configured to reduce capacitive coupling between the bottom plate 104 and the substrate 101. In other examples, not shown, the isolation structure 106, if present, may include one or more doped well regions that may provide junction isolation between the bottom plate 104 and the substrate 101. As depicted in
The plates 104 and 105 may be comprised of any suitable metal. Examples described herein may describe the plates 104 and 105 as being formed from aluminum (Al), although other metal interconnect systems, such as copper (Cu) or gold (Au), may be used in additional and/or alternative arrangements without undue experimentation. The top plate 105 may be configured to receive a high voltage signal, e.g., via a wire ball-bonded to the top plate 105. The high voltage signal may be received from a high-voltage source to which the device 100 is connected, e.g., another IC operating in a high voltage domain, an electric motor, etc., to provide data transmission or an electronic function such as monitoring or controlling. Depending on implementation, “high voltage” may refer to a static or RMS voltage of about 100 V or more, and “low voltage” may refer to a static or RMS voltage of about 20 V or less for purposes of some examples herein, without limitation.
The top plate 105 is capacitively coupled to the bottom plate 104 through the one or more intervening dielectric layers, e.g., ILD1-ILD4 and corresponding IMD1-IMD4 in the illustrated arrangement of
For purposes of some examples of the present disclosure, three types of silicon dioxide dielectric materials are described. Two types may be produced by a plasma-enhanced chemical vapor deposition (PECVD) process in a capacitively-coupled plasma reactor using tetraethoxysilane (TEOS) feedstock. These dielectrics are referred to herein as “PE-TEOS”, where a first type of PE-TEOS is a “high-stress” PE-TEOS and a second type of PE-TEOS is “low-stress” PE-TEOS, without limitation. In a non-limiting example, a “high-stress” PE-TEOS process may be configured to produce an SiO2 layer with about 120 MPa (megapascal) compressive stress, whereas a “low-stress” PE-TEOS process may be configured to produce an SiO2 layer with about 20 MPa compressive stress. A third type of silicon dioxide may be produced using by a high-density plasma in an inductively-coupled reactor, and is referred to as “HDP oxide”, without limitation. In some arrangements, HDP oxide and/or high-stress PE-TEOS may be used as the dielectric in close proximity to or in contact with the plates 104 and 105, while one or more of the dielectric levels between the plates 104 and 105 include low-stress PE-TEOS to reduce the impact/extent of wafer bow. Additional details with respect to forming PE-TEOS and HDP oxide layers that may be implemented in some examples of the present disclosure may be found in U.S. Pat. No. 11,495,658, which is incorporated by reference herein for all purposes.
Continuing to refer to the example of
In the illustrated example, the bottom plate 104 is formed in the MET2 level that is formed over the high-stress PE-TEOS sublayer 130, where an HDP oxide layer 139 is formed as part of the IMD2 layer over the bottom plate 104. Accordingly, the bottom plate 104 is bounded by HDP oxide on top and side surfaces, and by high-stress PE-TEOS on the bottom surface. The bottom plate 104 and the top plate 105 are spaced apart by a dielectric stack structure comprising portions of or formed from the various ILD and IMD layers, which may comprise PE-TEOS and/or HDP oxide materials, where a silicon nitride (SiN) bilayer forming part of the dielectric stack structure may be formed directly underlying the top plate 105 for purposes of the present disclosure as will be set forth further below.
In the illustrated example, portions of the ILD2, IMD3, ILD3, IMD4 and ILD4 layers may be operable as part of a vertical stack structure of dielectrics (not specifically labeled with a reference number in
The top plate 105 may be located at least partially within the IMD5 layer, which includes an HDP oxide layer 190, where the HDP oxide layer 190 covers or touches sidewalls and a portion of the top surface of the top plate 105 such that only an opening 199 formed for wire bonding is exposed. In similar fashion, a TEOS layer 193 having an opening corresponding to the wire bond opening of the HDP oxide layer 190 may be formed thereover. A suitable PO layer 196 may be formed to cover remaining portions of the TEOS layer 193 of the IMD5 level. Additionally, the PE-TEOS layer 171 of IMD4 is covered by a SiN bilayer 177 and an SiON layer 174 for enhancing HV breakdown performance of the electronic device 100 in some examples.
In various examples of the present disclosure, the SiN bilayer layer 177 may be formed as a composite bilayer having a first SiN layer 177A (also referred to as top or upper SiN layer) with a low refractive index (RI) range that is in contact with and directly underlying the top plate 105. The upper SiN layer 177A having a low RI relative to an underlying second SiN layer 177B (also referred to as a bottom or lower SiN layer) may be provided for reducing potential defectivity that may be caused due to upper level via processing by CMP, as will be described below in reference to the cross-sectional views of
In some arrangements, the PE-TEOS layers 141, 156, 171 may be provided as low-stress layers that may be encapsulated by other dielectric layers that effectively prevent moisture diffusion into the dielectric stack and/or prevent significant out-diffusion of moisture incorporated in the PE-TEOS layers during manufacturing. In other examples, not shown, configured to operate in relatively low-voltage applications in which the risk of dielectric breakdown near corners of the top plate 105 is reduced, low-stress PE-TEOS layers may be replaced by high-stress PE-TEOS layer of similar thicknesses, respectively.
In the example of
In
In the illustrated example, another via and metal level is formed, as shown in
In
The SiN bilayer 177 may have a desired overall target thickness, e.g., around 500 nm to 800 nm, depending on the HV application, where the thickness of the upper SiN layer 177A may be less than the thickness of the lower SiN layer 177B by a fraction less than unity, e.g., about one-fifth (20%) or less. Because the upper SiN layer 177A (with lower RI) is expected to be lost or sacrificed due to subsequent via CMP erosion, a thicker upper SiN layer 177A may be initially deposited over the lower SiN layer 177B having a target thickness and required high RI characteristics. Vias 183 may be formed through the composite SiON/SiN layer 174/177, where there may be metal overburden 202 while filling the vias with suitable metal (e.g., W), as shown in
In BEOL process flows that include the formation of a high RI SiN film directly underlying a top electrode of an HV isolation device, the via CMP process typically lands on the polished high RI SiN film. Because CMP (including eCMP) is generally an unclean process as noted previously, various types of particulate matter, metal whiskers, metal strings, granulated metallics, CMP slurry materials such as aggregates, agglomerates, and gels, debris such as microscopic flakes, flecks, shards etc. caused by routine wear and tear of the equipment components, and the like, which may be broadly referred to herein as “contaminants” or “surface defects”, may remain on the surface of the high RI SiN layer even after an aggressive post-CMP cleaning process. Where the vias are operable for providing top level connectivity, e.g., providing electrically conductive paths between a topmost MET level and a lower MET level, the contaminants on the SiN surface can remain encapsulated by subsequent conductive and/or dielectric layers, thereby increasing the risk of defectivity, which can negatively affect the HV breakdown performance of a device. The inventors of the present disclosure have discovered that the CMP-associated surface defect levels and the range of RI values of SiN films on which the CMP process lands are directly related, e.g., showing a positive correlation between the two variables. It is postulated herein that increased RI of a SiN film affects the Zeta (C) potential associated with the contaminants. The Zeta potential is a net electrokinetic potential resulting from the van der Waal attractive forces and electrical double-layer repulsive forces that may be established in a system containing particulate matter having charged surfaces, where the charged particulate matter may be in a suspension and/or on a material surface. With sufficient Zeta potential, which may be on the order of several millivolts in some examples, the particulate matter may form bonds with one another as well as with the material surface based on the phenomena such as flocculation and/or coagulation, which may render the particulate matter more resistant to a cleaning process. As high RI values of SiN films are directly related to the defectivity levels (e.g., in terms of surface defects, particulate counts, and/or defective parts per million (dppm), etc.), a BEOL process for forming composite SiON/SiN layers in HV isolation devices may be suitably characterized and/or qualified such that a SiN layer having a sufficiently low RI value may be process-engineered for a particular application requiring a level of defectivity that does not exceed a given threshold level. Because HV isolation performance requires a high RI SiN layer in some implementations, a combination of SiN materials having different RI characteristics may be optimized and provided as a bilayer structure according to the examples herein, where a low RI SiN material may form a thin upper layer for attenuating CMP-based defectivity levels (due to the expected reduction in Zeta potential interactions, which may also facilitate better surface potential control over the layer in the electrolytic solution) while a high RI SiN material may form a lower layer of sufficient thickness that affords acceptable HV isolation performance. For a given erosion amount, e.g., 100 nm to 150 nm of overburden, a CMP/eCMP process may be configured to have a suitable material removal rate endpoint for landing on the low RI SiN layer, thereby ameliorating the incidence of the surface defectivity levels according to some examples herein. An initial thickness of the low RI SiN layer may also be selected depending on how much material may be sacrificed in CMP, thickness of the low RI SiN layer relative to overall target thickness of the SiN bilayer, etc. In additional and/or alterative arrangements, the compressive stresses of the various components of a composite SiON/SiN layer may also be optimized while balancing the defectivity levels and HV isolation performance of an electronic device, e.g., device 100. It should be recognized upon reference hereto that the term “CMP” is inclusive of “eCMP” at least for purposes of some examples herein, depending on the context, unless otherwise noted.
As set forth previously, the composite SiON/SiN layer 174/177 may be operable as ILD4 in an example arrangement. Vias 183, e.g., tungsten, formed within the ILD4 are operable to connect MET4 structures 165 to upper MET5 structures 187 that may be formed at a subsequent stage.
In some examples, high RI and low RI SiN layers underlying the top electrode 105 of the device 100 may be distinguished by ellipsometry where in-situ and/or offline RI measurements may be obtained for purposes of process characterization, qualification and/or statistical process quality control. In some examples, a physical cross-section of the device 100 may be analyzed and reverse engineered for differentiating between the high RI and low RI SiN layers.
The preceding description of the example 5 LM process sequence is not limited to any particular thicknesses of metal and/or dielectric layers. Further, a similar process sequence for depositing a combination SiN layer including two or more SiN sublayers with disparate RI values, respectively, may be provided in conjunction with any multilevel metal interconnect system having an arbitrary number of MET levels (e.g., 6 to 12 MET levels or more), where the top electrode of an isolation device is configured to be in direct contact with a low RI SiN sublayer.
While various examples of the present disclosure have been described above, they have been presented by way of example only and not limitation. Numerous changes to the disclosed examples can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above described examples. Rather, the scope of the disclosure should be defined in accordance with the claims appended hereto and their equivalents.
For example, in this disclosure and the claims that follow, unless stated otherwise and/or specified to the contrary, any one or more of the layers set forth herein can be formed in any number of suitable ways, such as with spin-on techniques, sputtering techniques (e.g., Magnetron and/or ion beam sputtering), (thermal) growth techniques or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), PECVD, or atomic layer deposition (ALD), etc. As another example, silicon nitride may be a silicon-rich silicon nitride or an oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the materials dielectric constant is substantially different from that of high purity silicon nitride.
Further, in at least some additional or alternative implementations, the functions/acts described in the blocks may occur out of the order shown in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. Also, some blocks in the flowcharts may be optionally omitted. Furthermore, although some of the diagrams include arrows on communication paths to show a primary direction of communication, it is to be understood that communication may occur in the opposite direction relative to the depicted arrows. Finally, other blocks may be added/inserted between the blocks that are illustrated.
The order or sequence of the acts, steps, functions, components or blocks illustrated in any of the flowcharts and/or block diagrams depicted in the drawing Figures of the present disclosure may be modified, altered, replaced, customized or otherwise rearranged within a particular flowchart or block diagram, including deletion or omission of a particular act, step, function, component or block. Moreover, the acts, steps, functions, components or blocks illustrated in a particular flowchart may be inter-mixed or otherwise inter-arranged or rearranged with the acts, steps, functions, components or blocks illustrated in another flowchart in order to effectuate additional variations, modifications and configurations with respect to one or more processes for purposes of practicing the teachings of the present disclosure. Likewise, although various examples have been set forth herein, not all features of a particular example are necessarily limited thereto and/or required therefor.
At least some portions of the foregoing description may include certain directional terminology, such as, “upper”, “lower”, “top”, “bottom”, “left-hand”, “right-hand”, “front side”, “backside”, “vertical”, “horizontal”, etc., which may be used with reference to the orientation of some of the Figures or illustrative elements thereof being described. Because components of some examples can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Likewise, references to features referred to as “first”, “second”, etc., are not indicative of any specific order, importance, and the like, and such references may be interchanged, depending on the context, implementation, etc. Further, the features of examples described herein may be combined with each other unless specifically noted otherwise.
Although various implementations have been shown and described in detail, the claims are not limited to any particular implementation or example. None of the above Detailed Description should be read as implying that any particular component, element, step, act, or function is essential such that it must be included in the scope of the claims. Where the phrases such as “at least one of A and B” or phrases of similar import are recited or described, such a phrase should be understood to mean “only A, only B, or both A and B.” Reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” In similar fashion, phrases such as “a plurality” or “multiple” may mean “one or more” or “at least one”, depending on the context. All structural and functional equivalents to the elements of the above-described implementations are expressly incorporated herein by reference and are intended to be encompassed by the claims appended below.
