Tin [Sn] as principal constituent

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H01L2224/81411

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

Current Industry

H01L2224/81411Tin [Sn] as principal constituent

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 12,132,002
- Issue date Oct 29, 2024
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package structure with nickel layer
- Patent number 12,125,715
- Issue date Oct 22, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Kuo-Ching Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out interconnect integration processes and structures
- Patent number 12,074,106
- Issue date Aug 27, 2024
- Applied Materials, Inc.
- Richard W. Plavidal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package
- Patent number 12,057,380
- Issue date Aug 6, 2024
- Samsung Electronics Co., Ltd.
- Myungsam Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged die and RDL with bonding structures therebetween
- Patent number 11,996,401
- Issue date May 28, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsien-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing a semiconductor device including a joint a...
- Patent number 11,894,330
- Issue date Feb 6, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chun-Lin Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Quad flat no-lead (QFN) package without leadframe and direct contac...
- Patent number 11,749,534
- Issue date Sep 5, 2023
- Deca Technologies USA, Inc.
- Robin Davis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package structure with conductive adhesive layer
- Patent number 11,728,180
- Issue date Aug 15, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Kuo-Ching Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out interconnect integration processes and structures
- Patent number 11,699,651
- Issue date Jul 11, 2023
- Applied Materials, Inc.
- Richard W. Plavidal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 11,694,960
- Issue date Jul 4, 2023
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of making wafer level chip scale pa...
- Patent number 11,676,938
- Issue date Jun 13, 2023
- JCET Semiconductor (Shaoxing) Co., Ltd.
- Ming-Che Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System-in-package with double-sided molding
- Patent number 11,670,618
- Issue date Jun 6, 2023
- STATS ChipPAC Pte. Ltd.
- DeokKyung Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged die and RDL with bonding structures therebetween
- Patent number 11,640,958
- Issue date May 2, 2023
- Taiwan Semiconductor Manufacturing Company
- Hsien-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die package with bridge layer
- Patent number 11,476,125
- Issue date Oct 18, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei Sen Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package structure with conductive adhesive layer and method fo...
- Patent number 11,302,537
- Issue date Apr 12, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Kuo-Ching Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar integrated circuit package interconnects
- Patent number 11,276,630
- Issue date Mar 15, 2022
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a pillar structure having a non-metal sidewall pro...
- Patent number 11,257,714
- Issue date Feb 22, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chien Ling Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead structure of circuit with increased gaps between adjacent leads
- Patent number 11,217,508
- Issue date Jan 4, 2022
- Sitronix Technology Corp.
- Kuo-Wei Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level integration including design/co-design, structure proce...
- Patent number 11,201,138
- Issue date Dec 14, 2021
- International Business Machines Corporation
- Bing Dang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 11,133,257
- Issue date Sep 28, 2021
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate, electronic substrate, and method for producing electroni...
- Patent number 11,094,658
- Issue date Aug 17, 2021
- Lenovo (Singapore) Pte. Ltd.
- Tadashi Kosuga
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure and manufacturing method thereof
- Patent number 11,075,155
- Issue date Jul 27, 2021
- Innolux Corporation
- Hsueh-Hsuan Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structures and methods of forming same
- Patent number 11,043,463
- Issue date Jun 22, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Hsiung Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged die and RDL with bonding structures therebetween
- Patent number 11,004,838
- Issue date May 11, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hsien-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnection structure including a metal post encapsulated by a...
- Patent number 10,971,463
- Issue date Apr 6, 2021
- Taiwan Semiconductor Manufacturing Company Ltd.
- Chun-Lin Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hollow metal pillar packaging scheme
- Patent number 10,825,804
- Issue date Nov 3, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chang-Pin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-porous copper to copper interconnect
- Patent number 10,804,241
- Issue date Oct 13, 2020
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System-in-package with double-sided molding
- Patent number 10,797,024
- Issue date Oct 6, 2020
- STATS ChipPAC Pte. Ltd.
- DeokKyung Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structures and methods of forming same
- Patent number 10,714,442
- Issue date Jul 14, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Hsiung Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET with reduced resistance
- Patent number 10,707,327
- Issue date Jul 7, 2020
- Great Wall Semiconductor Corporation
- Patrick M. Shea
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHIP PACKAGE STRUCTURE WITH NICKEL LAYER
- Publication number 20240387192
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kuo-Ching HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LIQUID METAL BASED FIRST LEVEL INTERCONNECTS
- Publication number 20240006400
- Publication date Jan 4, 2024
- Intel Corporation
- Kyle J. Arrington
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE WITH NICKEL LAYER
- Publication number 20230335411
- Publication date Oct 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kuo-Ching HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED DIE AND RDL WITH BONDING STRUCTURES THEREBETWEEN
- Publication number 20230253395
- Publication date Aug 10, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20230215791
- Publication date Jul 6, 2023
- Samsung Electronics Co., Ltd.
- Jinmo Kwon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE
- Publication number 20230154877
- Publication date May 18, 2023
- Industrial Technology Research Institute
- Yu-Ming Peng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20230119406
- Publication date Apr 20, 2023
- Samsung Electronics Co., Ltd
- Pilsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
- Publication number 20230091632
- Publication date Mar 23, 2023
- Rohm Co., Ltd.
- Satoshi KAGEYAMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20230068587
- Publication date Mar 2, 2023
- Samsung Electronics Co., Ltd.
- Yae Jung YOON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL CONNECTION PAD WITH ENHANCED SOLDERABILITY AND CORRESPON...
- Publication number 20220369455
- Publication date Nov 17, 2022
- TECHNISCHE HOCHSCHULE ASCHAFFENBURG
- Stefan Rung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE
- Publication number 20220367327
- Publication date Nov 17, 2022
- Samsung Electronics Co., Ltd.
- MYUNGSAM KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE WITH CONDUCTIVE ADHESIVE LAYER
- Publication number 20220238352
- Publication date Jul 28, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kuo-Ching HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20210384129
- Publication date Dec 9, 2021
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE WITH CONDUCTIVE ADHESIVE LAYER AND METHOD FO...
- Publication number 20210313195
- Publication date Oct 7, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Ching HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED DIE AND RDL WITH BONDING STRUCTURES THEREBETWEEN
- Publication number 20210249399
- Publication date Aug 12, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20210210450
- Publication date Jul 8, 2021
- Taiwan Semiconductor Manufacturing company Ltd.
- CHUN-LIN LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE, ELECTRONIC SUBSTRATE, AND METHOD FOR PRODUCING ELECTRONI...
- Publication number 20200373268
- Publication date Nov 26, 2020
- LENOVO (SINGAPORE) PTE. LTD.
- Tadashi Kosuga
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect Structures and Methods of Forming Same
- Publication number 20200343209
- Publication date Oct 29, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Hsiung Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for Making Multi-Die Package With Bridge Layer
- Publication number 20200266074
- Publication date Aug 20, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei Sen Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCE...
- Publication number 20200126951
- Publication date Apr 23, 2020
- International Business Machines Corporation
- Bing DANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-POROUS COPPER TO COPPER INTERCONNECT
- Publication number 20200098723
- Publication date Mar 26, 2020
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20200051902
- Publication date Feb 13, 2020
- InnoLux Corporation
- Hsueh-Hsuan Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20200043852
- Publication date Feb 6, 2020
- Intel Corporation
- Yueli Liu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Hollow Metal Pillar Packaging Scheme
- Publication number 20190341377
- Publication date Nov 7, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chang-Pin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect Structures and Methods of Forming Same
- Publication number 20190244920
- Publication date Aug 8, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Hsiung Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY PACKAGE INTERCONNECTS
- Publication number 20190172778
- Publication date Jun 6, 2019
- Intel Corporation
- Sanka GANESAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-POROUS COPPER TO COPPER INTERCONNECT
- Publication number 20190067239
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Packages and Methods of Forming the Same
- Publication number 20180374836
- Publication date Dec 27, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Hsien-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interconnect Structures and Methods of Forming Same
- Publication number 20180226373
- Publication date Aug 9, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wen-Hsiung Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY PACKAGE INTERCONNECTS
- Publication number 20180182696
- Publication date Jun 28, 2018
- Intel Corporation
- Sanka GANESAN
- H01 - BASIC ELECTRIC ELEMENTS

Tin [Sn] as principal constituent

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Bridge interconnection with layered interconnect structures

Chip package structure with nickel layer

Fan-out interconnect integration processes and structures

Semiconductor package

Packaged die and RDL with bonding structures therebetween

Methods of manufacturing a semiconductor device including a joint a...

Quad flat no-lead (QFN) package without leadframe and direct contac...

Chip package structure with conductive adhesive layer

Fan-out interconnect integration processes and structures

Bridge interconnection with layered interconnect structures

Semiconductor device and method of making wafer level chip scale pa...

System-in-package with double-sided molding

Packaged die and RDL with bonding structures therebetween

Multi-die package with bridge layer

Chip package structure with conductive adhesive layer and method fo...

Planar integrated circuit package interconnects

Method of making a pillar structure having a non-metal sidewall pro...

Lead structure of circuit with increased gaps between adjacent leads

Wafer level integration including design/co-design, structure proce...

Bridge interconnection with layered interconnect structures

Substrate, electronic substrate, and method for producing electroni...

Package structure and manufacturing method thereof

Interconnect structures and methods of forming same

Packaged die and RDL with bonding structures therebetween

Interconnection structure including a metal post encapsulated by a...

Hollow metal pillar packaging scheme

Non-porous copper to copper interconnect

System-in-package with double-sided molding

Interconnect structures and methods of forming same

MOSFET with reduced resistance

Patents Applicationslast 30 patents

CHIP PACKAGE STRUCTURE WITH NICKEL LAYER

LIQUID METAL BASED FIRST LEVEL INTERCONNECTS

CHIP PACKAGE STRUCTURE WITH NICKEL LAYER

PACKAGED DIE AND RDL WITH BONDING STRUCTURES THEREBETWEEN

SEMICONDUCTOR PACKAGE

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR PACKAGE

ELECTRICAL CONNECTION PAD WITH ENHANCED SOLDERABILITY AND CORRESPON...

SEMICONDUCTOR PACKAGE

CHIP PACKAGE STRUCTURE WITH CONDUCTIVE ADHESIVE LAYER

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

CHIP PACKAGE STRUCTURE WITH CONDUCTIVE ADHESIVE LAYER AND METHOD FO...

PACKAGED DIE AND RDL WITH BONDING STRUCTURES THEREBETWEEN

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SUBSTRATE, ELECTRONIC SUBSTRATE, AND METHOD FOR PRODUCING ELECTRONI...

Interconnect Structures and Methods of Forming Same

Methods for Making Multi-Die Package With Bridge Layer

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCE...

NON-POROUS COPPER TO COPPER INTERCONNECT

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

Hollow Metal Pillar Packaging Scheme

Interconnect Structures and Methods of Forming Same

HIGH DENSITY PACKAGE INTERCONNECTS

NON-POROUS COPPER TO COPPER INTERCONNECT

Semiconductor Packages and Methods of Forming the Same

Interconnect Structures and Methods of Forming Same

HIGH DENSITY PACKAGE INTERCONNECTS