Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
Solder ball grid arrays are also a technique sometimes used to join substrate, dies or packages, with an array of solder balls deposited on the bonding pads of a first substrate, and with a second substrate, die or package joined at its own bonding pad sites to the first pad via the solder balls. Solder balls may be formed on a pad as liquid solder, and then solidified for additional processing. The environment with the solder balls is subsequently heated to melt the solder balls and the packages compressed to cause the solder balls to contact the upper and lower pads.
For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, methods and apparatus in accordance with the present disclosure. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be appreciated that the following figures are not drawn to scale; rather, these figures are merely intended for illustration.
Embodiments will be described with respect to a specific context, namely making and using interconnects useful in, for example, WLCSP assemblies. Other embodiments may also be applied, however, to other semiconductor devices, including, but not limited to, package-on-package assemblies, die-to-die assemblies, wafer-to-wafer assemblies, die-to-substrate assemblies, in assembling packaging, in processing substrates, interposers, substrates, or the like, or mounting input components, boards, dies or other components, or for connection packaging or mounting combinations of any type of integrated circuit or electrical component.
The substrate 20 may include active and passive devices (not shown in
The substrate 20 may also include metallization layers (not shown). The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like).
The contact pad 22 may be formed over and in electrical contact with the metallization layers in order to help provide external connections to the active and passive devices. The contact pad 22 may comprise aluminum, copper, nickel, the like, or a combination thereof. The contact pad 22 may be formed using a deposition process, such as sputtering, to form a layer of material (not shown). Portions of the layer of material may then be removed through a suitable process, such as photolithographic masking and etching, to form the contact pad 22. However, any other suitable process may be utilized to form contact pad 22. The contact pad 22 may be formed to have a thickness of between about 0.5 μm and about 4 μm.
A first passivation layer 24 may be formed on the substrate 20 and over the contact pad 22. The first passivation layer 24 may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, solder resist, polybenzoxazole (PBO), benzocyclobutene (BCB), molding compound, the like, or a combination thereof. The first passivation layer 24 may be formed through a process such as chemical vapor deposition (CVD), although any suitable process may be utilized, and may have a thickness between about 0.5 μm and about 30 μm. In some embodiments, a top surface of contact pad 22 and a portion of a bottom surface of the first passivation layer 24 are substantially level.
After the first passivation layer 24 has been formed, an opening may be formed through the first passivation layer 24 to expose at least a portion of the underlying contact pad 22. This opening through the first passivation layer 24 to expose the portion of the underlying contact pad 22 allows for physical and electrical contact between the contact pad 22 and the PPI 28 (discussed further below). The opening through the first passivation layer 24 may be formed using a suitable photolithographic mask and etching process, although any other suitable process to expose portions of the contact pad 22 may alternatively be used.
The second passivation layer 26 may be formed over the contact pad 22 and the first passivation layer 24. The second passivation layer 26 may be formed from a polymer such as polyimide. Alternatively, the second passivation layer 26 may be formed of a material similar to the material used as the first passivation layer 24, such as silicon oxides, silicon nitrides, low-k dielectrics, extremely low-k dielectrics, BCB, PBO, the like, or a combination thereof. The second passivation layer 26 may be formed to have a thickness between about 2 μm and about 30 μm.
After the second passivation layer 26 has been formed, another opening through the second passivation layer 26 to expose at least a portion of the underlying contact pad 22 may be made. The opening through the second passivation layer 26 to the underlying contact pad 22 allows for physical and electrical contact between the contact pad 22 and the PPI 28 (discussed further below). The opening through the second passivation layer 26 may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of the contact pad 22 may be used.
After the opening through the second passivation layer 26 has been formed, the PPI 28 may be formed to extend through the second passivation layer 26 and to extend along the second passivation layer 26. The PPI 28 may provide electrical connection between the contact pad 22 and the subsequently formed connector 32 (see
After the PPI 28 has been formed, an optional flux 30 may be formed to the PPI 28. The flux 30 may be formed on the PPI 28 to control the spread of the subsequently formed connector 32 (see
After the application of the mold 42 and the release compound 40, the molding compound may be cured (step 408) and the mold 42 and the release compound 40 may be removed as illustrated in
As illustrated in
The molding compound 34 may be formed to support the connector 32 in later processing steps, such as reflowing the connector 32 for attaching a second substrate (see
After the mold 42 and the release compound 40 are removed, a plasma cleaning process may be performed (step 410) on the connector 32. The plasma cleaning process may be used to clean the connector 32 and to remove any residual release compound 40 or molding compound 34.
The second substrate 50 has a bond pad 52 which will be physically and electrically coupled to the connector 32. In some embodiments, the bond pad 52 may comprise a pre-solder layer, and in other embodiments, the bond pad 52 may comprise a contact pad or an under bump metallization (UBM). The bond pad 52 may comprise copper, nickel, aluminum, gold, silver, tin, the like, or a combination thereof. In an embodiment, the second substrate 50 may be bonded to the connector 32 by a reflow process. During this reflow process, the bond pad 52 on the second substrate 50 is in contact with the connector 32 to physically and electrically couple the second substrate 50 to the PPI 28. The connector 32 bonded to the bond pad 52 of the second substrate 50 may also be referred to as a bonding structure 32. In an embodiment, the second substrate 50 has a standoff height H1 from the top surface 34A of the molding compound 34 from about 20 μm to about 150 μm.
As illustrated in
The number of connectors 32, the number of bond pads 52, the number of PPIs 28, and the number of contact pads 22 in
The substrate 20, the contact pad 22, the first passivation layer 24, the second passivation layer 26, the PPI 28 may be similar to those described above and the descriptions will not be repeated herein. The connector 64 may be similar to the connector 32 described above and the description will not be repeated herein, although the connectors 64 and 32 need not be the same. The manufacture of interconnect structure 200 may be similar to interconnect structure 100 in
After the formation of the connector 64, a third passivation layer 60 may be formed on the second passivation layer 26 and the PPI 28 and surrounding a lower portion of the connector 64. The third passivation layer 60 may be formed from a polymer such as polyimide. Alternatively, the third passivation layer 60 may be formed of silicon oxides, silicon nitrides, low-k dielectrics, extremely low-k dielectrics, BCB, PBO, the like, or a combination thereof. The third passivation layer 60 may be formed to have a thickness between about 2 μm and about 30 μm.
After the third passivation layer 60 has been formed, a molding compound 62 may be formed on the third passivation layer 60 and surrounding a middle portion of the connector 64. The molding compound 62 may be similar to the molding compound 34 described above except that it is formed on the third passivation layer 60 rather than the PPI 28 and the second passivation layer 26 and the description of the molding compound will not be repeated. The molding compound may undergo similar processing as molding compound 34 such as pressure molding, curing, and plasma cleaning as described above. In some embodiments, the pressure molding and curing of the molding compound 62 may cause a portion 62B of molding compound 62 to fill between the connector 64 and the third passivation layer 60.
As illustrated in
The substrate 20, the contact pad 22, the first passivation layer 24, the second passivation layer 26, the PPI 28, and the third passivation layer 60 may be similar to those described above and the descriptions will not be repeated herein. The connector 72 may be similar to the connector 32 described above and the description will not be repeated herein, although the connectors 72 and 32 need not be the same. The manufacture of interconnect structure 300 may be similar to interconnect structure 100 in
After the formation of PPI 28, the third passivation layer 60 may be formed on the second passivation layer 26 and the PPI 28. The third passivation layer 60 was previously described and the description will not be repeated herein.
After the third passivation layer 60 has been formed, a UBM 70 may be formed on the PPI 28. An opening (not shown) may be formed through the third passivation layer 60 to expose at least a portion of the PPI 28 to allow for electrical and physical contact between the UBM 70 and the PPI 28. The opening may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose a portion of the PPI 28 may be used.
After the opening is formed through the third passivation layer 60, the UBM 70 may be formed along the third passivation layer 60 and in the opening over the PPI 28. In an embodiment the UBM 70 may comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBM 70. Any suitable materials or layers of material that may be used for the UBM 70 are fully intended to be included within the scope of the current application. In some embodiments, the PPI 28 may be formed as a UBM 28 (not shown) in a similar manner as described above for UBM 70. In these embodiments, the UBM 70 may be formed in contact with the UBM 28.
After the UBM 70 is formed, a connector 72 may be formed on the UBM 70 to electrically couple the connector 72 to the PPI 28. The connector 72 may be similar to the connectors 32 and 64 described above and the description will not be repeated herein.
After the connector 72 has been formed, a molding compound 68 may be formed on the third passivation layer 60 and surrounding the UBM 70 and a lower portion of the connector 72. The molding compound 68 may be similar to the molding compound 34 described above except that it is formed on the third passivation layer 60 rather than the PPI 28 and the second passivation layer 26 and the description of the molding compound will not be repeated. The molding compound may undergo similar processing as molding compound 34 such as pressure molding, curing, and plasma cleaning as described above.
As illustrated in
It has been found that the molding compound 34 surrounding the connectors 32 and/or the bonding structures 32 protects their shape and reduces the stress between the connectors/bonding structures and the underlying interconnect. Further, the molding compound 34 protects the underlying structures such as the PPI 28, the passivation layers 24 and 26, the contact pad 22, and the substrate 20 from the stresses of later processing steps. This protection afforded by the molding compound 34 results in improved the reliability of the interconnect structure, especially for larger dies and chips.
In an embodiment, an interconnect structure includes: a post-passivation interconnect (PPI) coupled to a first substrate; a conductive connector on the PPI; and a molding compound on a surface of the PPI, the molding compound having a concave top surface adjoining the conductive connector, the conductive connector having a first width at the adjoining concave top surface of the molding compound, the first width being in a range from 150 μm to about 180 μm, the concave top surface of the molding compound having an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate.
In some embodiments, the interconnect structure further includes: a second substrate; and a bond pad on a first surface of the second substrate, the bond pad being bonded to the conductive connector. In some embodiments of the interconnect structure, the bond pad has a second width, a ratio of the first width to the second width being from 1:1 to 1.2:1. In some embodiments of the interconnect structure, a distance between the concave top surface of the molding compound and the first surface of the second substrate is from 20 μm to 150 μm. In some embodiments, the interconnect structure further includes: a contact pad on a top surface of the first substrate; a first passivation layer on the contact pad and the top surface of the first substrate; and a second passivation layer on the first passivation layer and the contact pad, the PPI extending through the first passivation layer and the second passivation layer to physically and electrically couple the contact pad. In some embodiments of the interconnect structure, the molding compound is on the second passivation layer, the molding compound contacting a lower portion and a middle portion of the conductive connector. In some embodiments, the interconnect structure further includes: a third passivation layer on the second passivation layer, the third passivation layer contacting a lower portion of the conductive connector, the molding compound being on the third passivation layer, the molding compound contacting a middle portion of the conductive connector. In some embodiments, the interconnect structure further includes: an under bump metallization (UBM) extending through the third passivation layer to physically and electrically couple the PPI, the UBM being disposed between the PPI and the conductive connector.
In an embodiment, an interconnect structure includes: a contact pad on a surface of a first substrate; a post-passivation interconnect (PPI) contacting a surface of the contact pad; a first passivation layer on a surface of the PPI; a connector on the surface of the PPI, the first passivation layer directly adjoining a lower portion of the connector; a molding compound disposed on a surface of the first passivation layer, the molding compound covering a middle portion of the connector and exposing another portion of the connector; and a bond pad on a surface of a second substrate, the bond pad being bonded to the connector.
In some embodiments, the interconnect structure further includes: a second passivation layer on the contact pad and the surface of the first substrate; and a third passivation layer on the second passivation layer and the contact pad, the PPI extending through the second passivation layer and the third passivation layer, the first passivation layer being disposed on the third passivation layer. In some embodiments of the interconnect structure, the molding compound has a concave top surface adjoining the connector, the connector having a first width at the adjoining concave top surface of the molding compound, the bond pad having a second width, a ratio of the first width to the second width being from 1:1 to 1.2:1. In some embodiments of the interconnect structure, the concave top surface of the molding compound has an angle from about 10 degrees to about 60 degrees relative to a plane parallel with the surface of the first substrate. In some embodiments of the interconnect structure, in the first width is a range from 150 μm to about 180 μm. In some embodiments of the interconnect structure, a distance between the concave top surface of the molding compound and the surface of the second substrate is from about 20 μm to about 150 μm. In some embodiments, the interconnect structure further includes: an under bump metallization (UBM) extending through the first passivation layer to physically and electrically couple the PPI, the UBM being disposed between the PPI and the connector.
In an embodiment, an interconnect structure includes: a contact pad on a top surface of a first substrate; a first passivation layer on the top surface of the first substrate, the first passivation layer directly adjoining a first portion of a top surface of the contact pad; a second passivation layer on the first passivation layer, the second passivation layer directly adjoining a second portion of the top surface of the contact pad; a post-passivation interconnect (PPI) contacting a third portion of the top surface of the contact pad and extending along a top surface of the second passivation layer; a third passivation layer on a top surface of the PPI; a connector on the top surface of the PPI, the third passivation layer directly adjoining a lower portion of the connector; a molding compound disposed on a surface of the third passivation layer and having a concave top surface adjoining the connector, the concave top surface of the molding compound having an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate; and a bond pad on a first surface of a second substrate, the bond pad being bonded to the connector, the bond pad having a second width, the connector having a first width at an adjoining top surface of the molding compound.
In some embodiments of the interconnect structure, a ratio of the first width to the second width is from 1:1 to 1.2:1. In some embodiments of the interconnect structure, in the first width is a range from 150 μm to about 180 μm. In some embodiments, the interconnect structure further includes: an under bump metallization (UBM) extending through the third passivation layer, the UBM directly adjoining the top surface of the PPI, the connector directly adjoining a top surface of the UBM. In some embodiments of the interconnect structure, a distance between the concave top surface of the molding compound and the first surface of the second substrate is from about 20 μm to about 150 μm.
Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
This application is a continuation of U.S. patent application Ser. No. 16/384,136, filed on Apr. 15, 2019, entitled “Interconnect Structures and Methods of Forming the Same,” which is a continuation of U.S. patent application Ser. No. 15/942,692, filed on Apr. 2, 2018, entitled “Interconnect Structures and Methods of Forming the Same,” now U.S. Pat. No. 10,262,964 issued on Apr. 16, 2019, which is a continuation of U.S. patent application Ser. No. 14/991,426, filed on Jan. 8, 2016, entitled “Interconnect Structures and Methods of Forming Same,” now U.S. Pat. No. 9,935,070, issued on Apr. 3, 2018, which is a divisional of U.S. patent application Ser. No. 13/838,748, filed on Mar. 15, 2013, entitled “Interconnected Structures and Methods of Forming Same,” now U.S. Pat. No. 9,257,333, issued on Feb. 9, 2016, which claims the benefit of U.S. Provisional Application No. 61/776,684, filed on Mar. 11, 2013, entitled “Interconnect Structures and Methods of Forming Same”, which applications are hereby incorporated herein by reference. This application relates to the following co-pending and commonly assigned patent applications: Ser. No. 13/349,405, filed Jan. 12, 2012, entitled “Package on Package Interconnect Structure;” Ser. No. 13/751,289, filed Jan. 28, 2013, entitled “System and Method for an Improved Fine Pitch Joint;” Ser. No. 13/868,554, filed Apr. 23, 2013, entitled “Method for Wafer Separation;” Ser. No. 13/913,599, filed Jun. 10, 2013, entitled “Interconnect Joint Protective Layer Apparatus and Method;” Ser. No. 13/914,426, filed Jun. 10, 2013, entitled “Interconnect Structures and Methods of Forming Same;” Ser. No. 13/934,562, filed Jul. 3, 2013, entitled “Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods” and Ser. No. 13/939,966, filed Jul. 11, 2013, entitled “Apparatus for Package Reinforcement Using Molding Underfill.”
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Child | 14991426 | US |
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Child | 16923739 | US | |
Parent | 15942692 | Apr 2018 | US |
Child | 16384136 | US | |
Parent | 14991426 | Jan 2016 | US |
Child | 15942692 | US |