Patent Application
20240203892
The present invention relates to three-dimensional integrated circuit structures and circuits.
The electronics industry continues to strive for ever-increasing electronic functionality and performance in a wide variety of products, including (by way of example only) personal electronics (e.g., “smart” watches and fitness wearables), personal computers, tablet computers, wireless network components, televisions, cable system “set top” boxes, radar systems, and cellular telephones. Increased functionality and/or performance commonly translates to more transistors and other electronic components on an integrated circuit (IC) die. While the number of transistors per unit area of an IC die has increased over time as IC manufacturing process nodes have shrunk device dimensions, the two-dimensional (2-D) planar “footprint” of some IC dies has not decreased at the same rate, primarily owing to the use of more (albeit smaller) transistors to implement increased functionality and/or performance. The 2-D footprint of an IC die is one constraint on reducing the size of modules and circuit boards within products.
Accordingly, there is a need for higher-functionality integrated circuit structures that are less constrained by the 2-D footprint of an IC die.
The present invention encompasses three-dimensional (3-D) integrated circuit (IC) structures that are less constrained by the 2-D footprint of a conventional IC die. The novel 3-D IC structures combine 3-D ICs fabricated using die and/or wafer bonding technologies with embedded die packaging technology, an advanced form of laminate technology. Combining one or more 3-D ICs with embedded die packaging technology results in a high degree of integration and miniaturization by taking advantage of electrical connection pad placement on both top and bottom surfaces of the 3-D ICs, enables better integration of active components and passive components in a single IC structure, enables flexible partitioning of circuits and systems for 3-D integration, and enables low-profile 3-D IC structures that take advantage of economies of scale.
Embodiments include a 3-D IC structure including one or more 3-D IC dies embedded within a stack of one or more planar lamination layers. Other embodiments include a 3-D IC structure having a top surface and a bottom surface opposite the top surface, the 3-D IC structure including: one or more 3-D IC dies embedded within a stack of one or more planar lamination layers, wherein at least one of the one or more 3-D IC dies includes a plurality of contact die-pads on a first surface and on a second surface opposite the first surface; and one or more connection pads formed on at least one of the top surface and a bottom surface of the 3-D IC structure.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference numbers and designations in the various drawings indicate like elements.
The present invention encompasses three-dimensional (3-D) integrated circuit (IC) structures that are less constrained by the 2-D footprint of a conventional IC die. The novel 3-D IC structures combine 3-D ICs fabricated using die and/or wafer bonding technologies with embedded die packaging technology, an advanced form of laminate technology. Combining one or more 3-D ICs with embedded die packaging technology results in a high degree of integration and miniaturization by taking advantage of electrical connection pad placement on both top and bottom surfaces of the 3-D ICs, enables better integration of active components as well as passive components, enables flexible partitioning of circuits and systems for 3-D integration, and enables low-profile 3-D IC structures that take advantage of economies of scale.
It may be useful to review how 2-D metal-oxide-semiconductor field effect transistor (MOSFET) circuitry is fabricated using a conventional silicon-on-insulator (SOI) process. Starting with a wafer substrate, such as silicon, an insulating buried oxide (BOX) layer is formed, on which an active layer is formed, typically of doped silicon. On and/or within the active layer, one or more MOSFET structures are formed within the bounds of an individual IC die (unsingulated at this point). Each wafer substrate typically includes hundreds to thousands of unsingulated dies.
A MOSFET structure generally includes a mask-formed channel, a gate, a source, a drain, and isolation regions. The IC fabrication process up to this point is generally considered the front-end-of-line (FEOL) where individual devices (transistors, capacitors, resistors, inductors etc.) are patterned in or on the active layer. The FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers, and may be regarded as fabrication of die substructures.
After the last FEOL step, a wafer contains multiple die regions each including isolated transistors without any interconnecting conductors. The back-end-of-line (BEOL) is the second portion of IC fabrication where the individual devices (transistors, capacitors, resistors, inductors, etc.) within a die region are interconnected with conductors formed as part of or spanning one or more metal interconnect layers. BEOL includes fabrication of electrical contacts (pads), vias, insulating layers (dielectrics), metal levels, and bonding sites for die-to-package connections. In some applications, “through-silicon vias” (TSVs) may be fabricated, each TSV passing through the wafer substrate between the active layer and a connection point, such as a bond pad.
Some BEOL fabrication processes or post-BEOL fabrication processes (e.g., as part of outsourced semiconductor assembly and test) allow application of a redistribution layer (RDL), which is generally an extra patterned conductive layer (commonly aluminum) on an IC die that makes the input/output (I/O) pads of an IC die available to be coupled to other locations of the die, and/or to another IC die, and/or to specialized packaging structures. The RDL may be formed on top of the “upper” BEOL superstructure of an IC die. In some cases (for example, for single-layer transfer or SLT die structures), the RDL may be formed adjacent to a primary circuit layer containing active FET regions after removal of the wafer substrate and re-attachment of the primary circuit layer and superstructure to a handle wafer.
Thus, a 2-D MOSFET IC die is essentially formed in two parts, a “lower” FEOL substructure and an “upper” BEOL superstructure formed within a die region of a wafer. After FEOL and BEOL processing, the wafer undergoes a number of additional known process steps, including dicing, testing, and packaging, to form multiple IC dies. While a MOSFET IC die is actually made by building up multiple layers, and thus technically is a three-dimensional structure, the layers are extremely thin, and by convention such MOSFETs are considered to be two-dimensional structures.
In order to shrink the 2-D footprint of an IC die, a number of 3-D technologies have been developed that have focused on stacking and bonding aligned IC dies originally fabricated on different wafers (also known as wafer-to-wafer bonding), stacking and bonding individual IC dies on non-singulated IC dies on a wafer (also known as die-to-wafer bonding), and stacking and bonding an individual IC die on another IC die (also known as die-to-die bonding). One such technology may be referred to as “hybrid bonding interconnect” (HBI), in which circuitry is fabricated on different wafers or dies and then vertically stacked and interconnected in a 3-D structure. Bonding of the two wafers/dies generally uses both dielectric materials (e.g., silicon dioxide, SiCN, SiCOH, and/or analogous alloys) and conductive interconnect materials (e.g., copper, aluminum, and/or their alloys). In general, a high density of interconnects between the top and bottom wafers/dies is desirable to achieve good communications between them. The interconnect pitch can be between about 0.2 to 10 μm, and preferably in approximately the 2-5 μm range. HBI technology has a demonstrated high interconnect density, is a planar technology that does not require underfill or carrier wafer integration, and enables formation of interconnects between two IC wafers/dies during the bonding stage of processing at relatively low temperatures (e.g., <400)° ° C.
Another stacking-and-bonding technology for shrinking the 2-D footprint of an IC die utilizes thermo-compression bonding of pillar bumps on mated ICs. Thermo-compression bonding is also referred to as diffusion bonding, pressure joining, thermocompression welding, or solid-state welding. Pillar bumps may be made of copper with a contact-end coated in nickel and then silver or tin (e.g., solder). Two IC chips that include corresponding aligned pillar bumps are mated together while applying force and heat simultaneously, thereby creating an electrical coupling between mated conductors. Atoms migrate between the metallic crystal lattices of the two components based on crystal lattice vibration, which adheres the interfaces together. This method enables direct electrical interconnection between two structures without additional steps.
Another technology for shrinking the 2-D footprint of an IC die utilizes 3-D embedded die packaging. For example, an individual IC die may be embedded in a substrate layer (typically an organic material such as a laminate), with conductive (e.g., copper) interconnects or “vias” electrically coupling to connection points (e.g., die-pads, connection pads, bump, or pins) for internal and/or external connections. The embedded-die substrate layer on which an IC die is embedded essentially functions as a printed circuit board. One method of building up connections is by using conventional BEOL processes (e.g., sequential formation of one or more dielectric layers or conductive layers around an embedded IC die, including formation of interlayer connections such as vias). Another method of building up connections is by laminating multiple layers designed to accommodate an embedded IC die and containing horizontal and vertical conductors. After initial lamination, additional laminated layers may be added and/or conventional BEOL processes may be applied post-lamination to form additional structures, layers, and/or connection pads.
In the illustrated example, some of the horizontal conductors 106 contact die-pads 110 that form part of the 3-D IC die 102. Connection pads 112 are shown formed on the top and bottom surfaces of the lamination layers 104, thus allowing connections to the 3-D IC die 102 and other components (e.g., resistors, capacitors including supply capacitors, inductors) that may be included within the lamination layers 104. In some embodiments, one or more connection pads 112 may be formed on only one of the top and bottom surfaces of the lamination layers 104. In some embodiments, the connection pads 112 may be omitted from a surface that is to be subjected to hybrid bonding or the like.
In some embodiments, external components may be attached to the exterior of the 3-D IC structure 100. For example, in
The completed 3-D IC structure 100 with attached external components may be overmolded to form a robust chip-scale package (CSP) that may be utilized in subsequent processes like a 2-D integrated circuit, such as by attachment to other structures (e.g., interposers, die modules, or printed circuit boards).
The 3-D IC die 102 embedded in the 3-D IC structure 100 of
The 3-D IC die 102 of
After bonding of DIE 1 and DIE 2, contact die-pads 110 are exposed on both the top and the bottom surfaces of the combined dies and thus enable a greater number of interconnections to the 3-D IC die 102 within the 3-D IC structure 100 compared to a conventional 2-D IC die. Other advantages of the 3-D IC die configuration of
The example 3-D IC structure 100 shown in
As another example,
As should be clear, the examples shown in
Applications of the present invention are numerous. For example,
It is common for an antenna switch to need at least one relatively large capacitor (e.g., 1.5 μF) for proper operation. In conventional antenna switches, such an external supply capacitor is coupled between a contact die-pad of the antenna switch IC and circuit ground. However, applying the present invention, the illustrated antenna switch 500 may be implemented as a single 3-D IC structure that includes an embedded capacitor C, as in the example shown in
Regarding MLCCs of the type shown in the examples of this disclosure, one method of fabricating such MLCCs may be based on a combination of multi-layer ceramic capacitor (MLCC) and low temperature-co-firing-ceramic (LTCC) technology. For example, pre-milled ceramic dielectric powder may be mixed with a suitable amount of binder (typically an organic polymer) to make a dielectric “green” sheet. The ceramic powder may be, for example, barium titanate (BaTiO3). Internal electrodes may be formed by printing (e.g., screen printing) a conductive paste (e.g., nickel) on the green sheet to form multiple sets of parallel capacitor plates. At a later stage, the sets of parallel capacitor plates can be separated (diced) to form individual discrete capacitors.
Multiple printed green sheets may then be stacked together and pressed (laminated). The number of stack layers and the total layer thickness are pre-determined to achieve a target capacitance value. Through-vias may be formed and then filled with a suitable conductor, such as copper or aluminum. Through-vias may be formed using a number of techniques, including laser drilling through the laminated stack. In alternative processes, through-vias may be formed before capacitor plate printing and stacking by punching holes through the green sheet and filling the holes with a conductor. A single discrete capacitor structure may be internally divided into an array of two or more capacitor cells or partitions, with the partitions being electrically isolated from each other.
Surface termination electrodes or pads may be printed to connect to the through-vias, and then the multi-layered laminated green sheet may be loaded into a furnace for binder burnout and sintering. The sintering temperature of BaTiO3, prepared by a conventional mixed-oxide method, is in general considerably above 1200° ° C. to obtain dense ceramic bodies. Sintering temperatures of about 1100° C. are possible using nano-sized BaTiO3 and a two-step sintering procedure. However, such temperatures are well above common IC fabrication temperatures, particularly for CMOS ICs (generally below about 300° C.).
In some processes, additional printing of conductors may be done. The individual capacitors may then be separated from each other, and electrically tested and screened for capacitance, dissipation factor, and intrinsic resistance values. In some processes, testing may occur before singulation.
As should be apparent, MLCC fabrication by means of stacking and laminating layers concurrently differs from semiconductor device fabrication, where layers are generally processed serially, with each new layer fabricated on previous layers.
As noted above, embodiments of the present invention are not limited to use of MLCC capacitors, but include other known capacitor structures, including (but not limited to), ceramic capacitors, tantalum capacitors, aluminum electrolytic capacitors, and conductive polymer capacitors.
Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.
As one example of further integration of embodiments of the present invention with other components,
The substrate 600 may also include one or more passive devices 606 embedded in, formed on, and/or affixed to the substrate 600. While shown as generic rectangles, the passive devices 606 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 600 to other passive devices 606 and/or the individual ICs 602a-602d. The front or back surface of the substrate 600 may be used as a location for the formation of other structures.
Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.
Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, bc) protocols, as well as other radio communication standards and protocols.
The current invention enables 3-D IC structures within increased functionality that are less constrained by the 2-D footprint of a conventional IC die. Embodiments of the present invention enable smaller end-use products and shorter signal paths between IC dies, which may, for example, improve range, quality of reception, power usage, and bandwidth in radio frequency applications.
Another aspect of the invention includes methods for fabricating 3-D IC structures. For example,
Additional aspects of the above method may include one or more of the following: forming at least one conductive path within the one or more planar lamination layers connecting at least one of the plurality of contact die-pads to at least one of the one or more connection pads; attaching at least one electronic, electromechanical, and/or electro-optical component to at least one of the one or more connection pads; wherein the at least one component is a capacitor; wherein the at least one component is a multi-layer ceramic capacitor including interdigitated electrically-isolated internal electrodes, internal via-type main electrodes connected to respective sets of the internal electrodes, and connection pads located on a bonding surface of the multi-layer ceramic capacitor and connected to respective ones of the internal via-type main electrodes; wherein the at least one of the one or more 3-D IC dies comprises first and second 2-D IC dies each having a substrate, wherein the first and second 2-D IC dies are bonded together such that the substrate of the first 2-D IC die faces the substrate of the second 2-D IC die; wherein the substrate of at least one of the first and second 2-D IC dies is thinned before bonding; wherein the at least one of the one or more 3-D IC dies comprises first and second two-dimensional IC dies each having a substrate and a substructure/superstructure formed on the substrate, wherein the first and second 2-D IC dies are bonded together such that the substructure/superstructure of the first 2-D IC die faces the substrate of the second 2-D IC die; wherein the at least one of the one or more 3-D IC dies comprises first and second two-dimensional IC dies each having a substrate, a substructure formed on the substrate, and a superstructure formed on the substructure, wherein the first and second 2-D IC dies are bonded together such that the substructure of the first 2-D IC die faces the substrate of the second 2-D IC die and the substrate of the first 2-D IC die is removed; wherein the at least one of the one or more 3-D IC dies comprises a substrate having a first surface and a second surface opposite the first surface, wherein the first surface is processed to form a combined substructure/superstructure on the first surface and the second surface is processed to form a combined substructure/superstructure on the second surface; placing at least two 3-D IC dies horizontally spaced with respect to each other within the 3-D IC structure; and/or placing at least two 3-D IC dies vertically spaced with respect to each other within the 3-D IC structure.
The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.
With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.
Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar junction transistors (BJTs), BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, MESFET, InP HBT, InP HEMT, FinFET, GAAFET, and SiC-based power device technologies, using 2-D, 2.5-D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.
It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).
