3791024

Information

• Patent Grant
• 3791024

• References
• Source

• Patent Number

  3,791,024

• Date Filed

  Not available

• Date Issued

  Tuesday, February 12, 1974
  50 years ago

• CPC

  • H01L27/0688 - Integrated circuits having a three-dimensional layout
  • H01L21/00 - Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/76264 - SOI together with lateral isolation
  • H01L21/764 - Air gaps
  • H01L21/8221 - Three dimensional integrated circuits stacked in different levels
  • H01L21/86 - the insulating body being sapphire, e.g. silicon on sapphire structure
  • H01L23/522 - including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L21/76289 - Lateral isolation by air gap
  • H01L2924/0002 - Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
  • Y10S148/008 - Bi-level fabrication
  • Y10S148/085 - Isolated-integrated
  • Y10S148/122 - Polycrystalline
  • Y10S148/15 - Silicon on sapphire SOS

• US Classifications

  • 438 - Semiconductor device manufacturing: process
  • 148 - Metal treatment
  • 257 - Active solid-state devices