Patent Application
20180337140
The present technology relates to high density integrated circuit devices, including three-dimensional 3D memory devices, which can be subject to deformation stress during manufacturing.
3D integrated circuits comprise stacks of material having multiple planes of circuit elements disposed in a stack. For example, technologies for stacking multiple levels of memory cells to achieve greater storage capacity have been developed. Researchers have developed various structures, such as Bit Cost Scalable (BiCS) memory, Terabit Cell Array Transistor (TCAT) and Vertical NAND (V-NAND). For these types of structures, and other complex structures that comprise stacks of active layers separated by insulating (or inactive) layers, it is often useful to form conductors or other circuit elements connecting layers deep in the stacks with upper layers or with patterned metal layers over the stacks used for connection to peripheral circuits.
However, the formation of these conductors or other circuit elements can be difficult. Once the stack is etched to define patterns in an intermediate structure which can include high aspect ratio trenches, the intermediate structure tends to deform as a result of manufacturing processes or environments.
It is desirable to provide a 3D integrated circuit structure with reduced deformation. This can improve the quality of circuit elements extending through or into the stacks, and improve alignment tolerances for the BEOL routings and other structures.
A process for making a buttress structure and the resulting structure are described, which can oppose stress-induced deformation of the device being formed.
In one aspect, an integrated circuit described herein comprises a stack region and a region outside the stack region over a substrate; a stack including a plurality of layers disposed in the stack region; a plurality of circuit elements extending through the stack; and a buttress structure disposed around the stack region, the buttress structure comprising a fence-shaped, electrically passive element configured to oppose expansion of materials in the region outside the stack region in a direction toward the stack region.
In another aspect, a method of manufacturing an integrated circuit described herein comprises forming a stack including a plurality of layers in a stack region on a substrate; forming a buttress structure around the stack; etching through the plurality of layers in the stack to form a pattern of openings in the stack, after forming the buttress structure; and filling at least some of the openings in the stack with conductive or semiconductive material to form circuit elements in the stack.
In yet another aspect, an integrated circuit described herein comprises a stack of active and inactive layers disposed over a substrate; a plurality of vertical conductors extending through the stack of active and inactive layers; and a region surrounding the stack including a buttress structure in a fill material, wherein the buttress structure comprises a material having a Young's modulus greater than the fill material.
Other aspects and advantages of the present technology can be seen on review of the drawings, the detailed description and the claims, which follow.
A detailed description of embodiments of the present invention is provided with reference to
Stair step structures are disposed in regions 301, 302, 303, 304 and can be configured as word line landing pads for example along the sides of the stack or stacks in this example. In another example, the stair step structures can be disposed in the other layout configurations, such as in the middle of the stack or stacks. The number and location of the stair step structures are changeable depending on the device layout and design.
A buttress structure 330 is disposed around the stack region 310 and comprises a fence-shaped, electrically passive element disposed in a fill material in a closed polygonal line surrounding the stack region. The fence-shaped, electrically passive element is configured to oppose expansion of materials in the region 320 in a direction toward the stack region 310. The fence-shaped, electrically passive element is a unitary element and has a closed rectangular shape in this example. The buttress structure 330 is electrically passive in the sense that it does not have any circuit functions. The electrically passive buttress structure 330 is isolated from the ground potential and other voltage sources. In some embodiments, the buttress structure may not be isolated, for example, but does not contribute to the electrical function of the circuit. In some embodiments, the buttress structure can extend through, or have a depth as deep as, multiple layers in the stack.
The buttress structure is disposed in an intermediate region between the stack region and structures that form peripheral circuits outside the stack region in a peripheral region. There are no conductive lines that extend through the intermediate region in which the buttress is formed from the stack to the peripheral circuits in this example. Rather all electrical connections between the circuit elements in the stack and the peripheral circuits are formed in patterned conductors over the buttress structure, or beneath the buttress structure.
The buttress structure 330 may comprise a material having a Young's modulus greater than the fill material in which it is disposed, in one embodiment. The buttress structure 330 may comprise a gap in another embodiment.
The device comprises a structure forming peripheral circuits in the region 320 outside the stack region 310 composed mostly of a peripheral circuit fill material, at least at elevations proximal to upper layers of the stack. The buttress structure 330 may comprise a material having a Young's modulus greater than the peripheral circuit fill material.
The device can comprise a 3D memory including the stack, through which a plurality of circuit elements, such as filled-trench vertical conductors, and a plurality of memory pillars (not shown) between pairs of the vertical conductors are disposed.
Prior to formation of openings such as elongated trenches in the stack used for forming the circuit elements 371 (vertical conductors), the buttress structure 330 is formed around the stack region 310.
Depending on the layout or other design rules, the buttress structure may have, but is not limited to, the configurations and shapes as shown in
In one example, the memory layer comprises first, second and third layers. The first layer of the memory layer 521 is formed on the sidewalls of the openings and can comprise silicon oxide having a thickness of about 50 Å to 130 Å, and act as a blocking layer. Other blocking dielectrics can include high-κ materials like aluminum oxide of 150 Å.
The second layer of the memory layer 521 is formed on the first layer, and can comprise silicon nitride having a thickness of about 40 Å to 90 Å, and act as a charge trapping layer. Other charge trapping materials and structures may be employed, including, for example, silicon oxynitride (SixOyNz), silicon-rich nitride, silicon-rich oxide, trapping layers including embedded nano-particles and so on.
The third layer of the memory layer 521 is formed on the second layer and can comprise silicon oxide having a thickness of about 20 Å to 60 Å, and act as a tunneling layer. In another example, other tunneling materials and structures may be employed, for example, composite tunneling structure.
A composite tunneling structure can comprise a layer of silicon oxide less than 2 nm thick, a layer of silicon nitride less than 3 nm thick, and a layer of silicon oxide less than 4 nm thick. In one embodiment, the composite tunneling structure consists of an ultrathin silicon oxide layer O1 (e.g. ≤15 Å), an ultrathin silicon nitride layer N1 (e.g. ≤30 Å) and an ultrathin silicon oxide layer O2 (e.g. ≤35 Å), which results in an increase in the valence band energy level of about 2.6 eV at an offset 15 Å or less from the interface with the semiconductor body. The O2 layer separates the N1 layer from the charge trapping layer, at a second offset (e.g. about 30 Å to 45 Å from the interface), by a region of lower valence band energy level (higher hole tunneling barrier) and higher conduction band energy level. The electric field sufficient to induce hole tunneling raises the valence band energy level after the second location to a level that effectively eliminates the hole tunneling barrier, because the second location is at a greater distance from the interface. Therefore, the O2 layer does not significantly interfere with the electric field assisted hole tunneling, while improving the ability of the engineered tunneling dielectric to block leakage during low fields.
The deposition techniques applied to form the composite, multilayer film can be carried out by low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), other suitable methods, or combinations.
Next, an etch process is carried out to remove the memory layer 521 on the top of the stack and at the bottom of the openings. A thin film 522 is then deposited over the stack and has a portion in contact with the substrate 500 at the bottom of the openings. The thin film 522 can comprise a semiconductor adapted by choice of material, e.g. silicon, and doping concentrations, e.g. undoped or lightly doped, to act as vertical channel structures.
After formation of the semiconductor thin film 522, a fill-in process is implemented using a spin-on dielectric (SOD), for example silicon oxide or other insulating materials, to fill the space between the thin film 522 within the openings, followed by a CMP process to remove the SOD on the top of the fill material 520 and an etch process to remove the SOD in the upper portions of the openings. So the insulating structures 523 are formed inside the pillars. In one example, the insulating structure 523 can be completely filled with the SOD, and be free of void and seam. In another example, a seam or a void may exist in the insulating structure 523.
Next, a conductive material, for example polysilicon, is deposited to fill the upper portions of the openings, followed by CMP and/or etch back processes to form the plugs 524, thereby providing contact areas for connections from the vertical channel pillars for vertical strings of memory cells, to the corresponding overlying patterned conductors (not shown). A salicide process is optionally applied to lower the resistance for better conductivity. In another example, the plugs 524 may comprise doped polysilicon.
In yet another example, the insulating structure 523 can be a seam or a gap, which is formed during the deposition of the thin film 522. The overhangs formed on the top of the inside surface of the thin film 522 may connect together so as to form the seam or gap enclosed by the thin film 522. The plugs 524 are therefore formed by the overhangs being connected.
In yet another example, the thin film 522 completely fills the openings in the stack, and therefore, the insulating structure 523 and the plugs 524 do not exist.
Using a material with a greater Young's modulus than the fill material used in the peripheral circuits, or in the region in which the buttress is formed, results in a buttress structure more rigid than the fill material, and will resist deformation in the stack by the thermal expansion of materials outside the buttress structure in the following manufacturing processes.
In some embodiments, the buttress structure can comprise a gap, alone or in combination with a fence-shaped element or elements, at least during stages of the manufacturing process in which the stress is to be offset by the buttress structure, which allows the device to have more space to absorb the thermal expansion.
The buttress structure 532 can extend into the fill material 520 to a depth at an elevation proximal to the bottom layer of the stack, such that the buttress structure 532 is in contact with the substrate. In some embodiments, the buttress structure 532 can have a depth at an elevation proximal to the intermediate layer of the stack and does not contact the substrate 500.
Next, in this example a gate replacement process is implemented which can further increase the susceptibility of the stack to deformation stresses. The gate replacement process in this example comprises (1) removing the sacrificial layers (e.g. 511, 513, 515, 517 of
After the gate replacement process, the stack comprises active layers consisting of active circuit elements such as the metal gates (e.g. 551, 552, 553, 554). The memory cells are disposed at the interface regions between the active layers and the pillars. In this embodiment, the active layers acts as the word lines surround the pillar and constitutes the all-around gates. The memory cells have gate-all-around configuration.
Next, an insulator 560 is deposited covering the sidewalls of the openings (e.g. 561, 562) and filling the recesses on the sidewalls. In one example, the insulator 560 is formed at a low temperature, for example 25° C. to form an oxide layer. In another example, the insulator 560 can comprise materials other than silicon oxide and be formed using other deposition techniques, such as CVD, ALD, and PVD. Then, an etch process is applied to remove the insulator 560 at the bottom of the elongated trenches.
An anneal process up to a temperature about 1000° C., for example, is implemented to solidify the insulator 560. The high temperature tends to cause thermal expansion and induce deformation. The buttress structure 532 formed prior to the anneal process would oppose expansion of materials outside the stack region in a direction toward the stack region.
The material suitable for the barrier layer 565 of the circuit elements (e.g. 571, 572) in form of the vertical conductor in this example may comprise silicon nitride (SiN), Titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), other metal alloys, or combinations thereof.
The material suitable for the conducting layer 567 of the circuit elements (e.g. 571, 572) in form of the vertical conductor in this example may comprise polysilicon, amorphous silicon, Titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), copper (Cu), cobalt (Co), other metals and metal alloys, or combinations thereof.
In another embodiment, the barrier layer 565 can be omitted where the conductive layer 567 comprises for example polysilicon or other materials, which can provide good adhesion between the insulator 560 and the conducting layer 567.
A first plurality of patterned conductors (not shown) overlying the stack is connected by interlayer conductors through vias aligned with the circuit elements 571, 572 (i.e. vertical conductors in this example) and to a source of a reference voltage, configured as a common source line. As such, an electrical conductor over the stack is connected to one or more of the circuit elements. Also, a second plurality of patterned conductors (not shown) overlying the stack connects the plurality of pillars to a voltage supply, providing bit line voltages to the corresponding vertical channel structures of the pillars, configured as bit lines. In addition, a third plurality of patterned conductors (not shown) overlying the stack is connected to the corresponding active layers through contacts in the stair step structure (word line landing pad), configured as word lines. The patterned conductors and interlayer conductors in the vias can be formed by aligning a mask with one or more of the circuit elements in the stack; and using the aligned mask, making an electrical conductor over the stack connecting to the one or more of the circuit elements in the stack. Because of the use of the buttress structure before forming the openings used for the circuit elements 571, 572 (vertical conductors), the alignment can be accomplished with greater accuracy, allowing for denser circuit structures.
The process includes forming control circuitry in the peripheral region outside the stack region, configured to apply different bias voltages to the active layers and pillars in the stack, and can be configured to execute a program operation by which one, or more than one, bit of data can be stored in a selected memory cell.
In other examples, the buttress structure in the cross-section can be bowed (e.g. structure 1032B in
The depth (HB) of the buttress structure is defined for the purposes of this description by the elevation of a lower surface 1050 relative to the bottom active layer in the stack. The lower surface 1050 is at an elevation less than the depth (Hc) of the vertical conductors in the illustrated example, and below the bottom active layer. The buttress structure can have a depth (HB) so that the lower surface 1050 is at a minimum depth as low as one tenth of the height of the stack and less than one tenth the thickness of the fill material 1020. The depth (HB) of the buttress structure can be greater than the depth (Hc) of the vertical conductors in the other embodiments.
In one embodiment, the buttress structure comprises a higher Young's modulus material than the fill material in which it is disposed, to increase the rigidity of the structure and to diminish the deformation.
In another embodiment, the buttress structure comprises a gap alone or in combination with a solid material, to create space to absorb the thermal expansion so as to release the stress and diminish the deformation.
An SSL/GSL decoder 940 is coupled to a plurality of SSL/GSL lines 945, arranged in the memory array 960. A level decoder 950 is coupled to a plurality of word lines 955. A global bit line column decoder 970 is coupled to a plurality of global bit lines 965, arranged along columns in the memory array 960 for reading data from and writing data to the memory array 960. Addresses are supplied on bus 930 from control logic 910 to decoder 970, decoder 940 and decoder 950. Sense amplifier and program buffer circuits 980 are coupled to the column decoder 970, in this example via first data lines 975. The program buffer in circuits 980 can store program codes for multiple-level programming, or values that are a function of the program codes, to indicate program or inhibit states for selected bit lines. The column decoder 970 can include circuits for selectively applying program and inhibit voltages to bit lines in the memory in response to the data values in the program buffer.
Sensed data from the sense amplifier/program buffer circuits 980 are supplied via second data lines 985 to multi-level data buffer 990, which is in turn coupled to input/output circuits 991 via a data path 993. Also, input data is applied in this example to the multi-level data buffer 990 for use in support of multiple-level program operations for each of the independent sides of the independent double gate cells in the array.
Input/output circuits 991 drive the data to destinations external to the integrated circuit 901. Input/output data and control signals are moved via data bus 905 between the input/output circuits 991, the control logic 910 and input/output ports on the integrated circuit 901 or other data sources internal or external to the integrated circuit 901, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the memory array 960.
In the example shown in
applying a reference voltage to common source lines, such as biasing the conductive layer on the substrate via the vertical conductors described herein;
selecting a layer of memory cells in the array, such as using a word line layer decoder;
selecting vertical channel structures in a selected row in the array such as by using SSL switches and GSL switches on the rows of vertical channel structures; and
storing charge in charge trapping sites in the selected layer on the selected row of vertical channel structures in the array, to represent data using bit line circuitry like page buffers on global bit lines coupled to the selected row of vertical channel structures.
In some embodiments, the logic is configured to select a layer, such as by controlling word line layer decoders.
In some embodiments, the logic is configured to store multiple levels of charge to represent more than one bit of data in the charge trapping sites in the selected layer on the selected row of vertical channel structures in the array. In this manner, a selected cell in the array stores more than two bits, including more than one bit on each cell.
The control logic 910 can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the control logic comprises a general-purpose processor, which can be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor can be utilized for implementation of the control logic.
The buttress structure described herein can be implemented in other 3D structures and circuits, and in other complex structures.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. What is claimed is:
