Patent Application
20250167154
For AESA radiating elements at high frequency (mmwave bands), the space available for necessary components is very small. The frequency of operation defines lattice spacing and thereby creates the available envelope. As frequencies trend higher, the available space continues to shrink. Despite space limitations, systems require power supply decoupling capacitance, precision calibrated resistors, and high capacitance for pulsed applications.
Electrical interconnects in a single printed circuit board traverse a significant path length through traces, and packaging that creates significant electrical loss. Furthermore, manufacturing processes make single printed circuit board solutions difficult. RF performance requires unbalanced printed circuit board stack-ups and unique material sets. Because of the differences in thermal expansion coefficients, these unbalanced stack-ups cause the printed circuit board to bow and twist; bowing and twisting causes assembly issues for large footprints and large BGA components resulting in low yields.
Complexity, (large number of processing steps for a single printed circuit board) increases production cost through yield loss. Damage at any process causes the entire card, including radio-frequency integrated circuits, to be replaced at significant cost.
In one aspect, embodiments of the inventive concepts disclosed herein are directed to a package including multiple separate circuit cards. The package addresses the inherent imbalance associated with complex radiating structures by separating the overall imbalanced constructions into sub constructions comprised of significantly more balance. An unbalanced, single circuit card is separated into multiple individual circuit cards with balanced stacks. The beamforming circuitry, antenna, power distribution, and control circuitry may be embodied in separate circuit cards.
In a further aspect, the beamforming circuitry and amplifiers may include pads for electronic connectivity on both a top surface and a bottom surface. Internal vias create electronic connectivity between the top surface and bottom surface.
In a further aspect, an antenna card may connect to the beamforming circuitry via pads on the top surface of the circuit card.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and should not restrict the scope of the claims. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments of the inventive concepts disclosed herein and together with the general description, serve to explain the principles.
The numerous advantages of the embodiments of the inventive concepts disclosed herein may be better understood by those skilled in the art by reference to the accompanying figures in which:
Before explaining various embodiments of the inventive concepts disclosed herein in detail, it is to be understood that the inventive concepts are not limited in their application to the arrangement of the components or steps or methodologies set forth in the following description or illustrated in the drawings. In the following detailed description of embodiments of the instant inventive concepts, numerous specific details are set forth in order to provide a more thorough understanding of the inventive concepts. However, it will be apparent to one of ordinary skill in the art having the benefit of the instant disclosure that the inventive concepts disclosed herein may be practiced without these specific details. In other instances, well-known features may not be described in detail to avoid unnecessarily complicating the instant disclosure. The inventive concepts disclosed herein are capable of other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting.
As used herein a letter following a reference numeral is intended to reference an embodiment of a feature or element that may be similar, but not necessarily identical, to a previously described element or feature bearing the same reference numeral (e.g., 1, 1a, 1b). Such shorthand notations are used for purposes of convenience only, and should not be construed to limit the inventive concepts disclosed herein in any way unless expressly stated to the contrary.
Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).
In addition, use of “a” or “an” are employed to describe elements and components of embodiments of the instant inventive concepts. This is done merely for convenience and to give a general sense of the inventive concepts, and “a” and “an” are intended to include one or at least one and the singular also includes the plural unless it is obvious that it is meant otherwise.
Also, while various components may be depicted as being connected directly, direct connection is not a requirement. Components may be in data communication with intervening components that are not illustrated or described.
Finally, as used herein any reference to “one embodiment,” or “some embodiments” means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the inventive concepts disclosed herein. The appearances of the phrase “in at least one embodiment” in the specification does not necessarily refer to the same embodiment. Embodiments of the inventive concepts disclosed may include one or more of the features expressly described or inherently present herein, or any combination or sub-combination of two or more such features.
Broadly, embodiments of the inventive concepts disclosed herein are directed to a package including a die(s) and other electronic components and a plurality of pads disposed on a top surface of the package, connected to the die by vias. The die may be connected to an interposer through the overmold, wire bonds, solder joints or similar area array connections. The interposer may be affixed to a host circuit board. Electronic components may be affixed to the top surface of the package and reflowed before or after the die is encapsulated.
The present disclosure enables microelectronics packaging to allow more efficient use of volume on an AESA assembly while minimizing the complexity of the PCBs that need to be designed.
Referring to
In at least one embodiment, a top surface of the die 100 may be exposed (not covered by any over mold 102). In such embodiments, pads 104, 106, 108 may be in direct electronic communication with the die 100, without any intervening vias 110, 112, 114.
In at least one embodiment, the die 100 is in electronic communication with one or more pads 116 disposed on a bottom surface of the die 100/over mold 102. In at least one embodiment, the one or more pads 116 are connected to a bottom surface of the die 100 by corresponding vias. Alternatively, or additionally, the one or more pads 116 are connected to a bottom surface of the die 100 by an interposer 118. The interposer 118 includes top pads disposed to enable electronic connectivity with the die 100 at a top surface, and bottom pads disposed to engage solder joints or joints made with other conducting materials to create electronic connectivity with a host circuit board 120. Vias create electronic connectivity between the top pads and bottom pads within the interposer 118.
In at least one embodiment, a via 122 may connect a pad 124 on a top surface of the die 100/over mold 102 to the interposer 118 directly, without interfacing with the die 100.
Referring to
In at least one embodiment, the first card 200 defines a beamforming card including beamforming integrated circuit components 204, 206 and one or more amplifiers/beamformers 208, 210. In may be appreciated that the amplifiers/beamformers 208, 210 may be represented in more detail in
The one or more second cards 202, including radiating structures, may include pads disposed on a bottom surface to allow electronic communication between the radiating structures and the beamforming components 208,210 when disposed above the first card 200; supporting electronics 204, 206 may be disposed on a bottom surface of the first card 200. In at least one embodiment, the first card 200 may be connected to the one or more second cards 202 via conductive elastomer pins 212, 214 disposed to engage the pads on the bottom surface of the one or more second cards 202 and pads on the top surface of the first card 200 (either directly or via the one or more amplifiers/beamformers 208, 210. Other connection types such as sponge-like cylindrical electrical interconnects, copper pillar, solder bumping or the like are envisioned.
Embodiments may utilize monolithic, waveguide, slot, helix, coil, microstrip patch radiating elements, or the like.
Embodiments of the present disclosure enable methods to shrink the size of the unit cell to allow higher frequency operation. Components are disposed vertically and connected through solder pads and/or vias to a die. Pads are disposed on both the top and the bottom side of the die for low inductance paths. Embodiments increase functional density to facilitate development of higher frequency antennas.
Radiating element may be disposed on a separate card and can be tuned/changed. Furthermore, while two cards have been illustrated and described, multiple separate cards are envisioned as necessary to create balanced stacks and reduce the impact of thermal expansion.
Separating the stack into smaller components facilitates fabrication via a Z-axis, additive fabrication processes. Such processes would otherwise be incompatible with existing fabrication processes. Furthermore, because materials with differing coefficients of thermal expansion can be separated, optimal dielectrics for specific applications can be used.
Embodiments of the present disclosure may be applicable to analog or digital electronic components in a vertical stack. Manufacturing processes may produce a smaller footprint, higher component density, higher yield, and lower HF interference.
Large packages are often difficult to solder; some pins may not make solder connections. Separating functional elements across cards with relatively balanced stacks for dielectric thickness may facilitate higher yielding interconnect operations due to lower warpage.
It is believed that the inventive concepts disclosed herein and many of their attendant advantages will be understood by the foregoing description of embodiments of the inventive concepts, and it will be apparent that various changes may be made in the form, construction, and arrangement of the components thereof without departing from the broad scope of the inventive concepts disclosed herein or without sacrificing all of their material advantages; and individual features from various embodiments may be combined to arrive at other embodiments. The forms herein before described being merely explanatory embodiments thereof, it is the intention of the following claims to encompass and include such changes. Furthermore, any of the features disclosed in relation to any of the individual embodiments may be incorporated into any other embodiment.
