Patent Application
20230335518
Light emitting diodes (LEDs) convert electrical energy into optical energy, and offer many benefits over other light sources, such as reduced size, improved durability, and increased efficiency. LEDs can be used as light sources in many display systems, such as televisions, computer monitors, laptop computers, tablets, smartphones, projection systems, and wearable electronic devices. Micro-LEDs (“μLEDs”) based on III-V semiconductors, such as alloys of AlN, GaN, InN, AlGaInP, other ternary and quaternary nitride, phosphide, and arsenide compositions, have begun to be developed for various display applications due to their small size (e.g., with a linear dimension less than 100 μm, less than 50 μm, less than 10 μm, or less than 5 μm), high packing density (and hence higher resolution), and high brightness. For example, micro-LEDs that emit light of different colors (e.g., red, green, and blue) can be used to form the sub-pixels of a display system, such as a television or a near-eye display system.
This disclosure relates generally to micro-light emitting diodes (micro-LEDs). More specifically, and without limitation, techniques disclosed herein relate to micro-LED devices including high-thermal conductivity dielectric materials (e.g., aluminum nitride) in the bonding layers and/or the electrical interconnect layers to improve the thermal performance of the micro-LED devices. Various inventive embodiments are described herein, including devices, systems, methods, structures, materials, processes, and the like.
According to certain embodiments, a micro-light emitting diode (micro-LED) device may include a backplane including drive circuits and a first bonding layer, and an array of micro-LEDs including an array of semiconductor mesa structures and a second bonding layer. The first bonding layer may include a first dielectric layer, and first metal interconnects electrically connected to the drive circuits. The second bonding layer may include a second dielectric layer, and second metal interconnects electrically connected to the array of semiconductor mesa structures. The first bonding layer is bonded to the second bonding layer. At least one of the first dielectric layer or the second dielectric layer includes aluminum nitride.
In some embodiments of the micro-LED device, the first dielectric layer may be bonded to the second dielectric layer, and the first metal interconnects may be bonded to the second metal interconnects. In some embodiments, both the first dielectric layer and the second dielectric layer include AlN. The array of micro-LEDs may include AlN in regions between semiconductor mesa structures of the array of semiconductor mesa structures. Each semiconductor mesa structure of the array of semiconductor mesa structures may include a p-type semiconductor layer, an active region configured to emit light, and an n-type semiconductor layer. Each micro-LED of the array of micro-LEDs may include a semiconductor mesa structure of the array of semiconductor mesa structures, a passivation layer on sidewalls of the semiconductor mesa structure, and a reflective metal layer on the passivation layer. The reflective metal layer may fill regions between semiconductor mesa structures of the array of semiconductor mesa structures. In some embodiments, the second metal interconnects include metal reflectors.
In some embodiments of the micro-LED device, the first bonding layer may also include a third dielectric layer that has a dielectric material different from a dielectric material of the first dielectric layer. The first dielectric layer or the third dielectric layer may include AlN. The first metal interconnects may be in the first dielectric layer and the third dielectric layer. In some embodiments, the second bonding layer may also include a fourth dielectric layer that has a dielectric material different from a dielectric material of the second dielectric layer. The second dielectric layer or the fourth dielectric layer may include AlN. The second metal interconnects may be in the second dielectric layer and the fourth dielectric layer.
In some embodiments, sidewalls of the first metal interconnects may physically contact a dielectric material of the first dielectric layer. In some embodiments, sidewalls of the second metal interconnects may physically contact a dielectric material of the second dielectric layer. In some embodiments, the first bonding layer may include a barrier layer between sidewalls of the first metal interconnects and a dielectric material of the first dielectric layer. In some embodiments, the second bonding layer may include a barrier layer between sidewalls of the second metal interconnects and a dielectric material of the second dielectric layer.
According to certain embodiments, a micro-LED device may include a backplane including drive circuits and a first bonding layer, and an array of micro-LEDs including an array of semiconductor mesa structures and a second bonding layer. The first bonding layer may include a first dielectric layer, and first metal interconnects that are at least partially in the first dielectric layer and electrically connected to the drive circuits. The second bonding layer may include a second dielectric layer, and second metal interconnects that are at least partially in the second dielectric layer and electrically connected to the array of semiconductor mesa structures.
The first bonding layer may be bonded to the second bonding layer. At least one of the first dielectric layer or the second dielectric layer may include a first dielectric material characterized by a thermal conductivity greater than 50 W/(m·K) at room temperature.
In some embodiments of the micro-LED device, the first dielectric layer may be bonded to the second dielectric layer, and the first metal interconnects may be bonded to the second metal interconnects. A thermal expansion coefficient (CTE) of the first dielectric material may be higher than a CTE of silicon oxide at room temperature, and a hardness of the first dielectric material may be higher than a hardness of silicon oxide at room temperature. The first dielectric material may include, for example, AIN. Sidewalls of the first metal interconnects may physically contact a dielectric material of the first dielectric layer. Sidewalls of the second metal interconnects may physically contact a dielectric material of the second dielectric layer.
This summary is neither intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in isolation to determine the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification of this disclosure, any or all drawings, and each claim. The foregoing, together with other features and examples, will be described in more detail below in the following specification, claims, and accompanying drawings.
Illustrative embodiments are described in detail below with reference to the following figures.
The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated may be employed without departing from the principles, or benefits touted, of this disclosure.
In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
This disclosure relates generally to micro-light emitting diodes (micro-LEDs). More specifically, and without limitation, techniques disclosed herein relate to micro-LED devices including high-thermal conductivity dielectric materials (e.g., aluminum nitride) in the bonding layers and/or the electrical interconnect layers to improve the thermal performance of the micro-LED devices. Various inventive embodiments are described herein, including devices, systems, methods, structures, materials, processes, and the like.
Augmented reality (AR) and virtual reality (VR) applications may use near-eye displays that include tiny monochrome light emitters, such as mini- or micro-LEDs. In light emitting diodes (LEDs), photons are generated through the recombination of electrons and holes within an active region (e.g., including one or more semiconductor layers that may form one or more quantum wells). The proportion of carriers (e.g., electrons or holes) injected into the active region of an LED among the carriers that pass through the LED is referred to as the carrier injection efficiency. The ratio between the number of emitted photons and the number of carriers injected into the active region is referred to as the internal quantum efficiency (IQE) of the LED. Light emitted in the active region may be extracted from the LED at a certain light extraction efficiency (LEE). The ratio between the number of emitted photons extracted from the LED and the number of electrons passing through the LED is referred to as the external quantum efficiency (EQE) of the LED, which describes how efficiently the LED converts injected carriers into photons that are extracted from the LED. The EQE may be a product of the carrier injection efficiency, the IQE, and the LEE.
The internal quantum efficiency of an LED depends on the relative rates of competitive radiative (light producing) recombination and non-radiative (lossy) recombination that occur in the active region of the LED. Non-radiative recombination processes in the active region include Shockley-Read-Hall (SRH) recombination at defect sites and electron-electron-hole (eeh) and/or electron-hole-hole (ehh) Auger recombination. The Auger recombination is a non-radiative process involving three carriers, which affects all sizes of LEDs. In micro-LEDs, because the lateral size of each micro-LED may be comparable to the minority carrier diffusion length, a larger proportion of the total active region may be within a distance less than the minority carrier diffusion length from the LED sidewall surfaces where the defect density and the defect-induced non-radiative recombination rate may be high due to the abrupt ending of the lattice structure, chemical contamination, and/or structural damages (e.g., due to dry etch). Therefore, a larger proportion of the injected carriers may diffuse to the regions near the sidewall surfaces, where the carriers may be subjected to a higher SRH recombination rate. This may cause the efficiency of the LED to decrease (in particular, at low current injection), cause the peak efficiency of the LED to decrease, and/or cause the peak efficiency operating current to increase. Increasing the injected current may cause the efficiencies of the micro-LEDs to drop due to the higher eeh or ehh Auger recombination rate at a higher current density, and may also cause spectral shift of the emitted light. As the physical sizes of LEDs are further reduced, efficiency losses due to surface recombination near the etched sidewall facets that include surface imperfections may become much more significant.
In addition, the performance of micro-LED may be very sensitive to temperature. For example, the electron and hole concentration, electron mobility, operation current and voltage, and energy bandgap may change with the junction temperature. Non-radiative recombination and leakage current may also increase at high operational current densities and high temperature. For example, Auger recombination has been shown to be a temperature-dependent source of non-radiative recombination and can contribute to efficiency droop at high-injection current conditions. SRH recombination from trap states is also temperature dependent. Therefore, the efficiencies of LEDs may decrease to cause brightness decay as the device heats up. The junction temperature change may also cause an energy bandgap decrease and thus a color displacement, which may affect the color quality of LED-based displays at high junction temperatures. If no effective heat-sinking is employed, there may be a temperature gradient within an LED array, which may cause different brightness decay and color shifting. In micro-LEDs that may have low efficiencies, a high percentage of the electrical power may be converted to heat to heat up the micro-LEDs. Thus, if no effective thermal control mechanism is employed, the performance of micro-LEDs may significantly deteriorate due to the increase of the operating temperature. Various structures and external cooling mechanisms can be used to reduce the operating temperature and alleviate the temperature-dependent performance droop, including modifying device architectures and using external cooling devices. However, due to the constraints in the energy budget and the form factor of near-eye displays, active thermal solution for local temperature control may not be feasible for micro-LEDs used in near-eye displays.
According to certain embodiments, passive thermal solutions may be used to maintain desired localized temperatures in micro-LED devices, where the low-thermal conductivity dielectric materials (e.g., SiO2, SiN, and Al2O3) commonly used in interconnect layers and/or bonding layers of existing micro-LEDs may be replaced by high-thermal conductivity dielectric materials, such as aluminum nitride (AlN), beryllium oxide (BeO), or boron nitride (BN). may have a large energy bandgap (and thus may be used as an insulator), and a high thermal conductivity due to, for example, small atomic mass, strong interatomic bonds, and simple crystal structure. The AlN dielectric material can help to efficiently and rapidly dissipate heat generated in the active regions of micro-LEDs into the backplane, and retain a uniform temperature distribution among the micro-LEDs in a micro-LED array. Therefore, the AlN layers may behave as efficient heat spreading layers between the micro-LED array and drive circuits on the backplane. Using AlN rather than SiO2 may also help to mitigate the CTE mismatch among different materials in the micro-LED device, such as the silicon substrate, semiconductor epitaxial layers, and dielectric materials. Furthermore, due to the combability in the relevant processes, replacing dielectric materials such as SiO2 with AlN may not negatively impact the downstream process flow.
In addition, the intrinsic stress inside an AlN layer can be tuned, such that desired wafer bowing (e.g., low or similar bowing) of the micro-LED wafer and the backplane wafer may be achieved, which may make the downstream processes, such as the wafer alignment and wafer-to-wafer hybrid bonding, easier to perform. Furthermore, AlN may have a higher hardness or stiffness than SiO2, and thus may have lower rounding and/or trenches after the planarization of the bonding layers. Therefore, the dielectric bonding area and bonding strength at the AlN-AlN bonding interface may be larger than those at the SiO2-SiO2 bonding interface. The surface roughness of AlN can be comparable to the surface roughness of SiO2, such as about a few angstroms, and thus the AlN-AlN bonding and the SiO2-SiO2 bonding may have comparable bonding quality. A barrier layer may not need to be used between the metal interconnects and the AlN material in the bonding layer to prevent the diffusion of metal atoms into the AlN material and the semiconductor material. Additionally, in some micro-LED wafers, such as a GaN-on-Si wafer, an AlN layer may often be grown on the silicon substrate as the seed layer (or buffer layer) during the epitaxy growth. In some embodiments, this AlN seed layer may be used as the bonding layer and metal bonding pads can be formed in this AlN seed layer, and thus a deposition process (e.g., a spluttering process) may not be needed to deposit the AlN dielectric layer for hybrid bonding, which may simplify the downstream process flow.
The micro-LEDs described herein may be used in conjunction with various technologies, such as an artificial reality system. An artificial reality system, such as a head-mounted display (HIVID) or heads-up display (HUD) system, generally includes a display configured to present artificial images that depict objects in a virtual environment. The display may present virtual objects or combine images of real objects with virtual objects, as in virtual reality (VR), augmented reality (AR), or mixed reality (MR) applications. For example, in an AR system, a user may view both displayed images of virtual objects (e.g., computer-generated images (CGIs)) and the surrounding environment by, for example, seeing through transparent display glasses or lenses (often referred to as optical see-through) or viewing displayed images of the surrounding environment captured by a camera (often referred to as video see-through). In some AR systems, the artificial images may be presented to users using an LED-based display subsystem.
As used herein, the term “light emitting diode (LED)” refers to a light source that includes at least an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting region (i.e., active region) between the n-type semiconductor layer and the p-type semiconductor layer. The light emitting region may include one or more semiconductor layers that form one or more heterostructures, such as quantum wells. In some embodiments, the light emitting region may include multiple semiconductor layers that form one or more multiple-quantum-wells (MQWs), each including multiple (e.g., about 2 to 6) quantum wells.
As used herein, the term “micro-LED” or “μLED” refers to an LED that has a chip where a linear dimension of the chip is less than about 200 μm, such as less than 100 μm, less than 50 μm, less than 20 μm, less than 10 μm, or smaller. For example, the linear dimension of a micro-LED may be as small as 6 μm, 5 μm, 4 μm, 2 μm, or smaller. Some micro-LEDs may have a linear dimension (e.g., length or diameter) comparable to the minority carrier diffusion length. However, the disclosure herein is not limited to micro-LEDs, and may also be applied to mini-LEDs and large LEDs.
As used herein, the term “bonding” may refer to various methods for physically and/or electrically connecting two or more devices and/or wafers, such as adhesive bonding, metal-to- metal bonding, metal oxide bonding, wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding, soldering, under-bump metallization, and the like. For example, adhesive bonding may use a curable adhesive (e.g., an epoxy) to physically bond two or more devices and/or wafers through adhesion. Metal-to-metal bonding may include, for example, wire bonding or flip chip bonding using soldering interfaces (e.g., pads or balls), conductive adhesive, or welded joints between metals. Metal oxide bonding may form a metal and oxide pattern on each surface, bond the oxide sections together, and then bond the metal sections together to create a conductive path. Wafer-to-wafer bonding may bond two wafers (e.g., silicon wafers or other semiconductor wafers) without any intermediate layers and is based on chemical bonds between the surfaces of the two wafers. Wafer-to-wafer bonding may include wafer cleaning and other preprocessing, aligning and pre-bonding at room temperature, and annealing at elevated temperatures, such as about 250° C. or higher. Die-to-wafer bonding may use bumps on one wafer to align features of a pre-formed chip with drivers of a wafer. Hybrid bonding may include, for example, wafer cleaning, high-precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric materials within the wafers at room temperature, and metal bonding of the contacts by annealing at, for example, 250-300° C. or higher. As used herein, the term “bump” may refer generically to a metal interconnect used or formed during bonding.
In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of examples of the disclosure. However, it will be apparent that various examples may be practiced without these specific details. For example, devices, systems, structures, assemblies, methods, and other components may be shown as components in block diagram form in order not to obscure the examples in unnecessary detail. In other instances, well-known devices, processes, systems, structures, and techniques may be shown without necessary detail in order to avoid obscuring the examples. The figures and description are not intended to be restrictive. The terms and expressions that have been employed in this disclosure are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding any equivalents of the features shown and described or portions thereof. The word “example” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
Near-eye display 120 may be a head-mounted display that presents content to a user. Examples of content presented by near-eye display 120 include one or more of images, videos, audio, or any combination thereof. In some embodiments, audio may be presented via an external device (e.g., speakers and/or headphones) that receives audio information from near-eye display 120, console 110, or both, and presents audio data based on the audio information. Near-eye display 120 may include one or more rigid bodies, which may be rigidly or non-rigidly coupled to each other. A rigid coupling between rigid bodies may cause the coupled rigid bodies to act as a single rigid entity. A non-rigid coupling between rigid bodies may allow the rigid bodies to move relative to each other. In various embodiments, near-eye display 120 may be implemented in any suitable form-factor, including a pair of glasses. Some embodiments of near-eye display 120 are further described below with respect to
In various embodiments, near-eye display 120 may include one or more of display electronics 122, display optics 124, and an eye-tracking unit 130. In some embodiments, near- eye display 120 may also include one or more locators 126, one or more position sensors 128, and an inertial measurement unit (IMU) 132. Near-eye display 120 may omit any of eye-tracking unit 130, locators 126, position sensors 128, and IMU 132, or include additional elements in various embodiments. Additionally, in some embodiments, near-eye display 120 may include elements combining the function of various elements described in conjunction with
Display electronics 122 may display or facilitate the display of images to the user according to data received from, for example, console 110. In various embodiments, display electronics 122 may include one or more display panels, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an inorganic light emitting diode (ILED) display, a micro light emitting diode (μLED) display, an active-matrix OLED display (AMOLED), a transparent OLED display (TOLED), or some other display. For example, in one implementation of near-eye display 120, display electronics 122 may include a front TOLED panel, a rear display panel, and an optical component (e.g., an attenuator, polarizer, or diffractive or spectral film) between the front and rear display panels. Display electronics 122 may include pixels to emit light of a predominant color such as red, green, blue, white, or yellow. In some implementations, display electronics 122 may display a three-dimensional (3D) image through stereoscopic effects produced by two-dimensional panels to create a subjective perception of image depth. For example, display electronics 122 may include a left display and a right display positioned in front of a user's left eye and right eye, respectively. The left and right displays may present copies of an image shifted horizontally relative to each other to create a stereoscopic effect (i.e., a perception of image depth by a user viewing the image).
In certain embodiments, display optics 124 may display image content optically (e.g., using optical waveguides and couplers) or magnify image light received from display electronics 122, correct optical errors associated with the image light, and present the corrected image light to a user of near-eye display 120. In various embodiments, display optics 124 may include one or more optical elements, such as, for example, a substrate, optical waveguides, an aperture, a Fresnel lens, a convex lens, a concave lens, a filter, input/output couplers, or any other suitable optical elements that may affect image light emitted from display electronics 122. Display optics 124 may include a combination of different optical elements as well as mechanical couplings to maintain relative spacing and orientation of the optical elements in the combination. One or more optical elements in display optics 124 may have an optical coating, such as an anti-reflective coating, a reflective coating, a filtering coating, or a combination of different optical coatings.
Magnification of the image light by display optics 124 may allow display electronics 122 to be physically smaller, weigh less, and consume less power than larger displays. Additionally, magnification may increase a field of view of the displayed content. The amount of magnification of image light by display optics 124 may be changed by adjusting, adding, or removing optical elements from display optics 124. In some embodiments, display optics 124 may project displayed images to one or more image planes that may be further away from the user's eyes than near-eye display 120.
Display optics 124 may also be designed to correct one or more types of optical errors, such as two-dimensional optical errors, three-dimensional optical errors, or any combination thereof. Two-dimensional errors may include optical aberrations that occur in two dimensions. Example types of two-dimensional errors may include barrel distortion, pincushion distortion, longitudinal chromatic aberration, and transverse chromatic aberration. Three-dimensional errors may include optical errors that occur in three dimensions. Example types of three-dimensional errors may include spherical aberration, comatic aberration, field curvature, and astigmatism.
Locators 126 may be objects located in specific positions on near-eye display 120 relative to one another and relative to a reference point on near-eye display 120. In some implementations, console 110 may identify locators 126 in images captured by external imaging device 150 to determine the artificial reality headset's position, orientation, or both. A locator 126 may be an LED, a corner cube reflector, a reflective marker, a type of light source that contrasts with an environment in which near-eye display 120 operates, or any combination thereof. In embodiments where locators 126 are active components (e.g., LEDs or other types of light emitting devices), locators 126 may emit light in the visible band (e.g., about 380 nm to 750 nm), in the infrared (IR) band (e.g., about 750 nm to 1 mm), in the ultraviolet band (e.g., about 10 nm to about 380 nm), in another portion of the electromagnetic spectrum, or in any combination of portions of the electromagnetic spectrum.
External imaging device 150 may include one or more cameras, one or more video cameras, any other device capable of capturing images including one or more of locators 126, or any combination thereof. Additionally, external imaging device 150 may include one or more filters (e.g., to increase signal to noise ratio). External imaging device 150 may be configured to detect light emitted or reflected from locators 126 in a field of view of external imaging device 150. In embodiments where locators 126 include passive elements (e.g., retroreflectors), external imaging device 150 may include a light source that illuminates some or all of locators 126, which may retro-reflect the light to the light source in external imaging device 150. Slow calibration data may be communicated from external imaging device 150 to console 110, and external imaging device 150 may receive one or more calibration parameters from console 110 to adjust one or more imaging parameters (e.g., focal length, focus, frame rate, sensor temperature, shutter speed, aperture, etc.).
Position sensors 128 may generate one or more measurement signals in response to motion of near-eye display 120. Examples of position sensors 128 may include accelerometers, gyroscopes, magnetometers, other motion-detecting or error-correcting sensors, or any combination thereof. For example, in some embodiments, position sensors 128 may include multiple accelerometers to measure translational motion (e.g., forward/back, up/down, or left/right) and multiple gyroscopes to measure rotational motion (e.g., pitch, yaw, or roll). In some embodiments, various position sensors may be oriented orthogonally to each other.
IMU 132 may be an electronic device that generates fast calibration data based on measurement signals received from one or more of position sensors 128. Position sensors 128 may be located external to IMU 132, internal to IMU 132, or any combination thereof. Based on the one or more measurement signals from one or more position sensors 128, IMU 132 may generate fast calibration data indicating an estimated position of near-eye display 120 relative to an initial position of near-eye display 120. For example, IMU 132 may integrate measurement signals received from accelerometers over time to estimate a velocity vector and integrate the velocity vector over time to determine an estimated position of a reference point on near-eye display 120. Alternatively, IMU 132 may provide the sampled measurement signals to console 110, which may determine the fast calibration data. While the reference point may generally be defined as a point in space, in various embodiments, the reference point may also be defined as a point within near-eye display 120 (e.g., a center of IMU 132).
Eye-tracking unit 130 may include one or more eye-tracking systems. Eye tracking may refer to determining an eye's position, including orientation and location of the eye, relative to near-eye display 120. An eye-tracking system may include an imaging system to image one or more eyes and may optionally include a light emitter, which may generate light that is directed to an eye such that light reflected by the eye may be captured by the imaging system. For example, eye-tracking unit 130 may include a non-coherent or coherent light source (e.g., a laser diode) emitting light in the visible spectrum or infrared spectrum, and a camera capturing the light reflected by the user's eye. As another example, eye-tracking unit 130 may capture reflected radio waves emitted by a miniature radar unit. Eye-tracking unit 130 may use low-power light emitters that emit light at frequencies and intensities that would not injure the eye or cause physical discomfort. Eye-tracking unit 130 may be arranged to increase contrast in images of an eye captured by eye-tracking unit 130 while reducing the overall power consumed by eye-tracking unit 130 (e.g., reducing power consumed by a light emitter and an imaging system included in eye-tracking unit 130). For example, in some implementations, eye-tracking unit 130 may consume less than 100 milliwatts of power.
Near-eye display 120 may use the orientation of the eye to, e.g., determine an inter-pupillary distance (IPD) of the user, determine gaze direction, introduce depth cues (e.g., blur image outside of the user's main line of sight), collect heuristics on the user interaction in the VR media (e.g., time spent on any particular subject, object, or frame as a function of exposed stimuli), some other functions that are based in part on the orientation of at least one of the user's eyes, or any combination thereof. Because the orientation may be determined for both eyes of the user, eye-tracking unit 130 may be able to determine where the user is looking. For example, determining a direction of a user's gaze may include determining a point of convergence based on the determined orientations of the user's left and right eyes. A point of convergence may be the point where the two foveal axes of the user's eyes intersect. The direction of the user's gaze may be the direction of a line passing through the point of convergence and the mid-point between the pupils of the user's eyes.
Input/output interface 140 may be a device that allows a user to send action requests to console 110. An action request may be a request to perform a particular action. For example, an action request may be to start or to end an application or to perform a particular action within the application. Input/output interface 140 may include one or more input devices. Example input devices may include a keyboard, a mouse, a game controller, a glove, a button, a touch screen, or any other suitable device for receiving action requests and communicating the received action requests to console 110. An action request received by the input/output interface 140 may be communicated to console 110, which may perform an action corresponding to the requested action. In some embodiments, input/output interface 140 may provide haptic feedback to the user in accordance with instructions received from console 110. For example, input/output interface 140 may provide haptic feedback when an action request is received, or when console 110 has performed a requested action and communicates instructions to input/output interface 140. In some embodiments, external imaging device 150 may be used to track input/output interface 140, such as tracking the location or position of a controller (which may include, for example, an IR light source) or a hand of the user to determine the motion of the user. In some embodiments, near-eye display 120 may include one or more imaging devices to track input/output interface 140, such as tracking the location or position of a controller or a hand of the user to determine the motion of the user.
Console 110 may provide content to near-eye display 120 for presentation to the user in accordance with information received from one or more of external imaging device 150, near-eye display 120, and input/output interface 140. In the example shown in
In some embodiments, console 110 may include a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor. The processor may include multiple processing units executing instructions in parallel. The non-transitory computer-readable storage medium may be any memory, such as a hard disk drive, a removable memory, or a solid-state drive (e.g., flash memory or dynamic random access memory (DRAM)). In various embodiments, the modules of console 110 described in conjunction with
Application store 112 may store one or more applications for execution by console 110. An application may include a group of instructions that, when executed by a processor, generates content for presentation to the user. Content generated by an application may be in response to inputs received from the user via movement of the user's eyes or inputs received from the input/output interface 140. Examples of the applications may include gaming applications, conferencing applications, video playback application, or other suitable applications.
Headset tracking module 114 may track movements of near-eye display 120 using slow calibration information from external imaging device 150. For example, headset tracking module 114 may determine positions of a reference point of near-eye display 120 using observed locators from the slow calibration information and a model of near-eye display 120. Headset tracking module 114 may also determine positions of a reference point of near-eye display 120 using position information from the fast calibration information. Additionally, in some embodiments, headset tracking module 114 may use portions of the fast calibration information, the slow calibration information, or any combination thereof, to predict a future location of near-eye display 120. Headset tracking module 114 may provide the estimated or predicted future position of near-eye display 120 to artificial reality engine 116.
Artificial reality engine 116 may execute applications within artificial reality system environment 100 and receive position information of near-eye display 120, acceleration information of near-eye display 120, velocity information of near-eye display 120, predicted future positions of near-eye display 120, or any combination thereof from headset tracking module 114. Artificial reality engine 116 may also receive estimated eye position and orientation information from eye-tracking module 118. Based on the received information, artificial reality engine 116 may determine content to provide to near-eye display 120 for presentation to the user. For example, if the received information indicates that the user has looked to the left, artificial reality engine 116 may generate content for near-eye display 120 that mirrors the user's eye movement in a virtual environment. Additionally, artificial reality engine 116 may perform an action within an application executing on console 110 in response to an action request received from input/output interface 140, and provide feedback to the user indicating that the action has been performed. The feedback may be visual or audible feedback via near-eye display 120 or haptic feedback via input/output interface 140.
Eye-tracking module 118 may receive eye-tracking data from eye-tracking unit 130 and determine the position of the user's eye based on the eye tracking data. The position of the eye may include an eye's orientation, location, or both relative to near-eye display 120 or any element thereof. Because the eye's axes of rotation change as a function of the eye's location in its socket, determining the eye's location in its socket may allow eye-tracking module 118 to determine the eye's orientation more accurately.
HMD device 200 may present to a user media including virtual and/or augmented views of a physical, real-world environment with computer-generated elements. Examples of the media presented by HMD device 200 may include images (e.g., two-dimensional (2D) or three-dimensional (3D) images), videos (e.g., 2D or 3D videos), audio, or any combination thereof. The images and videos may be presented to each eye of the user by one or more display assemblies (not shown in
In some implementations, HMD device 200 may include various sensors (not shown), such as depth sensors, motion sensors, position sensors, and eye tracking sensors. Some of these sensors may use a structured light pattern for sensing. In some implementations, HMD device 200 may include an input/output interface for communicating with a console. In some implementations, HMD device 200 may include a virtual reality engine (not shown) that can execute applications within HMD device 200 and receive depth information, position information, acceleration information, velocity information, predicted future positions, or any combination thereof of HIVID device 200 from the various sensors. In some implementations, the information received by the virtual reality engine may be used for producing a signal (e.g., display instructions) to the one or more display assemblies. In some implementations, HMD device 200 may include locators (not shown, such as locators 126) located in fixed positions on body 220 relative to one another and relative to a reference point. Each of the locators may emit light that is detectable by an external imaging device.
Near-eye display 300 may further include various sensors 350a, 350b, 350c, 350d, and 350e on or within frame 305. In some embodiments, sensors 350a-350e may include one or more depth sensors, motion sensors, position sensors, inertial sensors, or ambient light sensors. In some embodiments, sensors 350a-350e may include one or more image sensors configured to generate image data representing different fields of views in different directions. In some embodiments, sensors 350a-350e may be used as input devices to control or influence the displayed content of near-eye display 300, and/or to provide an interactive VR/AR/MR experience to a user of near-eye display 300. In some embodiments, sensors 350a-350e may also be used for stereoscopic imaging.
In some embodiments, near-eye display 300 may further include one or more illuminators 330 to project light into the physical environment. The projected light may be associated with different frequency bands (e.g., visible light, infra-red light, ultra-violet light, etc.), and may serve various purposes. For example, illuminator(s) 330 may project light in a dark environment (or in an environment with low intensity of infra-red light, ultra-violet light, etc.) to assist sensors 350a-350e in capturing images of different objects within the dark environment. In some embodiments, illuminator(s) 330 may be used to project certain light patterns onto the objects within the environment. In some embodiments, illuminator(s) 330 may be used as locators, such as locators 126 described above with respect to
In some embodiments, near-eye display 300 may also include a high-resolution camera 340. Camera 340 may capture images of the physical environment in the field of view. The captured images may be processed, for example, by a virtual reality engine (e.g., artificial reality engine 116 of
Combiner 415 may include an input coupler 430 for coupling light from projector 410 into a substrate 420 of combiner 415. Combiner 415 may transmit at least 50% of light in a first wavelength range and reflect at least 25% of light in a second wavelength range. For example, the first wavelength range may be visible light from about 400 nm to about 650 nm, and the second wavelength range may be in the infrared band, for example, from about 800 nm to about 1000 nm. Input coupler 430 may include a volume holographic grating, a diffractive optical element (DOE) (e.g., a surface-relief grating), a slanted surface of substrate 420, or a refractive coupler (e.g., a wedge or a prism). For example, input coupler 430 may include a reflective volume Bragg grating or a transmissive volume Bragg grating. Input coupler 430 may have a coupling efficiency of greater than 30%, 50%, 75%, 90%, or higher for visible light. Light coupled into substrate 420 may propagate within substrate 420 through, for example, total internal reflection (TIR). Substrate 420 may be in the form of a lens of a pair of eyeglasses. Substrate 420 may have a flat or a curved surface, and may include one or more types of dielectric materials, such as glass, quartz, plastic, polymer, poly(methyl methacrylate) (PMMA), crystal, or ceramic. A thickness of the substrate may range from, for example, less than about 1 mm to about 10 mm or more. Substrate 420 may be transparent to visible light.
Substrate 420 may include or may be coupled to a plurality of output couplers 440, each configured to extract at least a portion of the light guided by and propagating within substrate 420 from substrate 420, and direct extracted light 460 to an eyebox 495 where an eye 490 of the user of augmented reality system 400 may be located when augmented reality system 400 is in use. The plurality of output couplers 440 may replicate the exit pupil to increase the size of eyebox 495 such that the displayed image is visible in a larger area. As input coupler 430, output couplers 440 may include grating couplers (e.g., volume holographic gratings or surface-relief gratings), other diffraction optical elements (DOEs), prisms, etc. For example, output couplers 440 may include reflective volume Bragg gratings or transmissive volume Bragg gratings. Output couplers 440 may have different coupling (e.g., diffraction) efficiencies at different locations. Substrate 420 may also allow light 450 from the environment in front of combiner 415 to pass through with little or no loss. Output couplers 440 may also allow light 450 to pass through with little loss. For example, in some implementations, output couplers 440 may have a very low diffraction efficiency for light 450 such that light 450 may be refracted or otherwise pass through output couplers 440 with little loss, and thus may have a higher intensity than extracted light 460. In some implementations, output couplers 440 may have a high diffraction efficiency for light 450 and may diffract light 450 in certain desired directions (i.e., diffraction angles) with little loss. As a result, the user may be able to view combined images of the environment in front of combiner 415 and images of virtual objects projected by projector 410.
Before reaching waveguide display 530, the light emitted by light source 510 may be conditioned by projection optics 520, which may include a lens array. Projection optics 520 may collimate or focus the light emitted by light source 510 to waveguide display 530, which may include a coupler 532 for coupling the light emitted by light source 510 into waveguide display 530. The light coupled into waveguide display 530 may propagate within waveguide display 530 through, for example, total internal reflection as described above with respect to
Before reaching scanning mirror 570, the light emitted by light source 540 may be conditioned by various optical devices, such as collimating lenses or a freeform optical element 560. Freeform optical element 560 may include, for example, a multi-facet prism or another light folding element that may direct the light emitted by light source 540 towards scanning mirror 570, such as changing the propagation direction of the light emitted by light source 540 by, for example, about 90° or larger. In some embodiments, freeform optical element 560 may be rotatable to scan the light. Scanning mirror 570 and/or freeform optical element 560 may reflect and project the light emitted by light source 540 to waveguide display 580, which may include a coupler 582 for coupling the light emitted by light source 540 into waveguide display 580. The light coupled into waveguide display 580 may propagate within waveguide display 580 through, for example, total internal reflection as described above with respect to
Scanning mirror 570 may include a microelectromechanical system (MEMS) mirror or any other suitable mirrors. Scanning mirror 570 may rotate to scan in one or two dimensions. As scanning mirror 570 rotates, the light emitted by light source 540 may be directed to a different area of waveguide display 580 such that a full display image may be projected onto waveguide display 580 and directed to user's eye 590 by waveguide display 580 in each scanning cycle. For example, in embodiments where light source 540 includes light emitters for all pixels in one or more rows or columns, scanning mirror 570 may be rotated in the column or row direction (e.g., x or y direction) to scan an image. In embodiments where light source 540 includes light emitters for some but not all pixels in one or more rows or columns, scanning mirror 570 may be rotated in both the row and column directions (e.g., both x and y directions) to project a display image (e.g., using a raster-type scanning pattern).
NED device 550 may operate in predefined display periods. A display period (e.g., display cycle) may refer to a duration of time in which a full image is scanned or projected. For example, a display period may be a reciprocal of the desired frame rate. In NED device 550 that includes scanning mirror 570, the display period may also be referred to as a scanning period or scanning cycle. The light generation by light source 540 may be synchronized with the rotation of scanning mirror 570. For example, each scanning cycle may include multiple scanning steps, where light source 540 may generate a different light pattern in each respective scanning step.
In each scanning cycle, as scanning mirror 570 rotates, a display image may be projected onto waveguide display 580 and user's eye 590. The actual color value and light intensity (e.g., brightness) of a given pixel location of the display image may be an average of the light beams of the three colors (e.g., red, green, and blue) illuminating the pixel location during the scanning period. After completing a scanning period, scanning mirror 570 may revert back to the initial position to project light for the first few rows of the next display image or may rotate in a reverse direction or scan pattern to project light for the next display image, where a new set of driving signals may be fed to light source 540. The same process may be repeated as scanning mirror 570 rotates in each scanning cycle. As such, different images may be projected to user's eye 590 in different scanning cycles.
As described above, light source 642 may include a plurality of light emitters arranged in an array or a matrix. Each light emitter may emit monochromatic light, such as red light, blue light, green light, infra-red light, and the like. While RGB colors are often discussed in this disclosure, embodiments described herein are not limited to using red, green, and blue as primary colors. Other colors can also be used as the primary colors of near-eye display system 600. In some embodiments, a display panel in accordance with an embodiment may use more than three primary colors. Each pixel in light source 642 may include three subpixels that include a red micro-LED, a green micro-LED, and a blue micro-LED. A semiconductor LED generally includes an active light emitting layer within multiple layers of semiconductor materials. The multiple layers of semiconductor materials may include different compound materials or a same base material with different dopants and/or different doping densities. For example, the multiple layers of semiconductor materials may include an n-type material layer, an active region that may include hetero-structures (e.g., one or more quantum wells), and a p-type material layer. The multiple layers of semiconductor materials may be grown on a surface of a substrate having a certain orientation. In some embodiments, to increase light extraction efficiency, a mesa that includes at least some of the layers of semiconductor materials may be formed.
Controller 620 may control the image rendering operations of image source assembly 610, such as the operations of light source 642 and/or projector 650. For example, controller 620 may determine instructions for image source assembly 610 to render one or more display images. The instructions may include display instructions and scanning instructions. In some embodiments, the display instructions may include an image file (e.g., a bitmap file). The display instructions may be received from, for example, a console, such as console 110 described above with respect to
In some embodiments, controller 620 may be a graphics processing unit (GPU) of a display device. In other embodiments, controller 620 may be other kinds of processors. The operations performed by controller 620 may include taking content for display and dividing the content into discrete sections. Controller 620 may provide to light source 642 scanning instructions that include an address corresponding to an individual source element of light source 642 and/or an electrical bias applied to the individual source element. Controller 620 may instruct light source 642 to sequentially present the discrete sections using light emitters corresponding to one or more rows of pixels in an image ultimately displayed to the user. Controller 620 may also instruct projector 650 to perform different adjustments of the light. For example, controller 620 may control projector 650 to scan the discrete sections to different areas of a coupling element of the waveguide display (e.g., waveguide display 580) as described above with respect to
Image processor 630 may be a general-purpose processor and/or one or more application-specific circuits that are dedicated to performing the features described herein. In one embodiment, a general-purpose processor may be coupled to a memory to execute software instructions that cause the processor to perform certain processes described herein. In another embodiment, image processor 630 may be one or more circuits that are dedicated to performing certain features. While image processor 630 in
In the example shown in
Projector 650 may perform a set of optical functions, such as focusing, combining, conditioning, or scanning the image light generated by light source 642. In some embodiments, projector 650 may include a combining assembly, a light conditioning assembly, or a scanning mirror assembly. Projector 650 may include one or more optical components that optically adjust and potentially re-direct the light from light source 642. One example of the adjustment of light may include conditioning the light, such as expanding, collimating, correcting for one or more optical errors (e.g., field curvature, chromatic aberration, etc.), some other adjustments of the light, or any combination thereof. The optical components of projector 650 may include, for example, lenses, mirrors, apertures, gratings, or any combination thereof.
Projector 650 may redirect image light via its one or more reflective and/or refractive portions so that the image light is projected at certain orientations toward the waveguide display. The location where the image light is redirected toward the waveguide display may depend on specific orientations of the one or more reflective and/or refractive portions. In some embodiments, projector 650 includes a single scanning mirror that scans in at least two dimensions. In other embodiments, projector 650 may include a plurality of scanning mirrors that each scan in directions orthogonal to each other. Projector 650 may perform a raster scan (horizontally or vertically), a bi-resonant scan, or any combination thereof In some embodiments, projector 650 may perform a controlled vibration along the horizontal and/or vertical directions with a specific frequency of oscillation to scan along two dimensions and generate a two-dimensional projected image of the media presented to user's eyes. In other embodiments, projector 650 may include a lens or prism that may serve similar or the same function as one or more scanning mirrors. In some embodiments, image source assembly 610 may not include a projector, where the light emitted by light source 642 may be directly incident on the waveguide display.
The overall efficiency of a photonic integrated circuit or a waveguide-based display (e.g., in augmented reality system 400 or NED device 500 or 550) may be a product of the efficiency of individual components and may also depend on how the components are connected. For example, the overall efficiency ηtot of the waveguide-based display in augmented reality system 400 may depend on the light emitting efficiency of image source 412, the light coupling efficiency from image source 412 into combiner 415 by projector optics 414 and input coupler 430, and the output coupling efficiency of output coupler 440, and thus may be determined as:
ηtot=ηEQE×ηin×ηout, (1)
where ηEQE is the external quantum efficiency of image source 412, ηin is the in-coupling efficiency of light from image source 412 into the waveguide (e.g., substrate 420), and ηout is the outcoupling efficiency of light from the waveguide towards the user's eye by output coupler 440. Thus, the overall efficiency ηtot of the waveguide-based display can be improved by improving one or more of ηEQE, ηin, and ηout.
The optical coupler (e.g., input coupler 430 or coupler 532) that couples the emitted light from a light source to a waveguide may include, for example, a grating, a lens, a micro-lens, and/or a prism. In some embodiments, light from a small light source (e.g., a micro-LED) can be directly (e.g., end-to-end) coupled from the light source to a waveguide, without using an optical coupler. In some embodiments, the optical coupler (e.g., a lens or a parabolic-shaped reflector) may be manufactured on the light source.
The light sources, image sources, or other displays described above may include one or more LEDs. For example, each pixel in a display may include three subpixels that include a red micro-LED, a green micro-LED, and a blue micro-LED. A semiconductor light emitting diode generally includes an active light emitting layer within multiple layers of semiconductor materials. The multiple layers of semiconductor materials may include different compound materials or a same base material with different dopants and/or different doping densities. For example, the multiple layers of semiconductor materials may generally include an n-type material layer, an active layer that may include hetero-structures (e.g., one or more quantum wells), and a p-type material layer. The multiple layers of semiconductor materials may be grown on a surface of a substrate having a certain orientation.
Photons can be generated in a semiconductor LED (e.g., a micro-LED) at a certain internal quantum efficiency through the recombination of electrons and holes within the active layer (e.g., including one or more semiconductor layers). The generated light may then be extracted from the LEDs. The ratio between the number of emitted photons extracted from the LED and the number of electrons passing through the LED is referred to as the external quantum efficiency, which describes how efficiently the LED converts injected electrons to photons that are extracted from the device. The external quantum efficiency may be proportional to the carrier injection efficiency, the internal quantum efficiency, and the light extraction efficiency. The carrier injection efficiency refers to the proportion of electrons passing through the device that are injected into the active region. The light extraction efficiency is the proportion of photons generated in the active region that escape from the device. For LEDs, and in particular, micro-LEDs with reduced physical dimensions, improving the internal and external quantum efficiency can be challenging. In some embodiments, to increase the light extraction efficiency of an LED, a mesa structure may be etched in semiconductor epitaxial layers, and light extraction structures (e.g., reflectors, lenses, and/or rough surfaces) may be formed on the mesa structure.
In the example shown in
In some embodiments, an electron-blocking layer (EBL) (not shown in
To make contact with semiconductor layer 720 (e.g., an n-GaN layer) and to more efficiently extract light emitted by active layer 730 from LED 700, the semiconductor material layers (including heavily-doped semiconductor layer 750, semiconductor layer 740, active layer 730, and semiconductor layer 720) may be etched to expose semiconductor layer 720 and to form a mesa structure that includes layers 720-760. The mesa structure may confine the carriers within the device. Etching the mesa structure may lead to the formation of mesa sidewalls 732 that may be orthogonal to the growth planes. A passivation layer 770 may be formed on mesa sidewalls 732 of the mesa structure. Passivation layer 770 may include an oxide layer, such as a SiO2 layer, and may act as a reflector to reflect emitted light out of LED 700. A contact layer 780, which may include a metal layer, such as Al, Au, Ni, Ti, or any combination thereof, may be formed on semiconductor layer 720 and may act as an electrode of LED 700. In addition, another contact layer 790, such as an Al/Ni/Au metal layer, may be formed on conductive layer 760 and may act as another electrode of LED 700.
When a voltage signal is applied to contact layers 780 and 790, electrons and holes may recombine in active layer 730, where the recombination of electrons and holes may cause photon emission. The wavelength and energy of the emitted photons may depend on the energy bandgap between the valence band and the conduction band in active layer 730. For example, InGaN active layers may emit green or blue light, AlGaN active layers may emit blue to ultraviolet light, while AlGaInP active layers may emit red, orange, yellow, or green light. The emitted photons may be reflected by passivation layer 770 and may exit LED 700 from the top (e.g., conductive layer 760 and contact layer 790) or bottom (e.g., substrate 710).
In some embodiments, LED 700 may include one or more other components, such as a lens, on the light emission surface, such as substrate 710, to focus or collimate the emitted light or couple the emitted light into a waveguide. In some embodiments, an LED may include a mesa of another shape, such as planar, conical, semi-parabolic, or parabolic, and a base area of the mesa may be circular, rectangular, hexagonal, or triangular. For example, the LED may include a mesa of a curved shape (e.g., paraboloid shape) and/or a non-curved shape (e.g., conic shape). The mesa may be truncated or non-truncated.
To make contact with semiconductor layer 725 (e.g., an n-type GaN layer) and to more efficiently extract light emitted by active layer 735 from LED 705, the semiconductor layers may be etched to expose semiconductor layer 725 and to form a mesa structure that includes layers 725-745. The mesa structure may confine carriers within the injection area of the device. Etching the mesa structure may lead to the formation of mesa side walls (also referred to herein as facets) that may be non-parallel with, or in some cases, orthogonal, to the growth planes associated with crystalline growth of layers 725-745.
As shown in
Electrical contact 765 and electrical contact 785 may be formed on semiconductor layer 745 and semiconductor layer 725, respectively, to act as electrodes. Electrical contact 765 and electrical contact 785 may each include a conductive material, such as Al, Au, Pt, Ag, Ni, Ti, Cu, or any combination thereof (e.g., Ag/Pt/Au or Al/Ni/Au), and may act as the electrodes of LED 705. In the example shown in
When a voltage signal is applied across electrical contacts 765 and 785, electrons and holes may recombine in active layer 735. The recombination of electrons and holes may cause photon emission, thus producing light. The wavelength and energy of the emitted photons may depend on the energy bandgap between the valence band and the conduction band in active layer 735. For example, InGaN active layers may emit green or blue light, while AlGaInP active layers may emit red, orange, yellow, or green light. The emitted photons may propagate in many different directions, and may be reflected by the mesa reflector and/or the back reflector and may exit LED 705, for example, from the bottom side (e.g., substrate 715) shown in
When the mesa structure is formed (e.g., etched), the facets of the mesa structure, such as mesa sidewalls 732, may have high defect densities due to the abrupt ending of the lattice structure, chemical contamination, and/or structural damages (e.g., due to dry etch). For example, in plasma etching, high-energy ions may be used to bombard the exposed surfaces of semiconductor layers. Due to the bombardment by high-energy particles, the surfaces created by the etching may be highly damaged, where the damages may include alterations to the crystal structure or other modifications to the surfaces, such as dangling-bonds, surface oxides, surfaces modified by plasma atoms, lattice dislocations, vacancies, interstitial defects, and substitutional defects. The damages may extend into the interior of the mesa structure, such as about 50 nm to about 500 nm below the new surfaces formed by the etching. Therefore, the active region in proximity to the exposed sidewalls may have a higher density of defects, such as dislocations, dangling bonds, pores, grain boundaries, vacancies, inclusion of precipitates, and the like. The defects may introduce energy states having deep or shallow energy levels in the bandgap that otherwise would not exist within the bandgap of the semiconductor material. Carriers may be trapped by these energy states until they recombine non-radiatively. Thus, these imperfections may become the recombination centers where electrons and holes may be confined until they combine non-radiatively.Therefore, the active region in proximity to the exposed sidewalls may have a higher rate of SRH recombination, thereby reducing the efficiency of the resulting LED.
A wafer 803 may include a base layer 809 having passive or active integrated circuits (e.g., drive circuits 811) fabricated thereon. Base layer 809 may include, for example, a silicon wafer. Drive circuits 811 may be used to control the operations of LEDs 807. For example, the drive circuit for each LED 807 may include a 2T1C pixel structure that has two transistors and one capacitor. Wafer 803 may also include a bonding layer 813. Bonding layer 813 may include various materials, such as a metal, an oxide, a dielectric, CuSn, AuTi, and the like. In some embodiments, a patterned layer 815 may be formed on a surface of bonding layer 813, where patterned layer 815 may include a metallic grid made of a conductive material, such as Cu, Ag, Au, Al, or the like.
LED array 801 may be bonded to wafer 803 via bonding layer 813 or patterned layer 815. For example, patterned layer 815 may include metal pads or bumps made of various materials, such as CuSn, AuSn, or nanoporous Au, that may be used to align LEDs 807 of LED array 801 with corresponding drive circuits 811 on wafer 803. In one example, LED array 801 may be brought toward wafer 803 until LEDs 807 come into contact with respective metal pads or bumps corresponding to drive circuits 811. Some or all of LEDs 807 may be aligned with drive circuits 811, and may then be bonded to wafer 803 via patterned layer 815 by various bonding techniques, such as metal-to-metal bonding. After LEDs 807 have been bonded to wafer 803, carrier substrate 805 may be removed from LEDs 807.
In some embodiments, first wafer 802 may also include a bonding layer. Bonding layer 812 may include various materials, such as a metal, an oxide, a dielectric, CuSn, AuTi, or the like. In one example, bonding layer 812 may include p-contacts and/or n-contacts (not shown). In some embodiments, other layers may also be included on first wafer 802, such as a buffer layer between substrate 804 and first semiconductor layer 806. The buffer layer may include various materials, such as polycrystalline GaN or AlN. In some embodiments, a contact layer may be between second semiconductor layer 810 and bonding layer 812. The contact layer may include any suitable material for providing an electrical contact to second semiconductor layer 810 and/or first semiconductor layer 806.
First wafer 802 may be bonded to wafer 803 that includes drive circuits 811 and bonding layer 813 as described above, via bonding layer 813 and/or bonding layer 812. Bonding layer 812 and bonding layer 813 may be made of the same material or different materials. Bonding layer 813 and bonding layer 812 may be substantially flat. First wafer 802 may be bonded to wafer 803 by various methods, such as metal-to-metal bonding, eutectic bonding, metal oxide bonding, anodic bonding, thermo-compression bonding, ultraviolet (UV) bonding, and/or fusion bonding.
As shown in
In some embodiments where the two bonded wafers include materials having different coefficients of thermal expansion (CTEs), the dielectric materials bonded at room temperature may help to reduce or prevent misalignment of the contact pads caused by the different thermal expansions. In some embodiments, to further reduce or avoid the misalignment of the contact pads at a high temperature during annealing, trenches may be formed between micro-LEDs, between groups of micro-LEDs, through part or all of the substrate, or the like, before bonding.
After the micro-LEDs are bonded to the drive circuits, the substrate on which the micro-LEDs are fabricated may be thinned or removed, and various secondary optical components may be fabricated on the light emitting surfaces of the micro-LEDs to, for example, extract, collimate, and redirect the light emitted from the active regions of the micro-LEDs. In one example, micro-lenses may be formed on the micro-LEDs, where each micro-lens may correspond to a respective micro-LED and may help to improve the light extraction efficiency and collimate the light emitted by the micro-LED. In some embodiments, the secondary optical components may be fabricated in the substrate or the n-type layer of the micro-LEDs. In some embodiments, the secondary optical components may be fabricated in a dielectric layer deposited on the n-type side of the micro-LEDs. Examples of the secondary optical components may include a lens, a grating, an antireflection (AR) coating, a prism, a photonic crystal, or the like.
The substrate (not shown) of the LED chip or wafer may be thinned or may be removed to expose the n-type layer 1050 of micro-LEDs 1070. Various secondary optical components, such as a spherical micro-lens 1082, a grating 1084, a micro-lens 1086, an antireflection layer 1088, and the like, may be formed in or on top of n-type layer 1050. For example, spherical micro-lens arrays may be etched in the semiconductor materials of micro-LEDs 1070 using a gray-scale mask and a photoresist with a linear response to exposure light, or using an etch mask formed by thermal reflowing of a patterned photoresist layer. The secondary optical components may also be etched in a dielectric layer deposited on n-type layer 1050 using similar photolithographic techniques or other techniques. For example, micro-lens arrays may be formed in a polymer layer through thermal reflowing of the polymer layer that is patterned using a binary mask. The micro-lens arrays in the polymer layer may be used as the secondary optical components or may be used as the etch mask for transferring the profiles of the micro-lens arrays into a dielectric layer or a semiconductor layer. The dielectric layer may include, for example, SiCN, SiO2, SiN, Al2O3, HfO2, ZrO2, Ta2O5, or the like. In some embodiments, a micro-LED 1070 may have multiple corresponding secondary optical components, such as a micro-lens and an anti-reflection coating, a micro-lens etched in the semiconductor material and a micro-lens etched in a dielectric material layer, a micro-lens and a grating, a spherical lens and an aspherical lens, and the like. Three different secondary optical components are illustrated in
In some embodiments, a buffer layer (e.g., an AlN layer) may be formed on substrate 1110 to improve the lattice matching between the growth substrate and the epitaxial layers, thereby reducing stress and defects in the epitaxial layers. The epitaxial layers may include an n-type semiconductor layer 1120 (e.g., an n-doped GaN, AlInP, or AlGaInP layer), an active region 1130, and a p-type semiconductor layer 1140 (e.g., a p-doped GaN, AlInP, or AlGaInP layer). Active region 1130 may include multiple quantum wells or an MQW formed by thin quantum well layers (e.g., InGaN layers or GaInP layers) sandwiched by barrier layers (e.g., GaN layers, AlInP layers, or AlGaInP layers) as described above. The epitaxial layers may be grown layer-by-layer on substrate 1110 or the buffer layer using techniques such as VPE, LPE, MBE, or MOCVD. In some embodiments, n-type semiconductor layer 1120 may be thicker than p-type semiconductor layer 1140.
The top surfaces of semiconductor mesa structures 1102, reflective metal layer 1150, and/or dielectric material 1152 may be planarized, for example, using CMP techniques. A dielectric material 1160 (e.g., including SiO2) may then be deposited on the planarized top surfaces. In some embodiments, before depositing dielectric material 1160, an ITO layer may be formed on the planarized top surfaces to make contact with p-type semiconductor layer 1140 of semiconductor mesa structures 1102. Back reflector and p-contacts 1162 may be formed in dielectric material 1160 and may contact p-type semiconductor layer 1140 of corresponding semiconductor mesa structures 1102. Back reflector and p-contacts 1162 may include, for example, Au, Ag, Al, Ti, Cu, Ni, ITO, or a combination thereof. Even though not shown in
Even though not shown in
As described above with respect to, for example,
As described above, the internal quantum efficiency of an LED depends on the relative rates of competitive radiative (light producing) recombination and non-radiative (lossy) recombination that occur in the active region of the LED. Non-radiative recombination processes in the active region include Shockley-Read-Hall (SRH) recombination at defect sites and electron-electron-hole (eeh) and/or electron-hole-hole (ehh) Auger recombination. The Auger recombination is a non-radiative process involving three carriers, which affects all sizes of LEDs. The internal quantum efficiency of an LED may be determined by:
where A, B, and C are the rates of SRH recombination, bimolecular (radiative) recombination, and Auger recombination, respectively, and Nis the charge-carrier density (i.e., charge-carrier concentration) in the active region.
In micro-LEDs, because the lateral size of each micro-LED may be comparable to the minority carrier diffusion length, a larger proportion of the total active region may be within a distance less than the minority carrier diffusion length from the micro-LED sidewall surfaces where the defect density and the defect-induced non-radiative recombination rate may be high due to the abrupt ending of the lattice structure, chemical contamination, and/or structural damages (e.g., due to dry etch). Therefore, a larger proportion of the injected carriers may diffuse to the regions near the sidewall surfaces, where the carriers may be subjected to a higher SRH recombination rate. This may cause the efficiency of the micro-LED to decrease (in particular, at low current injection), cause the peak efficiency of the micro-LED to decrease, and/or cause the peak efficiency operating current to increase. Increasing the injected current may cause the efficiency of the micro-LED to drop due to the higher eeh or ehh Auger recombination rate at a higher current density, and may also cause spectral shift of the emitted light. As the physical sizes of micro-LEDs are further reduced, efficiency losses due to surface recombination near the etched sidewall facets that include surface imperfections may become much more significant.
In addition, the performance of micro-LED may be very sensitive to temperature. For example, the electron and hole concentration, electron mobility, operation current and voltage, and energy bandgap of a micro-LED may change with junction temperature. Non-radiative recombination and leakage current may also increase at high operational current densities and high temperatures. For example, Auger recombination may be a temperature-dependent source of non-radiative recombination and can contribute to efficiency droop at high-injection current conditions. SRH recombination from trap states is also temperature dependent. Therefore, the efficiencies of micro-LEDs may decrease to cause brightness decay as the device heats up. The junction temperature change may also cause an energy bandgap decrease and thus a color displacement that may affect the color quality of the micro-LED at high junction temperatures. If no effective thermal control technique is employed, there may be a temperature gradient within a micro-LED array, which may cause different brightness decay and color shifting at different micro-LEDs of the micro-LED array. In micro-LEDs with low efficiencies, a high percentage of the electrical power may be converted to heat to heat up the micro-LEDs. Thus, the devices performance of the micro-LEDs may significantly deteriorate due to the increase of the operating temperature if no effective thermal control technique is employed. Some structures and external cooling devices may be used to alleviate the temperature-dependent performance droop by reducing the operating temperature, including modifying device architectures and using external cooling devices. However, due to the constraints in the energy budget and the form factor of near-eye displays, active thermal solution for local temperature control may not be feasible for micro-LEDs used in near-eye displays.
The dielectric materials commonly used as insulation materials in micro-LEDs may include, for example, SiO2, Si3N4, and Al2O3. SiO2 has been widely used as the dielectric material in CMOS technology that is mature to a great extent. Therefore, SiO2 is also widely used as the dielectric material in micro-LEDs that may be fabricated using processing techniques developed for or compatible with CMOS technology. However, the thermal conductivities of these dielectric materials, such as SiO2, Si3N4, and Al2O3, are generally much lower compared with the semiconductor materials of the micro-LEDs, and thus may not be able to efficiently and rapidly dissipate heat generated in the active regions of micro-LEDs into the backplane to maintain a uniform temperature distribution among the micro-LEDs in a micro-LED array.
The thermal resistance is a measure of resistance to heat flow through a given thickness of a material and may be determined by:
where A is the size of a thermal conductive material layer, L is the thickness of the thermal conductive material layer, and k is the thermal conductivity of the thermal conductive material. In the example shown in
According to certain embodiments, the low-thermal conductivity dielectric materials (e.g., SiO2, SiN, and Al2O3) commonly used in the interconnect layers and/or bonding layers of existing micro-LED devices may be replaced by high-thermal conductivity dielectric materials, such as aluminum nitride (AlN), beryllium oxide (BeO), and boron nitride (BN). The AlN dielectric layers can help to efficiently and rapidly dissipate heat generated in the active regions of micro-LEDs into the backplane to retain a uniform temperature distribution among the micro-LEDs in a micro-LED array. Therefore, the AlN layers may behave as efficient heat spreading layers between the micro-LED array and drive circuits on the backplane, and thus may provide a passive thermal control solution for maintaining desired local temperatures. In addition, as described above, using AlN rather than SiO2 may help mitigate the CTE mismatch among different materials in the micro-LED device, such as the silicon substrate, semiconductor epitaxial layers, and dielectric materials. Furthermore, due to the combability in the relevant processes, replacing dielectric materials such as SiO2 with AlN may not negatively impact the downstream process flow.
In addition, the intrinsic stress inside an AlN layer can be tuned, such that desired wafer bowing (e.g., low or similar bowing) of the wafers to be bonded may be achieved, which may make the downstream processes, such as wafer alignment and wafer-to-wafer hybrid bonding, easier to perform. Furthermore, AlN may have a much higher hardness (e.g., about 18 GPa) than SiO2 (e.g., about 10 GPa), and a higher fracture strength (e.g., about 1.54 GPa) than SiO2 (e.g., about 0.81 GPa). Thus, AlN layers used as the bonding layers may have lower rounding and/or trenches in areas adjacent to the metal interconnects after the planarization of the bonding layers. Therefore, the dielectric bonding area and bonding strength at the AlN-AlN bonding interface may be larger than those at the SiO2-SiO2 bonding interface. The surface roughness of AlN can be comparable to the surface roughness of SiO2, such as a few angstroms, and thus the AlN-AlN bonding and the SiO2-SiO2 bonding may have comparable bonding quality. A barrier layer may not need to be used between the metal interconnects and the AlN material in the bonding layer to prevent the diffusion of metal atoms into the AlN material and the semiconductor material. Additionally, in some micro-LED wafers, such as a GaN-on-Si wafer, an AlN layer may often be grown on the silicon substrate as the seed layer (or buffer layer) during the epitaxy growth. In some embodiments, this AlN seed layer may be used as the bonding layer and metal bonding pads can be formed in this AlN seed layer, and thus a deposition process (e.g., a spluttering process) may not be needed to deposit the AlN dielectric layer for hybrid bonding, which may simplify the downstream process flow.
The micro-LED wafer may include an array of micro-LEDs formed in an epitaxial layer stack. The epitaxial layer stack may include a first semiconductor layer 1310 (e.g., an n-type or p-type semiconductor layer), active layers 1320 (e.g., including quantum well layers and quantum barrier layers), and a second semiconductor layer 1330 (e.g., a p-type or n-type semiconductor layer). The epitaxial layer stack may be etched to form an array of semiconductor mesa structures. A passivation layer 1340 may be formed on sidewalls of the semiconductor mesa structures. Passivation layer 1340 may include, for example, a dielectric layer (e.g., including SiO2, SiN, and Al2O3) or an undoped semiconductor layer. A reflective metal layer 1350 (e.g., including Al, Cu, Au, Ag, Ti, or a combination) may be deposited on passivation layer 1340. In some embodiments, reflective metal layer 1350 may fill gaps between the semiconductor mesa structures. In some embodiments, a high-thermal conductivity dielectric material 1352 (e.g., including AlN) may be deposited in regions between the semiconductor mesa structures. The micro-LED wafer may include one or more dielectric layers (e.g., AlN layers) formed on the semiconductor mesa structures and high-thermal conductivity dielectric material 1352. Metal interconnects (e.g., copper or tungsten pads or plugs) may be formed in the one or more dielectric layers. In the illustrated example, the micro-LED wafer may include a bonding layer that includes an AlN layer 1360 and metal interconnects 1362 (e.g., copper pads or plugs) formed therein. In some embodiments, the internal stress of AlN layer 1360 may be tuned to achieve desired wafer bowing of the micro-LED wafer. In the illustrated example, metal interconnects 1362 may be reflective and may function as back reflectors and electrodes (e.g., anodes or cathodes) for the micro-LEDs.
The micro-LED wafer may be bonded to the backplane wafer by, for example, bonding the bonding layer that includes AlN layer 1360 and metal interconnects 1362 to the bonding layer that includes AlN layer 1372 and metal interconnects 1374, using a hybrid wafer-to-wafer bonding process described above and below. For example, the two bonding layers may be cleaned and activated by, for example, an ion (e.g., plasma) beam or a fast atom (e.g., Ar) beam. Ar sputtering may also remove the Cu oxide layer. In some embodiments, the backplane wafer and the micro-LED wafer may be rinsed with deionized water and blown dry using nitrogen gas (N2). The activated surface may be atomically clean and reactive for formation of direct bonds between wafers when they are brought into contact, for example, at room temperature. In some embodiments, compressive force may be applied to the two bonding layers such that the two bonding layers may be pressed against each other. Due to the surface activation, the AlN in AlN layer 1360 and the AlN in AlN layer 1372 may react and form chemical bonds between them because the surface atoms may have dangling bonds and may be in unstable energy states after the activation. Thus, the AlN in AlN layer 1360 and the AlN in AlN layer 1372 may be bonded together by van der Waals attractions, with or without heat treatment or pressure. During annealing, AlN layer 1360 that is in contact with AlN layer 1372 may strengthen the bonds through a two-step condensation reaction. The annealing may also cause metal interconnects 1362 and 1374 to expand such that metal interconnects 1362 and 1374 may be in contact and may form direct metallic bonds at the activated surfaces.
After the bonding, the substrate of the micro-LED wafer may be removed and a transparent conductive oxide (TCO) layer 1380 (e.g., such as an ITO layer) may be formed on first semiconductor layer 1310. TCO layer 1380 may form a common electrode (e.g., a common cathode or a common anode) for the micro-LEDs. In the illustrated example, non-native lenses 1390 may be fabricated in a dielectric material (e.g., SiN or SiO2), and may be bonded to TCO layer 1380. In some embodiments, non-native lenses 1390 may be fabricated in a dielectric material deposited on TCO layer 1380. In some embodiments, native lenses may be fabricated in first semiconductor layer 1310, and the common electrode may be formed on the native lenses and/or may be the portion of first semiconductor layer 1310 that has not been etched (which may be heavily doped to reduce the resistance).
In micro-LED device 1300, the bonding layers may have high thermal conductivities that may be comparable to the thermal conductivities of the semiconductor materials and metal materials. The material that fills gaps between the semiconductor mesa structures may also include metals or a high-thermal conductivity dielectric material (e.g., AlN). Therefore, heat generated in the semiconductor mesa structures may be more efficiently dissipated to the backplane wafer (which may include a heat sink and/or a heat control/recycle structure), thereby maintaining a low local temperature in the semiconductor mesa structures. In addition, the CTEs of the materials may be better matched, and thus processing the wafers at elevated temperatures (e.g., for annealing) and cooling the wafers may not cause damages or bowing to the micro-LED device. As described above, a barrier layer (e.g., including Ti, Ta, TiN, TaN, W, or a combination thereof, such as such as TiN/Ti, TaN/Ta, Ti/TiN, or Ta/TaN) may not need to be used between AlN layer 1360 and metal interconnects 1362, or between AlN layer 1372 and metal interconnects 1374. Furthermore, AlN may have a higher hardness or stiffness than SiO2, and thus may have lower rounding and/or trenches after the planarization of the bonding layers, such that the bonding area and bonding strength of the dielectric bonding between AlN layer 1360 and AlN layer 1372 may be improved over devices with SiO2 in the bonding layers.
The micro-LED wafer may include an array of micro-LEDs 1361 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1361 may include a mesa structure with sidewalls tilted inwardly in the light-emitting direction (e.g., the z direction). Even though not shown in
Micro-LED device 1301 may be fabricated by singulating micro-LEDs before bonding or after bonding as described above with respect to
The micro-LED wafer may include an array of micro-LEDs 1366 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1366 may include a mesa structure with sidewalls tilted inwardly in the light-emitting direction (e.g., the z direction). Even though not shown in
The micro-LED wafer may include an array of micro-LEDs 1363 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1363 may include a mesa structure with sidewalls tilted outwardly in the light-emitting direction (e.g., the z direction). Even though not shown in
Micro-LED device 1303 may be fabricated by singulating micro-LEDs 1363 before or after bonding the micro-LED wafer to the backplane wafer as described above with respect to
The micro-LED wafer may include an array of micro-LEDs 1367 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1367 may include a mesa structure with sidewalls tilted outwardly in the light-emitting direction (e.g., the z direction). Even though not shown in
Micro-LED device 1307 may be fabricated by singulating micro-LEDs 1367 before or after bonding the micro-LED wafer to the backplane wafer as described above with respect to
The micro-LED wafer may include an array of micro-LEDs 1365 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1365 may include a mesa structure with vertical. Even though not shown in
The micro-LED wafer may include an array of micro-LEDs 1368 formed in an epitaxial layer stack that may include an n-type semiconductor layer, active layers (e.g., including quantum well layers and quantum barrier layers), and a p-type semiconductor layer. Each micro-LED 1368 may include a mesa structure with vertical. Even though not shown in
As described above, other high-thermal conductivity dielectric materials may also be used in micro-LED devices to efficiently and rapidly dissipate heat generated in the active regions of micro-LEDs. For example, beryllium oxide (BeO) and boron nitride (BN), such as amorphous boron nitride (a-BN), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN), or Wurtzite boron nitride (w-BN), may have high thermal conductivity and high energy bandgap, and thus may be used as electrical insulating materials in micro-LED devices.
Operations in block 1710 of flowchart 1700 may include obtaining a micro-LED wafer that includes an array of micro-LEDs. The array of micro-LEDs may include an array of semiconductor mesa structures and electrical and optical insulation materials between the semiconductor mesa structures of the array of semiconductor mesa structures. The array of semiconductor mesa structures may be etched in an epitaxial layer stack grown on a substrate. The epitaxial layer stack may include a p-type semiconductor layer, an active region that includes one or more quantum well layers and two or more quantum barrier layers, and an n-type semiconductor layer. Each micro-LED of the array of micro-LEDs may include a semiconductor mesa structure of the array of semiconductor mesa structures, a passivation layer on sidewalls of the semiconductor mesa structure, and a reflective metal layer on the passivation layer. In some embodiments, the reflective metal layer may fill regions between the semiconductor mesa structures of the array of semiconductor mesa structures. In some embodiments, regions between the semiconductor mesa structures of the array of semiconductor mesa structures may be filled with a high-thermal conductivity dielectric material, such as AlN. In some embodiments, the array of micro-LEDs may include a back reflector and contact layer on the semiconductor mesa structures. The back reflector and contact layer may be in contact with the p-type semiconductor layer or the n-type semiconductor layer, and may include, for example, Au, Ag, Al, Ti, Cu, Ni, ITO, or a combination thereof
Optional operations in block 1720 may include depositing an AlN bonding layer on the array of micro-LEDs on the micro-LED wafer. For example, the micro-LED wafer may be pre-cleaned using the RCA cleaning method to remove any organic and metallic contaminants, and then the AlN bonding layer may be deposited on the array of micro-LEDs by sputtering aluminum in reactive N2 atmosphere. In some embodiments, an annealing process may be performed at an elevated temperature to densify the AlN bonding layer. In some embodiments, an AlN layer may be grown on a substrate and used as a seed layer (or buffer layer) during the epitaxy growth. This AlN seed layer may be used as the AlN bonding layer, and metal bonding pads can be formed in this AlN seed layer, such that a deposition process (e.g., a spluttering process) may not be needed to deposit the AlN bonding layer for the hybrid bonding.
Operations in block 1730 may include forming metal bonding pads in the AlN bonding layer. For example, the AlN bonding layer may be etched to form trenches in the AlN bonding layer, and a metal material (e.g., Cu or W) may be deposited in the trenches and on the MN bonding layer. In some embodiments, a barrier layer may be formed on sidewalls of the trenches before the deposition of the metal material. The metal material in the trenches may be used as the metal bonding pads for hybrid bonding.
Operations in block 1740 may include planarizing and activating the AlN bonding layer. For example, the AlN bonding layer may be planarized using CMP, to remove the metal material on the AlN bonding layer and form a flat, smooth surface at the bonding surface of the AlN bonding layer. The planarized bonding surface of the AlN bonding layer may be activated by one or more plasma etching processes, using, for example, O2, Ar, and SF6, and may be cleaned using, for example, deionized water and blown dry with N2.
Operations in block 1715 of flowchart 1700 may include obtaining a backplane wafer including LED drive circuits formed thereon. The backplane wafer may include one or more dielectric layers and metal interconnects formed in the dielectric layers. At block 1725, an AlN bonding layer may be deposited on the backplane wafer in operations similar to the operations of block 1720. At block 1735, metal bonding pads may be formed in the AlN bonding layer deposited on the backplane wafer using operations similar to the operations of block 1730. At block 1745, the AlN bonding layer on the backplane wafer may be planarized and activated using operations similar to the operations of block 1740.
In block 1750, the AlN bonding layer of the micro-LED wafer may be bonded to the AlN bonding layer of the backplane wafer, for example, at room temperature. For example, the backplane wafer and the micro-LED wafer may be brought together such that the AlN bonding layer on the micro-LED wafer may contact the AlN bonding layer on the backplane wafer, to form AlN-AlN bonding at room temperature. In some embodiments, the backplane wafer may be compressed against the micro-LED wafer.
In block 1760, the bonded wafer stack may be annealed at an elevated temperature to cause the expansion of the metal bonding pads, such that the metal bonding pads of the micro-LED wafer may contact the metal bonding pads of the backplane wafer to form metal-metal bonds. After the annealing, the substrate of the micro-LED wafer may be removed, a transparent common cathode or anode (e.g., an ITO layer) may be formed on the exposed semiconductor layer (e.g., the n-type semiconductor layer or the p-type semiconductor layer). In some embodiments, light extraction structures, such as micro-lenses or gratings, may be formed on or bonded to the transparent common cathode or anode.
Embodiments disclosed herein may be used to implement components of an artificial reality system or may be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been adjusted in some manner before presentation to a user, which may include, for example, a virtual reality, an augmented reality, a mixed reality, a hybrid reality, or some combination and/or derivatives thereof. Artificial reality content may include completely generated content or generated content combined with captured (e.g., real-world) content. The artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of which may be presented in a single channel or in multiple channels (such as stereo video that produces a three-dimensional effect to the viewer). Additionally, in some embodiments, artificial reality may also be associated with applications, products, accessories, services, or some combination thereof, that are used to, for example, create content in an artificial reality and/or are otherwise used in (e.g., perform activities in) an artificial reality. The artificial reality system that provides the artificial reality content may be implemented on various platforms, including an HMD connected to a host computer system, a standalone HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers.
Memory 1820 may be coupled to processor(s) 1810. In some embodiments, memory 1820 may offer both short-term and long-term storage and may be divided into several units. Memory 1820 may be volatile, such as static random access memory (SRAM) and/or dynamic random access memory (DRAM) and/or non-volatile, such as read-only memory (ROM), flash memory, and the like. Furthermore, memory 1820 may include removable storage devices, such as secure digital (SD) cards. Memory 1820 may provide storage of computer-readable instructions, data structures, program modules, and other data for electronic system 1800. In some embodiments, memory 1820 may be distributed into different hardware modules. A set of instructions and/or code might be stored on memory 1820. The instructions might take the form of executable code that may be executable by electronic system 1800, and/or might take the form of source and/or installable code, which, upon compilation and/or installation on electronic system 1800 (e.g., using any of a variety of generally available compilers, installation programs, compression/decompression utilities, etc.), may take the form of executable code.
In some embodiments, memory 1820 may store a plurality of application modules 1822 through 1824, which may include any number of applications. Examples of applications may include gaming applications, conferencing applications, video playback applications, or other suitable applications. The applications may include a depth sensing function or eye tracking function. Application modules 1822-1824 may include particular instructions to be executed by processor(s) 1810. In some embodiments, certain applications or parts of application modules 1822-1824 may be executable by other hardware modules 1880. In certain embodiments, memory 1820 may additionally include secure memory, which may include additional security controls to prevent copying or other unauthorized access to secure information.
In some embodiments, memory 1820 may include an operating system 1825 loaded therein. Operating system 1825 may be operable to initiate the execution of the instructions provided by application modules 1822-1824 and/or manage other hardware modules 1880 as well as interfaces with a wireless communication subsystem 1830 which may include one or more wireless transceivers. Operating system 1825 may be adapted to perform other operations across the components of electronic system 1800 including threading, resource management, data storage control and other similar functionality.
Wireless communication subsystem 1830 may include, for example, an infrared communication device, a wireless communication device and/or chipset (such as a Bluetooth® device, an IEEE 802.11 device, a Wi-Fi device, a WiMax device, cellular communication facilities, etc.), and/or similar communication interfaces. Electronic system 1800 may include one or more antennas 1834 for wireless communication as part of wireless communication subsystem 1830 or as a separate component coupled to any portion of the system. Depending on desired functionality, wireless communication subsystem 1830 may include separate transceivers to communicate with base transceiver stations and other wireless devices and access points, which may include communicating with different data networks and/or network types, such as wireless wide-area networks (WWANs), wireless local area networks (WLANs), or wireless personal area networks (WPANs). A WWAN may be, for example, a WiMax (IEEE 802.16) network. A WLAN may be, for example, an IEEE 802.11x network. A WPAN may be, for example, a Bluetooth network, an IEEE 802.15x, or some other types of network. The techniques described herein may also be used for any combination of WWAN, WLAN, and/or WPAN. Wireless communications subsystem 1830 may permit data to be exchanged with a network, other computer systems, and/or any other devices described herein. Wireless communication subsystem 1830 may include a means for transmitting or receiving data, such as identifiers of HMD devices, position data, a geographic map, a heat map, photos, or videos, using antenna(s) 1834 and wireless link(s) 1832. Wireless communication subsystem 1830, processor(s) 1810, and memory 1820 may together comprise at least a part of one or more of a means for performing some functions disclosed herein.
Embodiments of electronic system 1800 may also include one or more sensors 1890. Sensor(s) 1890 may include, for example, an image sensor, an accelerometer, a pressure sensor, a temperature sensor, a proximity sensor, a magnetometer, a gyroscope, an inertial sensor (e.g., a module that combines an accelerometer and a gyroscope), an ambient light sensor, or any other similar module operable to provide sensory output and/or receive sensory input, such as a depth sensor or a position sensor. For example, in some implementations, sensor(s) 1890 may include one or more inertial measurement units (IMUs) and/or one or more position sensors. An IMU may generate calibration data indicating an estimated position of the HMD device relative to an initial position of the HMD device, based on measurement signals received from one or more of the position sensors. A position sensor may generate one or more measurement signals in response to motion of the HMD device. Examples of the position sensors may include, but are not limited to, one or more accelerometers, one or more gyroscopes, one or more magnetometers, another suitable type of sensor that detects motion, a type of sensor used for error correction of the IMU, or any combination thereof. The position sensors may be located external to the IMU, internal to the IMU, or any combination thereof. At least some sensors may use a structured light pattern for sensing.
Electronic system 1800 may include a display module 1860. Display module 1860 may be a near-eye display, and may graphically present information, such as images, videos, and various instructions, from electronic system 1800 to a user. Such information may be derived from one or more application modules 1822-1824, virtual reality engine 1826, one or more other hardware modules 1880, a combination thereof, or any other suitable means for resolving graphical content for the user (e.g., by operating system 1825). Display module 1860 may use LCD technology, LED technology (including, for example, OLED, ILED, μ-LED, AMOLED, TOLED, etc.), light emitting polymer display (LPD) technology, or some other display technology.
Electronic system 1800 may include a user input/output module 1870. User input/output module 1870 may allow a user to send action requests to electronic system 1800. An action request may be a request to perform a particular action. For example, an action request may be to start or end an application or to perform a particular action within the application. User input/output module 1870 may include one or more input devices. Example input devices may include a touchscreen, a touch pad, microphone(s), button(s), dial(s), switch(es), a keyboard, a mouse, a game controller, or any other suitable device for receiving action requests and communicating the received action requests to electronic system 1800. In some embodiments, user input/output module 1870 may provide haptic feedback to the user in accordance with instructions received from electronic system 1800. For example, the haptic feedback may be provided when an action request is received or has been performed.
Electronic system 1800 may include a camera 1850 that may be used to take photos or videos of a user, for example, for tracking the user's eye position. Camera 1850 may also be used to take photos or videos of the environment, for example, for VR, AR, or MR applications. Camera 1850 may include, for example, a complementary metal-oxide- semiconductor (CMOS) image sensor with a few millions or tens of millions of pixels. In some implementations, camera 1850 may include two or more cameras that may be used to capture 3-D images.
In some embodiments, electronic system 1800 may include a plurality of other hardware modules 1880. Each of other hardware modules 1880 may be a physical module within electronic system 1800. While each of other hardware modules 1880 may be permanently configured as a structure, some of other hardware modules 1880 may be temporarily configured to perform specific functions or temporarily activated. Examples of other hardware modules 1880 may include, for example, an audio output and/or input module (e.g., a microphone or speaker), a near field communication (NFC) module, a rechargeable battery, a battery management system, a wired/wireless battery charging system, etc. In some embodiments, one or more functions of other hardware modules 1880 may be implemented in software.
In some embodiments, memory 1820 of electronic system 1800 may also store a virtual reality engine 1826. Virtual reality engine 1826 may execute applications within electronic system 1800 and receive position information, acceleration information, velocity information, predicted future positions, or any combination thereof of the HMD device from the various sensors. In some embodiments, the information received by virtual reality engine 1826 may be used for producing a signal (e.g., display instructions) to display module 1860. For example, if the received information indicates that the user has looked to the left, virtual reality engine 1826 may generate content for the HMD device that mirrors the user's movement in a virtual environment. Additionally, virtual reality engine 1826 may perform an action within an application in response to an action request received from user input/output module 1870 and provide feedback to the user. The provided feedback may be visual, audible, or haptic feedback. In some implementations, processor(s) 1810 may include one or more GPUs that may execute virtual reality engine 1826.
In various implementations, the above-described hardware and modules may be implemented on a single device or on multiple devices that can communicate with one another using wired or wireless connections. For example, in some implementations, some components or modules, such as GPUs, virtual reality engine 1826, and applications (e.g., tracking application), may be implemented on a console separate from the head-mounted display device. In some implementations, one console may be connected to or support more than one HMD.
In alternative configurations, different and/or additional components may be included in electronic system 1800. Similarly, functionality of one or more of the components can be distributed among the components in a manner different from the manner described above. For example, in some embodiments, electronic system 1800 may be modified to include other system environments, such as an AR system environment and/or an MR environment.
The methods, systems, and devices discussed above are examples. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For instance, in alternative configurations, the methods described may be performed in an order different from that described, and/or various stages may be added, omitted, and/or combined. Also, features described with respect to certain embodiments may be combined in various other embodiments. Different aspects and elements of the embodiments may be combined in a similar manner. Also, technology evolves and, thus, many of the elements are examples that do not limit the scope of the disclosure to those specific examples.
Specific details are given in the description to provide a thorough understanding of the embodiments. However, embodiments may be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments. This description provides example embodiments only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the preceding description of the embodiments will provide those skilled in the art with an enabling description for implementing various embodiments. Various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the present disclosure.
Also, some embodiments were described as processes depicted as flow diagrams or block diagrams. Although each may describe the operations as a sequential process, many of the operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional steps not included in the figure. Furthermore, embodiments of the methods may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments to perform the associated tasks may be stored in a computer-readable medium such as a storage medium. Processors may perform the associated tasks.
It will be apparent to those skilled in the art that substantial variations may be made in accordance with specific requirements. For example, customized or special-purpose hardware might also be used, and/or particular elements might be implemented in hardware, software (including portable software, such as applets, etc.), or both. Further, connection to other computing devices such as network input/output devices may be employed.
With reference to the appended figures, components that can include memory can include non-transitory machine-readable media. The term “machine-readable medium” and “computer-readable medium” may refer to any storage medium that participates in providing data that causes a machine to operate in a specific fashion. In embodiments provided hereinabove, various machine-readable media might be involved in providing instructions/code to processing units and/or other device(s) for execution. Additionally or alternatively, the machine-readable media might be used to store and/or carry such instructions/code. In many implementations, a computer-readable medium is a physical and/or tangible storage medium. Such a medium may take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and/or optical media such as compact disk (CD) or digital versatile disk (DVD), punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read instructions and/or code. A computer program product may include code and/or machine-executable instructions that may represent a procedure, a function, a subprogram, a program, a routine, an application (App), a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements.
Those of skill in the art will appreciate that information and signals used to communicate the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Terms, “and” and “or” as used herein, may include a variety of meanings that are also expected to depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B, or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B, or C, here used in the exclusive sense. In addition, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, the term “at least one of” if used to associate a list, such as A, B, or C, can be interpreted to mean A, B, C, or any combination of A, B, and/or C, such as AB, AC, BC, AA, ABC, AAB, AABBCCC, or the like.
Further, while certain embodiments have been described using a particular combination of hardware and software, it should be recognized that other combinations of hardware and software are also possible. Certain embodiments may be implemented only in hardware, or only in software, or using combinations thereof. In one example, software may be implemented with a computer program product containing computer program code or instructions executable by one or more processors for performing any or all of the steps, operations, or processes described in this disclosure, where the computer program may be stored on a non-transitory computer readable medium. The various processes described herein can be implemented on the same processor or different processors in any combination.
Where devices, systems, components or modules are described as being configured to perform certain operations or functions, such configuration can be accomplished, for example, by designing electronic circuits to perform the operation, by programming programmable electronic circuits (such as microprocessors) to perform the operation such as by executing computer instructions or code, or processors or cores programmed to execute code or instructions stored on a non-transitory memory medium, or any combination thereof. Processes can communicate using a variety of techniques, including, but not limited to, conventional techniques for inter-process communications, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.
The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that additions, subtractions, deletions, and other modifications and changes may be made thereunto without departing from the broader spirit and scope as set forth in the claims. Thus, although specific embodiments have been described, these are not intended to be limiting. Various modifications and equivalents are within the scope of the following claims.
