The present disclosure relates generally to devices integrating fin-type field effect transistors (FinFETs) and planar electronic devices on a common substrate and methods of forming such devices.
Advances in technology have resulted in smaller and more powerful personal computing devices. For example, there currently exist a variety of portable personal computing devices, including wireless computing devices, such as portable wireless telephones, personal digital assistants (PDAs), and paging devices that are small, lightweight, and easily carried by users. More specifically, portable wireless telephones, such as cellular telephones and Internet Protocol (IP) telephones, can communicate voice and data packets over wireless networks. Further, many such wireless telephones include other types of devices that are incorporated therein. For example, a wireless telephone can also include a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such wireless telephones can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. However, power consumption of such portable devices can quickly deplete a battery and diminish a user's experience.
Reducing power consumption has led to smaller circuitry feature sizes and operating voltages within such portable devices. Reduction of feature size and operating voltages, while reducing power consumption, also increases sensitivity to noise and to manufacturing process variations. Fin-type field effect transistors (FinFETs) are low-power, high speed transistors that can be densely packed on a substrate. Unfortunately, FinFETs are not suitable for all purposes in integrated circuit designs. Different applications may involve use of different types of transistor devices.
One application may include both FinFETs and planar metal oxide semiconductor field effect transistors (MOSFETs) either on silicon on insulator (SOI) or bulk silicon substrate. However, techniques to integrate FinFETS and MOSFETs generally tend to result in large height differences between the FinFET gates and the MOSFET gates. As such, this height difference results in complex lithography and etching processes in addition to several manufacturing steps such as the use of multiple resist layers to form the FinFETs and the MOSFET devices.
In a particular embodiment, an apparatus is disclosed. The apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.
In another particular embodiment, a method of fabricating an electronic device is disclosed. The method includes forming a patterned resist layer by applying a template to fluidic resist material supported by a substrate and forming the electronic device using the formed patterned resist layer. The template has an imprint surface that includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device, and a second region having a second pattern adapted to fabricate a planar electronic device.
In another particular embodiment, a device is disclosed. The device includes a fin field effect transistor (FinFET) device and a planar electronic device. The FinFET device and the planar electronic device are located on a monolithic substrate. The FinFET device and the planar electronic device are formed by patterning a fluidic resist material with a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a FinFET device and a second region having a second pattern adapted to fabricate a planar electronic device.
A particular advantage provided by at least one of the disclosed embodiments is that a FinFET device and a planar electronic device can be formed on a common substrate using imprint technology without the need for additional resist layers being applied to the substrate since the FinFET device and the planar electronic device are formed at substantially the same time.
Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.
Referring to
The first topological pattern 116 and the second topological pattern 118 are transferred to an imprintable medium 122 by pressing the template 110 into the imprintable medium 122 on the substrate 120. An example of transferring such patterns into an imprintable medium is illustrated in
A resolution of the features on the template imprint surface may be a limiting factor on an attainable resolution of features formed on the substrate. As such, a technique capable of very high resolution may be beneficial in forming the imprint surface pattern. The template imprint surface pattern may be formed by electron beam writing. Additionally, release characteristics of the template 110 can also be a consideration, since poor template release or sticking may cause peeling or other damage to the imprinted layer resulting in the degradation of dimensional integrity of the imprinted pattern or features. The template 110 can, for example, be treated with a surface treatment material such as a lubricant coating to form a release layer on the template 110.
Referring to
Referring to
Referring to
Referring to
Referring to
Continuing to 606, the imprintable medium (e.g. resist layer) is formed into a solid layer. For example, when a thermosetting or thermoplastic polymer resin is used, the resin is heated to a temperature, such that upon contact with the template, the resin is sufficiently flowable to flow into the pattern features defined on the template. The patterned resin is then cooled. As another example, when a photo-curable liquid resist is used, the template is typically made of transparent material. In this case, after the template and resist are pressed together, the resist is cured in UV light and becomes solid.
Moving to 608, the template is separated from the imprintable medium and a solid imprinted layer including the imprinted pattern is formed on the substrate. Continuing to 610, the imprinted FinFET pattern and the planar electronic pattern is transferred from the imprinted resist layer (or other imprintable medium) to the substrate via a pattern transfer process, such as reactive ion etching or wet chemical etching, thereby forming features of a FinFET device and features of a planar electronic device (e.g. FET) on the substrate. In an exemplary embodiment, the planar electronic device may be a metal oxide semiconductor field effect transistor (MOSFET). The features of the FinFET device and the planar electronic device are formed without using additional patterned resist layers. A plurality of FinFET and planar electronic device patterns can be included on the imprint surface of the template, thereby forming multiple FinFETs and planar electronic devices.
After the formation of the FinFET device and the planar electronic device, processing occurs for formation of the remaining integrated circuit structures including interconnects, contacts, wiring layers, etc. (not shown), which are typically formed above the device level. Such processing includes the formation of insulating layers and the formation of conducting layers. The insulating layers and the conducting layers are selectively etched to form the remaining integrated circuit structures.
Referring to
Those of skill would further appreciate that various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software that is executed by a processor depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.
Number | Name | Date | Kind |
---|---|---|---|
6190929 | Wang et al. | Feb 2001 | B1 |
7180134 | Yang et al. | Feb 2007 | B2 |
20020163513 | Tsuji | Nov 2002 | A1 |
20030138704 | Mei et al. | Jul 2003 | A1 |
20040259295 | Tomiye et al. | Dec 2004 | A1 |
20040266076 | Doris et al. | Dec 2004 | A1 |
20040266088 | Luyken et al. | Dec 2004 | A1 |
20050224452 | Spiess et al. | Oct 2005 | A1 |
20050239252 | Ahn et al. | Oct 2005 | A1 |
20050242391 | She et al. | Nov 2005 | A1 |
20050266693 | Maekawa | Dec 2005 | A1 |
20060157788 | Joshi et al. | Jul 2006 | A1 |
20070001232 | King et al. | Jan 2007 | A1 |
20070069293 | Kavalieros et al. | Mar 2007 | A1 |
20070104813 | Wuister et al. | May 2007 | A1 |
20070257389 | Ruf | Nov 2007 | A1 |
20070261016 | Sandhu et al. | Nov 2007 | A1 |
20080265338 | Yu et al. | Oct 2008 | A1 |
20090166770 | Gluschenkov et al. | Jul 2009 | A1 |
20100165767 | Lin et al. | Jul 2010 | A1 |
Number | Date | Country |
---|---|---|
1726433 | Jan 2006 | CN |
101292346 | Oct 2008 | CN |
102006019962 | Nov 2007 | DE |
1331516 | Jul 2003 | EP |
1387216 | Feb 2004 | EP |
2003249444 | Sep 2003 | JP |
2004071587 | Mar 2004 | JP |
2005527110 | Sep 2005 | JP |
2006080519 | Mar 2006 | JP |
2009006619 | Jan 2009 | JP |
2012501084 | Jan 2012 | JP |
2004044654 | May 2004 | WO |
2008047447 | Apr 2008 | WO |
Entry |
---|
International Search Report and Written Opinion—PCT/US2010/037241, International Searching Authority—European Patent Office, Nov. 5, 2010. |
Taiwan Search Report—TW099118089—TIPO—May 29, 2013. |
Yaghmaie F., et al., “A Simplified Method to Produce a Functional Test Stamp for Nanoimprint Lithography (NIL)”, IEEE Sensors Journal, Mar. 2009, vol. 9 (3), pp. 233-234. |
Number | Date | Country | |
---|---|---|---|
20100308408 A1 | Dec 2010 | US |