Patent Application
20080157313
Embodiments of the present invention generally relate to the field of integrated circuit packages, and, more particularly to an array capacitor for decoupling multiple voltages.
Array capacitors are being attached to, or embedded in, the substrates of high frequency integrated circuit packages to manage power delivery to the die(s). Additionally, traditional array capacitors provide a single fixed capacitance for decoupling a single voltage.
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which:
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
While shown as including three electrically isolated capacitor regions, array capacitor 100 may include any number of unique capacitor regions which may or may not have the same capacitance values. In one embodiment, capacitor regions 102 and 106 have capacitance values of about 2 microfarads, while capacitor region 104 has a capacitance value of about 40 microfarads. In another embodiment, capacitor regions 102 and 106 are designed to provide decoupling to an I/O source voltage, while capacitor region 104 is designed to provide decoupling to a core (or common collector) voltage.
Bridge regions 108 and 110 electrically isolate and reduce crosstalk between capacitor regions 102, 104, and 106. Bridge regions 108 and 110 can be made of ceramic or other dielectric material. One skilled in the art would appreciate that the unique capacitor regions shown in array capacitor 100 can provide decoupling for multiple voltages.
Top surface 112 contains bumps or other conductive elements through which array capacitor 100 may be coupled with other components, for example a substrate. In one embodiment, bumps on top surface 112 are coated with nickel and tin to enable soldering to a substrate. As shown, vertical vias 116 carry current from top surface 112 to capacitor plates 118, which store charge.
While shown as including three electrically isolated capacitor regions, array capacitor 200 may include any number of unique capacitor regions which may or may not have the same capacitance values. In one embodiment, capacitor regions 202 and 206 have capacitance values of about 2 microfarads, while capacitor region 204 has a capacitance value of about 40 microfarads. In another embodiment, capacitor regions 202 and 206 are designed to provide decoupling to an I/O source voltage, while capacitor region 204 is designed to provide decoupling to a core (or common collector) voltage.
Bridge regions 208 and 210 electrically isolate and reduce crosstalk between capacitor regions 202, 204, and 206. Bridge regions 208 and 210 can be made of ceramic or other dielectric material. One skilled in the art would appreciate that the unique capacitor regions shown in array capacitor 200 can provide decoupling for multiple voltages.
Top contacts 212 and bottom contacts 214 represent bumps or other conductive elements through which array capacitor 200 may be coupled with other components, for example a substrate. As shown, vertical vias 216 carry current from bottom contacts 214 to top contacts 212, while capacitor plates 218 store charge, for example if array capacitor 200 is to be embedded within a substrate.
Dielectric layers 402 represent organic dielectric material, such as epoxy based dielectric, that has been added to a substrate as part of a build-up process. Metal traces, not shown, may be included in dielectric layers 402 to route signals to and from die 410.
Package connections 404 provide an interface between IC package 400 and other components, for example through a socket. In one embodiment, signals are routed through package connections 404 to traces in dielectric layers 402 while power and ground are routed through package connections 404 to contacts on the surface of array capacitor 100.
Micro-vias 406 may be formed on top of dielectric layers 402 as part of a manufacturing process to route the signal traces in dielectric layers 402 to the top of the package substrate.
Die bumps 408 may provide the mechanical and electrical connection between micro-vias 406 and die 410.
Die 410 may represent any type of integrated circuit device or devices that may benefit from the use of an array capacitor for decoupling multiple voltages, for example a multi-core processor.
Dielectric layers 502 represent organic dielectric material, such as epoxy based dielectric, that has been added to a substrate as part of a build-up process. Metal traces, not shown, may be included in dielectric layers 502 to route signals to and from die 510. To accommodate array capacitor 200, a portion of dielectric layers 502 may be removed, by etching or drilling for example, to expose micro-vias, or conductive elements coupled with package connections 504.
Package connections 504 provide an interface between IC package 500 and other components, for example through a socket. In one embodiment, signals are routed through package connections 504 to traces in dielectric layers 502 while power and ground are routed through package connections 504 to contacts on the bottom surface of array capacitor 200.
Micro-vias 506 may be formed on top of contacts on the top surface of array capacitor 200 as part of a manufacturing process to route the vertical vias in array capacitor 200 to the top of the package substrate.
Die bumps 508 may provide the mechanical and electrical connection between micro-vias 506 and die 510.
Die 510 may represent any type of integrated circuit device or devices that may benefit from the use of an array capacitor for decoupling multiple voltages, for example a multi-core processor.
Processor(s) 602 may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, processors(s) 602 are Intel® processors. Processor(s) 602 may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system.
Memory controller 604 may represent any type of chipset or control logic that interfaces system memory 606 with the other components of electronic appliance 600. In one embodiment, the connection between processor(s) 602 and memory controller 604 may be referred to as a front-side bus. In another embodiment, memory controller 604 may be referred to as a north bridge.
System memory 606 may represent any type of memory device(s) used to store data and instructions that may have been or will be used by processor(s) 602. Typically, though the invention is not limited in this respect, system memory 606 will consist of dynamic random access memory (DRAM). In one embodiment, system memory 606 may consist of Rambus DRAM (RDRAM). In another embodiment, system memory 606 may consist of double data rate synchronous DRAM (DDRSDRAM).
Input/output (I/O) controller 608 may represent any type of chipset or control logic that interfaces I/O device(s) 612 with the other components of electronic appliance 600. In one embodiment, I/O controller 608 may be referred to as a south bridge. In another embodiment, I/O controller 608 may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003.
Network controller 610 may represent any type of device that allows electronic appliance 600 to communicate with other electronic appliances or devices. In one embodiment, network controller 610 may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller 610 may be an Ethernet network interface card.
Input/output (I/O) device(s) 612 may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance 600.
In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.
Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.
