Patent Application
20230360896
Embodiments relate to the field of semiconductor manufacturing and, in particular, to a semiconductor processing tool that is configured to provide frequency retrieval from plasma power sources.
In plasma processing tools, the plasma is ignited by a cathode that is coupled to processing gasses within a chamber. In most tools, a power supply is coupled to the cathode through an impedance matching network (sometimes referred to simply as a “match”). The match allows for the impedance of the system to be adjusted in order to match the impedance of the load to which the cathode is coupled. The load has a wide range of impedances that are dictated by parameters such as processing conditions, chamber architecture, and the like. Matching the impedances is important in order to provide efficient power transfer from the power supply to the load.
In addition to matching impedances, it is also important to know the precise frequency of the power being supplied by the power supply. Accordingly, frequency detection systems may be included in the power delivery network. Currently existing schemes for frequency identification require messaging or other information passing from different systems or subsystems in order to determine the frequency. Optimal messaging and/or information passing requires a point-to-point network connection and is subject to large group delays between actuator control and feedback across various elements of a dynamic system. Accordingly, the necessary frequency feedback is subject to delays.
Embodiments disclosed herein include a processing tool. In an embodiment the processing tool comprises a transmission line sensor, and an analog to digital (A/D) converter. In an embodiment, the processing tool may further comprise a digital down converter (DDC), and a frequency digital phase lock loop (dPLL). In an embodiment, the processing tool may further comprise a transmission line scaling module.
Additional embodiments disclosed herein may also include a processing tool. In an embodiment, the processing tool comprises a transmission line sensor, and an analog to digital (A/D) converter. In an embodiment, the processing tool may further comprise a digital down converter (DDC), and a transmission line scaling module.
Additional embodiments may include a semiconductor processing tool. In an embodiment, the semiconductor processing tool may include a chamber, a plasma source coupled to the chamber, and a signal processing module for determining a frequency of a plasma generated by the plasma source. In an embodiment, the signal processing module comprises a transmission line sensor, an analog to digital (A/D) converter, a digital down converter (DDC), a frequency digital phase lock loop (dPLL), and a transmission line scaling module.
Systems described herein include a power delivery architecture configured to provide frequency retrieval from plasma power sources. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments. It will be apparent to one skilled in the art that embodiments may be practiced without these specific details. In other instances, well-known aspects are not described in detail in order to not unnecessarily obscure embodiments. Furthermore, it is to be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.
As noted above, for real-time process control and monitoring, the knowledge of the frequency of the process power is important. Accordingly, embodiments disclosed herein include a detection and retrieval process with high accuracy, minimal group delay, and optimal control. Additionally, the scheme described herein is autonomous and does not require messaging and/or information passing from other systems or subsystems.
Referring now to
In an embodiment, the plasma chamber 120 may be coupled to a power delivery architecture. For example, the power delivery architecture may include one or more power supplies 1321-132n. In the illustrated embodiment, a plurality of power supplies 132 are shown. However, it is to be appreciated that a single power supply 132 may be used in some embodiments. In an embodiment, the power supplies 132 may include any type of power supply. For example, the power supplies 132 may be RF power supplies, microwave power supplies, direct current (DC) power supplies, pulsed DC power supplies, or the like.
In an embodiment, the power supplies 132 may be coupled to the cathode 122 through an impedance matching network 130. The impedance matching network 130 alters the impedance of the power delivery architecture in order to match the load in the chamber 120. Due to changes in processing conditions (e.g. gas flow rates, pressure, temperature, etc.) the impedance of the load can vary. As such, the impedance matching network 130 is used to match the changing impedance in order to provide efficient power delivery into the chamber (i.e., with no or minimal reflected power).
In an embodiment, sensors 151 and 152 may be provided on opposite ends of the impedance matching network 130. For example, sensors 1511-151n may be on an upstream side of the impedance matching network 130, and sensor 152 may be on a downstream side of the impedance matching network 130. The “upstream” side may refer to the input side of the matching network 130, and the “downstream” side may refer to the output side of the matching network 130. As shown, a plurality of sensors 1511-151n are provided on the upstream side of the impedance matching network 130. The number of sensors 151 may be equal to the number of power supplies 132. That is, each power supply 132 may have a dedicated sensor 151. The downstream side of the impedance matching network 130 may have a single sensor 152. However, it is to be appreciated that when there is more than one output from the matching network 130, there may be additional sensors 152. For example, in a case where there is two outputs (e.g., for a center of the chamber 120 and an edge of the chamber 120), there may be two sensors 152.
In the case of multiple sensors 151, the plurality of sensors 1511-n may be fabricated on a single PCB. That is, a single module may include multiple sensors. Generally, embodiments described herein include electrical shielding techniques that limit the cross coupling between sensors on a single PCB.
In
In an embodiment, the sensors 151 and 152 may be communicatively coupled with a process power control module 134. For example, an RF process power control module 134 may be provided in
In an embodiment, the process power control module 134 may be coupled to the impedance matching network by a digital/analog link. Through the digital/analog link, the process power control module 134 may be able to send control signals to the impedance matching network 130. For example, control signals may be used to adjust the capacitance of variable capacitors within the impedance matching network 130. Additionally, the process power control module 134 may be coupled to the power supplies 132 by a digital/analog link. As such, the process power control module 134 is capable of coordinated impedance tuning.
Referring now to
In an embodiment, the current loop 254 may include inner vias 2558 and outer vias 255A. The vias 255 may be coupled to each other by traces 256 on a top surface of the PCB 253 and by traces 257 on a bottom surface of the PCB 253. In the illustrated embodiment, the current loop 254 includes a pair of windings around the aperture 260.
In an embodiment, the voltage ring 265 may include an inner conductive ring 266 and an outer conductive ring 268. An insulating ring 267 may be provided between the inner ring 266 and the outer ring 268. The inner ring 266 may be the voltage pickup surface and the outer ring 268 may be grounded. In an embodiment, the inner ring 266 may define the outer perimeter of the aperture 260.
In an embodiment, the sensor 250 may further comprise a guard ring 270 that surrounds an outer perimeter of the current loop 254. In an embodiment, the guard ring 270 may be grounded. The guard ring 270 may include vias (not shown) that couple the guard ring 270 to a ring on the bottom side of the PCB 253 with a similar size and shape. As such, an electrically shielding barrier is provided around the pickup components of the sensor 250. Accordingly, sensor performance can be increased.
In an embodiment, the voltage ring 265 may be coupled to pickup circuitry 281 on the PCB 253. The pickup circuitry 281 in
In an embodiment, the current loop 254 may be coupled to pickup circuitry 282 on the PCB 253. The pickup circuitry 282 in
In an embodiment, the pickup circuitry 281 is electrically isolated from the pickup circuitry 282. Electrically isolating the two sets of pickup circuitry 281 and 282 enables a reduction in cross-coupling between the two circuits. As such, performance of the sensor 250 may be improved. In an embodiment, the electrical isolation may be provided by a conductive strip 285 that is provided between the two sets of pickup circuitry 281 and 282. In an embodiment, the conductive strip 285 may be grounded. In some embodiments, the conductive strip 285 is electrically coupled to the guard ring 270. The conductive strip 285 may be provided on a top surface of the PCB 253. In other embodiments, vias may be provided below the strip 285 in order to extend the electrical isolation through a thickness of the PCB 253.
Referring now to
In an embodiment, the process power control module 790 may include a dual analog-to-digital (A/D) converter 741. The dual A/D converter 741 may receive a first input from a voltage sensor and a second input from a current sensor, such as a transmission line sensor 750. For example, an analog voltage signal and an analog current signal may be provided to the dual A/D converter 741. The analog voltage signal and the analog current signal may be picked up by a sensor such as the sensors described in greater detail above. For example, the sensor may include a current loop and a voltage ring. In an embodiment, the dual A/D converter 741 may have a sample rate of approximately 250 mega samples per second (MSPS) or greater. Though, it is to be appreciated that lower sampling rates are also possible in other embodiments.
In an embodiment, the converted digital signals can then be processed by a digital down converter (DDC) 742. The digital down converter may take the incoming signals and apply a low pass filter in order to obtain the desired signal. For example, in
In an embodiment, the output of the digital conversion may be provided in Cartesian coordinates. Additionally, the output may be split into two branches. A first branch may pass directly to a transmission line scaling matrix 764, and the second branch may pass through a digital phase lock loop dPLL 766. The first branch may remain in Cartesian coordinates and propagate a signal at a first rate R. The second branch may start in Cartesian coordinates and propagate a signal at a second rate nR. In an embodiment, the second rate nR may be greater than the first rate R. For example, the second rate nR may be four or more times greater than the first rate R.
In an embodiment, the second branch provides the Cartesian coordinates to a Polar Phase converter block. The frequency can then be fed to the scaling matrix 764 and/or fed back to the DDC 742 in order to provide feedback to the digital down conversion process in order to improve measurement accuracy of the system.
In the description of
Referring now to
In an embodiment, process 480 may begin with operation 481, which comprises picking up an analog voltage signal and an analog current signal with a transmission line sensor. In an embodiment, the analog voltage signal and the analog current signal may be detected with a sensor that includes a voltage ring and a current loop, such as the embodiments described in greater detail above. In an embodiment, a single sensor may be located before or after an impedance matching network. In other embodiments, multiple sensors may be used (e.g., before and/or after the impedance matching network).
In an embodiment, the process 480 may continue with operation 482, which comprises digitizing the analog voltage signal and the analog current signal into a digital voltage signal and a digital current signal. For example, the digitation process may be implemented by an A/D converter. A dual A/D converter may be used to digitize both signals in some embodiments. In a particular embodiment, the AD converter may have a sample rate of approximately 250 MSPS or greater.
In an embodiment, the process 480 may continue with operation 483, which comprises down converting the digital signals to provide a first signal with a first rate and a second signal with a second rate. In an embodiment, the first rate (i.e., a first signal rate) is less than the second rate (i.e., a second signal rate). In a particular embodiment, the second rate may be approximately four times the first signal rate. In other embodiments, the second rate may be approximately any integer multiple of the first signal rate. The down converting may be implemented with a DDC such as the DDC 342 described in greater detail above.
In an embodiment, the process 480 may continue with operation 484, which comprises extracting phase V (θV) and phase I (θI) from the second signal. For example, the second signal may be fed to a frequency detector, such as the one described in greater detail above. In such an embodiment, the desired signal maybe represented in Cartesian form, and is translated to Polar form to derive a time-varying phasor.
In an embodiment, the process 480 may continue with operation 485, which comprises multiplying the derivative of the phases by 2n to convert rotational phase units to revolutions. The multiplication operation may be implemented by a functional block that is configured to do the frequency translation.
In an embodiment, the detected frequency of the desired signal may be fed forward to a scaling matrix. The first signal may also be fed to the scaling matrix. In other embodiments, the detected frequency may optionally be routed back to the DDC as a feedback input in order to improve the accuracy of the frequency detection.
Accordingly, embodiments described herein allow for real-time process control and monitoring that utilizes knowledge of the frequency of the process power. The method of detection and retrieval described herein allow for a high degree of accuracy with minimal group delay, and optimal control. Additionally, the scheme described herein is autonomous and does not require messaging or information passing from other systems or subsystems.
Referring now to
In an embodiment, a pair of transmission line sensors (TL sensor port 1 and TL sensor port 2) provide signals into the processing system. The signal from TL sensor port 1 is A1 sin(ωcnTs+ϕ1), and the signal from TL sensor port 2 is A2 sin(ωcnTs+ϕ2). The signals are routed to dual A/D converters 561A and 561B. The dual A/D converters 561A and 561B are part of a digital down conversion block. Additionally, the signals may be routed to dual A/D converters 561C and 561D which are part of a frequency digital phase lock loop (dPLL) block.
In an embodiment, the dual A/D converters 561A and 561B may each provide an imaginary portion of the signal (Q) and a real portion of the signal (I) to a digital down converter (DDC) 5621. The DDCs 5621 may have a sample rate R. The DDCs 5621 may combine the imaginary Q and real I signals into a complex signal. For example, a first complex signal may take the form of a1ej(ωRTs+ϕ1) and a second complex signal may take the form of a2ej(ωRTs+ϕ2). In an embodiment, scaling factors (e.g., K21, K11, K12, and K22) may then be multiplied against the complex signals at multipliers 563. The results of the multiplication may then be fed to a transmission line scaling module 564. The transmission line scaling module 564 is a linear combination that takes the two complex signals and outputs a set of four outputs. For example, the four outputs may include voltage VL, power forward PF, power reflected PR, and current IL.
In an embodiment, the frequency dPLL block begins with dual A/D converters 561C and 561D. Similar to the dual A/D converters 561A and 561B, the dual A/D converters 561C and 561D provide a real (I) signal and an imaginary signal (Q). The signals I and Q can then be processed by DDCs 5622. The DDCs 5622 may have a sample rate that is different than the sample rate of the DDCs 5621. For example, the sample rate may be 2−1R in some embodiments. The DDCs output signals that are combined into a complex signal. The complex signals may take the form of a11ej(ωn2{circumflex over ( )}(-k)RTs) and a22ej(ωn2{circumflex over ( )}(-k)RTs). In an embodiment, the complex signals may then be converted into a polar form with Cartesian to polar converters 565. The output polar signals may take the form θ1(n2−kRTs) and θ2(n2−kRTs). The polar signals may then be processed by a frequency dPLL module 566. The frequency dPLL module 566 may output a frequency ω.
In an embodiment, the output from the frequency dPLL module 566 may be fed to direct digital synthesis (DDS) blocks 567. In an embodiment, the DDS blocks 567 output conjugate modifiers ej(ωnTs) or e−j(ωnTs) that are fed back to the dual A/D converters 561. In the bottom dPLL block, the modifiers may be conjugate pairs. The use of conjugate pairs prevents the dPLL from incorrectly locking to an in-band frequency.
Referring now to
In an embodiment, the complex signals may be converted into a polar form with a Cartesian to polar conversion module 665. The converted signals may have the form θ1(nRTs) and θ2(nRTs). The polar form signals may then be used to extract frequency values ω1 and ω2. The frequency values may then be fed into a DDS 667 in order to provide an output modifier ej(ωnTs) that is provided to the dual A/D converters 661.
In an embodiment, the complex signals may also be passed through filters 668. The filters 668 may be finite impulse response (FIR) filters. In a particular embodiment, the filters 668 may be equalizing FIR filters. The outputs of the filters 668 may be fed to a transmission line scaling module 664. The transmission line scaling module 664 includes a linear combination that takes the two complex signals and outputs a set of four outputs. For example, the four outputs may include load voltage VL, power forward PF, power reflected PR, and load current IL. Additionally, the scaling matrix may produce direct transfer from raw DDC complex quantities to incident voltage Vi, incident current Ii, reflected voltage Vr, and reflected current Ir.
Referring now to
In some embodiments, the frequency dPLL 766 may be shared between threads. For example, the frequency dPLL 766 for the second transmission line sensor 750 may be shared by the third transmission line sensor 750. That is, a single frequency dPLL 766 may be coupled to a pair of DDCs 742 and a pair of transmission line scaling modules 764.
In an embodiment, the transmission line scaling modules 764 may be communicatively coupled to a real time processor 791. The real time processor 791 may be communicatively coupled to a memory (e.g., DRAM 793) and a messaging controller 792.
Referring now to
Computer system 800 may include a computer program product, or software 822, having a non-transitory machine-readable medium having stored thereon instructions, which may be used to program computer system 800 (or other electronic devices) to perform a process according to embodiments. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.
In an embodiment, computer system 800 includes a system processor 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 818 (e.g., a data storage device), which communicate with each other via a bus 830.
System processor 802 represents one or more general-purpose processing devices such as a microsystem processor, central processing unit, or the like. More particularly, the system processor may be a complex instruction set computing (CISC) microsystem processor, reduced instruction set computing (RISC) microsystem processor, very long instruction word (VLIW) microsystem processor, a system processor implementing other instruction sets, or system processors implementing a combination of instruction sets. System processor 802 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal system processor (DSP), network system processor, or the like. System processor 802 is configured to execute the processing logic 826 for performing the operations described herein.
The computer system 800 may further include a system network interface device 808 for communicating with other devices or machines. The computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), and a signal generation device 816 (e.g., a speaker).
The secondary memory 818 may include a machine-accessible storage medium 832 (or more specifically a computer-readable storage medium) on which is stored one or more sets of instructions (e.g., software 822) embodying any one or more of the methodologies or functions described herein. The software 822 may also reside, completely or at least partially, within the main memory 804 and/or within the system processor 802 during execution thereof by the computer system 800, the main memory 804 and the system processor 802 also constituting machine-readable storage media. The software 822 may further be transmitted or received over a network 820 via the system network interface device 808. In an embodiment, the network interface device 808 may operate using RF coupling, optical coupling, acoustic coupling, or inductive coupling.
While the machine-accessible storage medium 832 is shown in an exemplary embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.
In the foregoing specification, specific exemplary embodiments have been described. It will be evident that various modifications may be made thereto without departing from the scope of the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
