Patent Application
20240194602
Generally, semiconductor devices can include a plurality of circuits which form an integrated circuit fabricated on a substrate. A complex network of signal paths can be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals can include the formation of multilevel or multilayered schemes (e.g., single or dual damascene wiring structures) during the back-end-of-line (BEOL) phase of manufacturing. Within an interconnect structure, conductive vias can run perpendicular to the substrate and conductive lines can run parallel to the substrate.
Illustrative embodiments of the present application include techniques for use in semiconductor manufacture. In an illustrative embodiment, a semiconductor structure comprises a lattice matched etch stop layer disposed on a silicon substrate layer. The lattice matched etch stop layer is lattice matched to the silicon substrate layer. The semiconductor structure further comprises an epitaxial silicon layer disposed on the lattice matched etch stop layer, a front-end-of-the-line device layer disposed on the epitaxial silicon layer, a back-end-of-the-line device layer disposed on the front-end-of-the-line device layer, and a carrier wafer disposed on the back-end-of-the-line device layer.
According to another exemplary embodiment, a semiconductor structure comprises an epitaxial silicon layer free of crystalline defects, and a backside power distribution network disposed on the epitaxial silicon layer.
According to yet another exemplary embodiment, a method, comprises forming a lattice matched etch stop layer on a silicon substrate layer, epitaxially growing a silicon layer on the lattice matched etch stop layer, forming a front-end-of-the-line device layer on the epitaxially grown silicon layer, forming a back-end-of-the-line device layer on the front-end-of-the-line device layer, and forming a carrier wafer on the back-end-of-the-line device layer to form a semiconductor structure. The lattice matched etch stop layer is lattice matched to the silicon substrate layer.
These and other exemplary embodiments will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
Exemplary embodiments will be described below in more detail, with reference to the accompanying drawings, of which:
This disclosure relates generally to semiconductor devices, and more particularly to a backside power distribution network (BSPDN) substrate formation using a lattice matched etch stop layer on a silicon substrate and methods for their fabrication. However, it is to be understood that embodiments of the invention are not limited to the illustrative methods, apparatus, systems and devices but instead are more broadly applicable to other suitable methods, apparatus, systems and devices.
It is to be understood that the various features shown in the accompanying drawings are schematic illustrations that are not necessarily drawn to scale. Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each of the drawings. Further, the terms “exemplary” and “illustrative” as used herein mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “illustrative” is not to be construed as preferred or advantageous over other embodiments or designs.
Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description. It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present, such as 1% or less than the stated amount.
Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment. The term “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g., interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
As used herein, “height” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional views measured from a bottom surface to a top surface of the element, and/or measured with respect to a surface on which the element is located. Conversely, a “depth” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional views measured from a top surface to a bottom surface of the element. Terms such as “thick”, “thickness”, “thin” or derivatives thereof may be used in place of “height” where indicated.
As used herein, “width” or “length” refers to a size of an element (e.g., a layer, trench, hole, opening, etc.) in the drawings measured from a side surface to an opposite surface of the element. Terms such as “thick”, “thickness”, “thin” or derivatives thereof may be used in place of “width” or “length” where indicated.
In the IC chip fabrication industry, there are three sections referred to in a typical IC chip build: front-end-of-line (FEOL), back-end-of-line (BEOL), and the section that connects those two together, the middle-of-line (MOL). The FEOL is made up of the semiconductor devices, e.g., transistors, the BEOL is made up of interconnects and wiring, and the MOL is an interconnect between the FEOL and BEOL that includes material to prevent the diffusion of BEOL metals to FEOL devices. Accordingly, illustrative embodiments described herein may be directed to BEOL semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) become interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL, part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.
Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.
Various techniques may be used to remove a silicon substrate when forming a backside power distribution network. For example, silicon germanium (SiGe) may be used as an etch stop layer. However, a sufficiently thick SiGe layer is necessary and exceeds the critical thickness of the SiGe, thereby leading to the generation of defect. If the thickness of the SiGe is below the critical thickness then the SiGe will not be thick enough to compensate for the silicon thickness variation caused by wafer grinding. In addition, there is limited etch selectivity between the SiGe etch stop layer and silicon substrate. As another example, using highly n-doped silicon as an alternative has similar issues. In particular, the high doping levels needed to achieve a desired etch selectivity will lead to defects in the crystalline material. In addition, even if one could accomplish low defectivity using, for example, epitaxial Si:P with 2−3×1021 cm−3 doping, the etch selectivity between the two materials is not sufficient when a relatively thick silicon layer (multiple microns) needs to be removed.
Accordingly, illustrative embodiments described herein overcome the foregoing drawbacks. Advantages of the illustrative embodiments include that deposition of a layer of a lattice matched etch stop layer such as a relatively thin layer of an epitaxial oxide onto a silicon substrate using, for example, molecular beam epitaxy (MBE), is a straight forward process and allows for subsequent growth of a device quality epitaxial silicon such as a relatively thick layer of device quality epitaxial silicon. Other advantages include that the lattice matched etch stop layer exhibits a superb etch selectivity against crystalline silicon, and can be made to have the same lattice constant as the silicon substrate, resulting in relatively little to no crystalline defects in the subsequently grown silicon. These defects can act as traps and affect, for example, the turn-on of the device (transistor), as well as the stability and mobility of the device. Thus, the illustrative embodiments allow for an improved semiconductor structure.
Referring now to the drawings in which like numerals represent the same of similar elements,
In illustrative embodiments, a lattice constant of the mixed rare earth oxide may be twice a lattice constant of the silicon substrate. In illustrative embodiments, a lattice constant of the mixed rare earth oxide may be twice a lattice constant of silicon. In illustrative embodiments, a mixed rare earth material includes oxides which can be used herein in terms of looking at the lattice constants and matching them so that they could match silicon. Suitable mixed rare earth oxides include, for example, samarium (e.g., (SmxY1-x)2O3), cerium (CexY1-x)2O3), gadolinium (LaxGd1-x)2O3), gadolinium oxide and europium oxide (e.g., (GdxEu1-x)2O3), etc.
In illustrative embodiments, the mixed rare earth oxide comprises a ternary mixed rare earth oxide. In illustrative embodiments, the mixed rare earth oxide comprises a rare earth cubic ternary oxide. In illustrative embodiments, the mixed rare earth oxide will have a majority amount of one rare earth oxide compound, to ensure the resulting ternary mixed rare earth oxide formed on the silicon substrate has a cubic lattice, and will also have a minority amount of another rare earth oxide. A majority amount as used herein should be understood to mean at least about 55% of the ternary mixed rare earth oxide compound. A minority amount as used herein should be understood to mean no more than about 45% of the ternary mixed rare earth oxide compound. Examples of the majority compounds include, but are not limited to, Eu2O3, Gd2O3, Tb2O3, Dy2O3, Ho2O3, Er2O3, Tm2O3, Yb2O3, Lu2O3, Y2O3, etc. Examples of the minority compounds include, but are not limited to, La2O3—, Ce2O3, Pr2O3—, Nd2O3, Pm2O3—, Sm2O3, etc.
To be lattice matched with silicon substrate 102, the ternary mixed rare earth oxide should have a substantially exact percentage of each compound. By substantially exact percentage of each compound means an exact percentage plus or minus one percent. Representative examples of rare earth oxides matching silicon include La—Y—O with 33% lanthanum, 68.8% gadolinium oxide with 31.2% europium oxide, 91.3% gadolinium oxide with 8.7% lanthanum oxide, 58.5% erbium oxide with 41.2% neodymium oxide, 62.6% erbium oxide with 37.4% lanthanum oxide, etc.
The lattice matched etch stop layer 104 can be formed using conventional epitaxial growth techniques such as molecular beam epitaxy (MBE), so that an epitaxial film of good quality may be grown on silicon substrate 102 by depositing the mixed rare earth material such as (LaxY1-x)2O3. In an illustrative embodiment, lattice matched etch stop layer 104 can have a thickness ranging from about 10 nanometers (nm) to about 500. In an illustrative embodiment, lattice matched etch stop layer 104 can have a thickness ranging from about 50 nm to about 150 nm.
In one embodiment, the lattice matched etch stop layer 104 has a different etch rate than the silicon substrate 102. In another embodiment, the lattice matched etch stop layer 104 has a different polishing rate than the silicon substrate 102.
BEOL device layer 110 is then formed on FEOL device layer 108. BEOL device layer 110 can include, for example, a lower frontside BEOL layer containing various BEOL interconnect structures including, for example, insulating layers (dielectrics), metal levels, and/or via levels. In illustrative embodiments, the lower frontside BEOL layer may only be used for signal routing, without any power distribution network.
BEOL device layer 110 can also include, for example, an upper frontside BEOL layer containing various BEOL interconnect structures including, for example, insulating layers (dielectrics), metal levels, via levels and bonding sites. In illustrative embodiments, the upper frontside BEOL layer may comprise only signal wiring. In illustrative embodiments, the upper frontside BEOL layer may comprise both signal wiring and wires for power delivery.
Carrier wafer 112 is then bonded to BEOL device layer 110. The carrier wafer 112 may be formed of materials similar to that of the silicon substrate 102, and may be formed over the BEOL device layer 110 using a wafer bonding process, such as dielectric-to-dielectric bonding.
Semiconductor devices and methods for forming the same in accordance with the above-described techniques can be employed in various applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
In some embodiments, the above-described techniques are used in connection with semiconductor devices that may require or otherwise utilize, for example, CMOSs, MOSFETS, and/or FinFETs. By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.
Various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either: (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
