Patent Application
20060076244
This invention relates to an electrochemical deposition process for depositing a thin film enhancement layer onto an existing ultra thin barrier layer to repair defects and enhance the barrier properties of the barrier layer. The deposited thin film enhancement layer serves as a barrier layer and as a seed layer for subsequent copper plating processes.
Metallization patterns are needed to interconnect numerous devices to form integrated circuits. For high performance ultra large scale integration (ULSI) chips, six or more metallization layers are commonly used. The number of layers is expected to increase as the industry works to decrease device dimensions and pack more devices onto integrated circuit chips.
Integrated circuit chip performance is limited by the signal propagation delay of the interconnections, also known as the “RC” delay. In order to improve circuit speed, it is important to reduce both the R (the resistance) and the C (the capacitance) associated with the interconnections. Recently, copper metallization has been introduced to replace aluminum metallization in integrated circuit fabrication because copper has both a lower resistivity and a higher current carrying capacity than aluminum.
Copper metallization requires different processing than aluminum metallization. Instead of metal deposition followed by patterning as used in forming aluminum interconnects, copper interconnects usually are formed using a damascene process. In a damascene process, the conductor pattern is first etched into the dielectric material. Then, the etched patterns are filled with copper. Excess copper then is removed from over the field using a chemical mechanical polishing (“CMP”) step. A via-hole is used to connect different metallization layers formed in the integrated circuit chip. When the conductor line pattern and via-hole pattern are filled and polished separately, the process is generally referred to as a “single damascene” process. When both the conductor line and the via-hole pattern are filled at the same time, the process is generally referred to as a “dual damascene” process.
In the known damascene process, a barrier layer and then a seed layer are deposited over the patterned dielectric layer surface before copper is introduced. The barrier layer is needed to prevent the copper from diffusing into the device region. When in contact with silicon, copper spoils the silicon device operation. Usually, thin refractory metals or metal nitrides are selected for the barrier layer. Representative barrier layer materials include tantalum, tantalum nitride, tungsten, tungsten nitride, titanium and titanium nitride. The seed layer is needed to provide the conductivity for the electrochemical deposition reaction and to provide nucleation sites for the subsequent copper electroplating. Usually, a thin copper layer is deposited over the barrier layer to serve as the seed layer.
One of the most important requirements for the damascene process for copper is to have the deposited copper perfectly fill the small geometries of etched lines or trenches and holes with high aspect ratios (calculated as depth divided by width). Electroplating processes are generally used to deposit copper because such processes have better gap filling capability as compared to physical vapor deposition (“PVD”) or chemical vapor deposition (“CVD”). Because electrochemical copper deposition processes can deposit more copper inside small trenches than outside the trenches, they are frequently called “super-filling.”
The PVD techniques include, for example, various evaporation and sputtering techniques, such as DC and/or RF plasma sputtering, bias sputtering, magnetron sputtering, ion plating, or ionized metal plasma sputtering. PVD processes generally produce non-conformal deposition due to their anisotropic and directional nature. The CVD techniques include, for example, thermal CVD, plasma enhanced CVD, low pressure CVD, high pressure CVD, and metal-organo CVD. CVD processes most frequently produce conformal deposition with substantially uniform thickness over the entire surface, including over the field and the bottom and sidewall surfaces of the openings.
Currently, the barrier and seed layers are deposited primarily by PVD processes, such as sputtering and ionized sputtering. Frequently, the barrier and seed layers are deposited sequentially in two different vacuum chambers without breaking vacuum to avoid surface contamination. The critical factor in such deposition processes is the film thickness inside the etched patterns, particularly on the sidewall and bottom of etched lines or trenches and via holes. The PVD processes commonly form thinner film layers in these etched patterns than over the flat field region of the dielectric material. The step coverage of these layers has been problematic. The films must be continuous and defect free. A void or defect in the barrier layer will compromise the integrity of the device. A void or defect in the seed layer will lead to a void or defect in the plated copper film.
To improve step coverage, CVD processes have been tried for depositing the barrier and seed layers. The CVD processes have not yielded better results than the PVD processes, and CVD processes are more expensive. Copper seed layers deposited by CVD processes usually have poor adhesion, higher impurities and poor crystal orientation, leading to problems when additional copper is electrochemically deposited over such seed layers. Sometimes PVD is used in conjunction with CVD, such that a separate copper seed layer is deposited by PVD processing over a copper seed layer deposited by CVD, further adding to the expense for CVD processing. Accordingly, PVD processing for barrier and seed layers for copper interconnects has remained preferred despite noted difficulties with step coverage.
Improvements to PVD deposition technology may not suffice to solve problems with film coverage for the barrier layers and seed layers deposited by PVD. As device dimensions continue to decrease, in the future the barrier film layer on the trench sidewall will need to be less than 10 nanometers. Combined technologies may be required to meet the more rigorous requirements.
U.S. Pat. No. 6,136,707 teaches a method of combining a first copper seed layer formed by CVD with a second copper seed layer formed by PVD. U.S. Pat. No. 6,197,181 discloses a method of combining a first copper seed layer electrolytically deposited from an alkaline plating solution with a second copper seed layer formed by PVD. Both of these patents thus require additional processing steps to achieve better PVD copper seed layer adhesion. However, the methods disclosed in these patents do not solve the problems caused by either a defective barrier layer or a poor interface between the barrier layer and the copper seed layer.
Accordingly, the industry seeks better methods for electrochemically depositing copper into high aspect ratio holes and trenches.
The invention comprises processes and apparatus for applying a metal to a microelectronic workpiece where the microelectronic workpiece includes a surface in which are disposed one or more micro-recessed structures. Most commonly, the microelectronic workpiece is a semiconductor wafer, such as a silicon or gallium arsenide semiconductor wafer. Preferably, the metal is copper applied to form metallization layers in trenches or holes or vias or other structures in the semiconductor wafer using a damascene or dual damascene process.
In the process according to the invention, the steps comprise:
Preferably, the enhancement layer is formed to a thickness of 100 Å or less, most preferably from 10 Å to 100 Å, using an electrochemical deposition process, such as an electroless or an electroplating process. Alternatively, the enhancement layer may be formed using a CVD or PVD process.
In one embodiment, the enhancement layer is formed from a copper alloy, such as Cu—Al, Cu—Mg and/or Cu—Zn. In another embodiment, the enhancement layer is formed from a binary alloy composition, such as Co—P, or a tertiary alloy composition, such as Co—W—P.
The enhancement layer conformally covers the barrier layer, even where the barrier layer has seams, discontinuities or grain boundary defects. For a silicon semiconductor wafer, the barrier layer may be titanium, titanium nitride, or other known barrier layer materials. The enhancement layer is conductive sufficient to permit deposition of a metal, preferably copper, thereon. Thereafter, excess metal is removed from the field surface, such as by chemical mechanical polishing. The deposited metal remains within the microelectronic structure forming the desired interconnect or metallization layer.
In a further embodiment, the process steps comprise:
In this alternate embodiment, the seed layer may comprise a further layer of a metal alloy or may comprise a layer of the metal intended to be deposited in the microelectronic structure. Thus, the seed layer may be a copper alloy, a binary alloy such as Co—P, or a tertiary alloy such as Co—W—P. The seed layer is formed with a thickness preferably from 50 Å to 500 Å.
The damascene processes may be carried out in a manufacturing line including a plurality of apparatus for the manufacture of microelectronic circuits or components, where one or more apparatus of the plurality of apparatus are used to apply interconnect metallization in a damascene process to a surface of a microelectronic workpiece used to form the microelectronic circuits or components. The microelectronic workpiece preferably is a silicon or gallium arsenide semiconductor wafer into which has been formed holes or trenches or vias suited for metallization to form microelectronic circuits or components. In such case, the one or more apparatus comprise:
means for applying a barrier layer to a surface of the microelectronic workpiece using a first deposition process, wherein the barrier layer is generally unsuitable for bulk electrochemical deposition of the interconnect metallization;
means for applying an enhancement layer over the barrier layer using a second deposition process, wherein the enhancement layer formed from an alloy composition that is generally suitable for subsequent electrochemical application of a metal to a predetermined thickness representing a bulk portion of the interconnect metallization; and
means for electrochemical application of a metal over the enhancement layer.
Preferably, the means for applying the enhancement layer is equipment for electrochemical deposition, such as equipment for electroless or electroplating processing. Alternatively, the means for applying the enhancement layer may be equipment for CVD or PVD processing. The means for applying the enhancement layer is capable of applying the enhancement layer conformally over the barrier layer to a thickness of 100 Å or less, preferably from 10 Å to 100 Å thick. The enhancement layer preferably is formed from a metal alloy, such as a copper alloy like Cu—Al, Cu—Mg and/or Cu—Zn, a binary alloy such as Co—P, or a tertiary alloy such as Co—W—P, or possibly even from mixtures of such alloys.
The means for electrochemical application of a metal over the enhancement layer is capable of applying copper as the metal in the damascene process. Once the copper is introduced into the metallization layers or microelectronic structures, a means is provided for removing a portion of the copper metal from the field surface of the microelectronic workpiece. Preferably, the means for removing a portion of the copper metal comprises chemical mechanical polishing equipment.
The apparatus may include a first chamber for applying the barrier layer and a second chamber for applying the enhancement layer. In addition, the optional additional seed layer and the copper metallization layer may be deposited onto the workpiece while the workpiece is in the second chamber used to apply the enhancement layer. Thus, electrochemical deposition of the enhancement layer, the optional seed layer, and the copper metal may be carried out in a single chamber in the apparatus.
The invention will be more fully understood by referring to the detailed specification and claims taken in connection with the following drawings.
Referring first to
The surface of the dielectric material 10 is coated with a thin barrier layer 14, preferably using a PVD process although a CVD process may also be used. The barrier layer generally may be a thin refractory metal or metal nitride. Representative barrier layer materials include tantalum, tantalum nitride, tantalum silicon nitride, tungsten, tungsten nitride, tungsten silicon nitride, titanium, titanium nitride and titanium silicon nitride, and other tertiary nitrides.
As shown in
Referring next to
Most of the failures in the barrier layer relate to copper diffusion at the grain boundaries because grain boundary diffusion is much faster than the diffusion through the bulk. It has been proposed to “stuff” the grain boundaries to improve the barrier properties of the barrier layer with grain boundary defects. For example, TiN barrier layers are usually annealed in an oxygen atmosphere to “stuff” the oxygen at the grain boundaries. Another method to reduce the diffusion at the grain boundaries is to add other materials to the original barrier metal to form alloys. The added material usually concentrates at the grain boundaries (also called segregation). Alloy composition can be adjusted to satisfy different requirements. For example, copper alloys, such as Cu—Sn, Cu—Zn, Cu—Mg or Cu—Al can be used as diffusion barriers for copper. The added metal in the alloy usually concentrates on the grain boundary surface or free surface and prevents the copper atoms from moving. Cu—Sn and Cu—Zn are known to slow the corrosion of Cu in air by preventing oxygen diffusion. Recently, Cu—Al has been studied as a diffusion barrier for copper because Al tends to segregate out at the grain boundaries and at the surface.
One of the most difficult issues in depositing a seed layer over the barrier layer is getting good adhesion between the original barrier layer and the seed layer deposited thereon. Plated copper adheres poorly to the barrier layer surface. That is why the seed enhancement layer described in U.S. Pat. No. 6,197,181 was not directly deposited on the barrier layer, but was deposited onto a PVD deposited copper seed layer. A CVD copper seed layer directly deposited onto the barrier layer also has poor adhesion, and a PVD copper seed layer is often used to improve the adhesion of the CVD copper seed layer.
According to the invention, as shown in
The barrier enhancement layer 24 is intended both to enhance the performance of the diffusion barrier layer and to serve as a seed layer for subsequent copper plating processing. Thus, depositing the barrier enhancement layer can eliminate the need for a separate copper seed layer.
The barrier enhancement layer is formed from a conductive metal that will adhere to the barrier layer and will also permit subsequent copper plating. Preferably, the barrier enhancement layer is formed from a binary or tertiary metal alloy material selected from one of the following: cobalt-phosphorous (Co—P) or cobalt-tungsten-phosphorous (Co—W—P); or is formed from a copper alloy, such as Cu—Al, Cu—Mg, Cu—Zn and/or Cu—Sn, or possibly mixtures of such alloys.
Preferably, the alloy material deposited as the barrier enhancement layer is Co—W—P. Electrochemical deposition processes for Co—W—P are described in detail in U.S. Pat. No. 5,695,810, which description is incorporated herein by reference. Typical deposition temperatures for this alloy range from room temperature to 90° C. However, at 90° C., the loss of aqueous electrolyte by evaporation may be excessive, such that a lower temperature, such as 75° C. is preferred. The thickness of the deposited Co—W—P layer can be controlled by controlling the deposition time and temperature for a given deposition chemistry. Co—W—P alloy material deposits over a TiN barrier layer at a rate of about 100 Å to 200 Å per minute at 75° C. in an electrochemical deposition process as graphically illustrated in
The electrochemical deposition processes are preferred for depositing the barrier enhancement layer. Such processes are compatible with the standard copper plating process and equipment already in use in copper interconnect fabrication. The new electrochemical deposition process for the barrier enhancement layer therefore can readily be integrated with existing plating tools by installing a new process chamber in the existing system. A suitable integrated tool configuration is shown in
After the barrier enhancement layer 24 is applied over the barrier layer 16, the etched pattern is filled with electroplated copper as shown in
In an alternate embodiment, two separate layers may be deposited onto the barrier layer. As shown in
A single barrier enhancement layer was deposited over a TiN barrier layer. The TiN barrier layer was sputtered over a silicon dioxide dielectric material. The TiN barrier layer surface was then cleaned and rinsed. A thin electroless Co—W—P layer was then deposited over the TiN barrier layer. The electrolyte used for deposition consisted of:
The deposition temperature was 75° C. and deposition time was about one minute. The deposited film (about 100 Å) had good diffusion properties and was used successfully as the seed layer for subsequent copper plating.
A sputtered tantalum barrier layer was applied to the silicon dioxide dielectric substrate. Because direct deposition of Co—W—P onto tantalum is known to have marginal adhesion, a thin layer (about 100 Å) of cobalt was sputtered onto the tantalum surface. Then, a layer of Co—W—P was deposited by electroless deposition onto the sputtered Co surface at 75° C. for about one minute. The combined film (approximately 200 Å) resulted in satisfactory adhesion. Copper was then directly electroplated onto the Co—W—P layer. In this example, the Co layer was the barrier enhancement layer and the Co—W—P was the seed layer for copper plating.
This example illustrates that according to the second embodiment of the invention: (1) two different layers may be used—a barrier enhancement layer and a seed layer; and (2) different deposition techniques were used for depositing the barrier enhancement layer and the seed layer.
The invention has been illustrated by detailed description and examples of the preferred embodiments. Various changes in form and detail will be within the skill of persons skilled in the art. Therefore, the invention must be measured by the claims and not by the description of the examples or the preferred embodiments.
This application claims priority from U.S. Provisional Application Ser. No. 60/298,138, filed Jul. 25, 2001.
| Number | Date | Country | |
|---|---|---|---|
| 60298138 | Jun 2001 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10172767 | Jun 2002 | US |
| Child | 11289998 | Nov 2005 | US |
