Patent Application
20190206753
Embodiments relate to semiconductor devices. More particularly, the embodiments relate to packaging semiconductor devices with a bicontinuous porous ceramic/polymer composite implemented as a die backside stiffener and a picture frame stiffener.
Packaging semiconductor devices, such as silicon wafers or dies, present several problems. One such problem is dies generate package warpage. Package warpage is typically generated as a result of a coefficient of thermal expansion (CTE) mismatch between the die and a substrate.
As an effective approach, packaging solutions typically use an epoxy mold compound and/or a stiffener comprising metallic materials (e.g., a stainless steel stiffner) to reduce package warpage. This presents additional problems for packaging solutions, especially for the current stiffener applications that include die backside stiffeners and picture frame stiffeners.
Epoxy mold compound typically achieves a low CTE by progressively adding fillers, which increases the overall viscosity and thus leads to various processing concerns. Composite materials, such as an epoxy mold compound, are commonly used in traditional semiconductor packaging industries to control the warpage of thin die packages/dies. As such, there are various processing concerns when using thin die packages with epoxy mold compounds, as these thin die packages are already predisposed to have high warpage both at room and reflow temperatures due to the CTE mismatch between the die and substrate and the low stiffness between the die and substrate.
Meanwhile, die backside stainless steel stiffeners have significant prohibitive challenges when applied on a singulated unit level. When the die backside stainless steel stiffeners are processed on a wafer level, the singulation of the wafer with stainless steel leads to burrs, respectively interfering with further downstream processing. Additionally, die backside stainless steel stiffener requires dispensing an adhesive layer between the die and the stiffener which leads to processing challenges, such as increased z-height, meeting tight keep-out-zones (KOZs), dispense optimization, and increased time and tooling/assembly costs. The required adhesive layer reduces the mitigation of the package warpage due to the weak mechanical coupling between the die and the die backside stainless steel stiffener, especially at high temperatures. Another problem with this stainless steel stiffener is that the adhesive layer acts as a thermal bottleneck (due to its low conductivity), which further limits the application of the die backside stainless steel stiffener to low-power semiconductor devices.
Embodiments described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar features. Furthermore, some conventional details have been omitted so as not to obscure from the inventive concepts described herein.
Described herein are systems that include a semiconductor package with a bicontinuous ceramic/polymer composite (BCC) (also referred to as a bicontinuous porous ceramic/polymer composite) implemented as a die backside stiffener and/or a picture frame stiffener, and methods of forming such semiconductor packages. Specifically, a semiconductor package (e.g., flip-chip packages) is described below and methods of forming such semiconductor package using BCC employed as a stiffener to provide thermal management and warpage control solutions both at room temperatures and reflow temperatures. The BCC stiffeners described herein can be employed as a picture frame stiffener surrounding the perimeter of the package and/or a die backside stiffener either at the wafer level or the unit level (after die attach).
In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present embodiments may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present embodiments may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present embodiments, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
As used herein the terms “top,” “bottom,” “upper,” “lower,” “lowermost,” and “uppermost” when used in relationship to one or more elements are intended to convey a relative rather than absolute physical configuration. Thus, an element described as an “uppermost element” or a “top element” in a device may instead form the “lowermost element” or “bottom element” in the device when the device is inverted. Similarly, an element described as the “lowermost element” or “bottom element” in the device may instead form the “uppermost element” or “top element” in the device when the device is inverted.
For some embodiments, the BCC semiconductor packages described herein include BCCs used as stiffeners to enable solutions in semiconductor packaging applications (e.g., controlling/mitigating package level warpage). As used herein, a “BCC” refers to a highly porous ceramic material impregnated (or connected) with a curing polymeric resin which can be used in semiconductor packages as an improvement, for example, to epoxy mold compound and/or a stainless steel stiffener. As used herein, a “BCC semiconductor package” refers to a semiconductor package/substrate having a bicontinuous porous ceramic/polymer implemented as a die backside stiffener on a die and/or a picture frame stiffener surrounding a die.
According to some embodiments, the connected porous ceramic structure (and/or porous metal structure) helps to provide very high modulus, high strength, and ultra-low (but tunable) CTE. Additionally, after the curing process, these embodiments allow the polymeric resin to offer a continuous soft matrix while providing toughness to the brittle ceramic matrix. The polymeric resin further facilitates attachment/bonding to various substrates, including polymeric substrates, silicon die backsides, etc.
Embodiments of the BCC semiconductor package enable several advantages for packaging solutions as compared to typically used epoxy mold compound and stainless steel stiffeners. For example, as described below, these embodiments provide improvements in mechanical properties such as mitigating CTE mismatch, optimizing modulus, and controlling the properties of the combined materials. Unlike epoxy mold compounds, the BCCs rely on the connected network/matrix of the ceramic materials to control and optimize the overall CTE of the composite.
Meanwhile, in comparison with stainless steel stiffeners, the BCC described herein enhance the bonding mechanism/process in semiconductor packaging (e.g., dispensing/disposing an adhesive layer is not required). Accordingly, in these embodiments, the BCC semiconductor package can have (i) a polymer resin disposed directly on the porous ceramic after placement (where the capillary forces in the ceramic may limit the resin flow within the ceramic only), and/or (ii) a pre-polymerized epoxy resin already impregnated in the porous ceramic which can soften upon heating for bonding and can be successively cured later.
One additional advantage is that the BCC can be processed on a unit level but also on a wafer level to provide die backside stiffener. As such, the BCC can be applied at the wafer level and mitigate burrs during the singulation of the wafer which reduces downstream processing. For some embodiments, the BCC may be used as a thermal solution for some packages—in addition to a stiffener solution—by utilizing a thermally conductive porous ceramic (and/or metal), which may form a continuous thermal path between the die on the package and the environment above the ceramic composite.
The embodiments illustrated below use BCC which may include a bicontinuous composite of a porous ceramic, a curable polymeric resin, and/or a metal. One of the main advantages of a porous ceramic is offering a connected rigid matrix which has a reduced CTE and a high bending stiffness. Additionally, to overcome highly porous ceramic materials that can be brittle, the embodiments of the BCC impregnate the highly porous ceramic with a polymeric resin. As noted above, the polymeric resin facilitates the bonding of the BCC design (e.g., a BCC die backside stiffener) on various substrates.
According to some embodiments, the final properties of the BCC can be easily tailored and optimized by selecting, for example but not limited to, the type of porous ceramic, the pore size, the pore density, and the polymeric resins. For some of these embodiments, the BCC may include one or more different materials such as, but not limited to, polymeric resins, ceramics, and metals. These embodiments facilitate a wide range of bicontinuous composite materials that can be used to enhance the modulus of the stiffener. As such, the stiffener materials can be managed so that their modulus and CTE are optimized for warpage or stress reduction by controlling the final properties of the selected BCC.
For one embodiment, the BCC may include one or more polymeric resin materials such as, but not limited to, epoxies, acrylates, acrylics, nitriles, phenol formaldehydes, cross-linked polyurethanes and other engineering plastics, ultra-violet (UV) curable materials, thermally curable materials, moisture cure materials, combinations thereof, and/or any other natural and/or synthetic polymer materials. Additionally, for another embodiment, the BCC may include one or more ceramics materials such as, but not limited to, alumina, boron oxide, silica, silicon carbide, silicon nitride, zirconium oxide, titanium carbide, combinations thereof, and/or any other ceramic materials. For other embodiments, the BCC may also include one or more metallic materials such as, but not limited to, copper, aluminum, titanium, stainless steel, silver, gold, metal alloys (e.g., stainless steel), combinations thereof, and/or any metallic materials.
As shown below, a BCC may be disposed on a semiconductor package to form BCC stiffeners on at least one of a die and a substrate using one or more methods/process flows (e.g., using a resin pre-loaded in a ceramic, a polymeric resin dispensed in a liquid state, a wafer-level stiffener, etc.). For one embodiment, a process flow may form BCC stiffeners with polymeric resin dispensed in a liquid state (e.g., as shown in
For another embodiment, a process flow may form BCC stiffeners with resin pre-loaded in a ceramic (e.g., as shown in
As shown below in
As used herein, a “stiffener” (or a BCC stiffener) refers to using one or more BCC materials to act as a stiffening structure/layer on a backside of a die (i.e., a die backside stiffener) and/or to surround a die (i.e., a picture frame stiffener) for mitigating warpage on a package (or substrate). As described above, a “stiffener” may be formed using one or more BCC materials that include polymer resins, ceramics, and metals. As used herein, a “z-height” refers to a unit of measurement on the z-axis in a three-dimensional package, which is usually oriented vertically.
Referring now to
For some embodiments, the BCC stiffener 110 helps reduce package warpage by creating the BCC structure/layer on the die 105 to counteract the CTE mismatch between the die 105 and the substrate 102. The BCC stiffener 110 thus strengthens the mechanical coupling between the die 105 and the BCC stiffener 110, which enables the BCC stiffener 110 to provide a warpage control solution for the semiconductor package 100.
For one embodiment, the die 105 may include, but is not limited to, a semiconductor die, an integrated circuit, a central processing unit (CPU), a microprocessor, a platform controller hub (PCH), a memory, and a field programmable gate array (FPGA). In addition, for other embodiments, the semiconductor package 100 may include multiple dies (not shown) that need BCC stiffeners. The BCC stiffener 110 (also referred to as a BCC stiffener structure or a BCC stiffening layer) is formed/disposed directly on the backside of the die 105 to mitigate warpage both room temperatures and reflow temperatures. According to some embodiments, the BCC stiffener 110 may be formed as a bicontinuous composite of a porous ceramic and curable polymeric resin. The BCC stiffener 110 provides a connected rigid matrix with a decreased CTE, a durable bending stiffness, and an improved bond/adhesion on the die 105 (and/or any other silicon device or organic substrate). Note that, as shown below in the process flows of
In one embodiment, the underfill layer 106 is formed between the die 105 and the substrate 102. For additional embodiments, the substrate 102 may be disposed on a motherboard (not shown) or any other packaging substrate, where the substrate 102 may be electrically coupled to the motherboard using solder bumps (not shown).
According to one embodiment, the substrate 102 may include, but is not limited to, a package, a packing substrate, a printed circuit board (PCB), a high-density interconnect (HDI) board, a ceramic substrate, or any organic semiconductor packaging substrate. For one embodiment, the substrate 102 is a PCB. For one embodiment, the PCB is made of an FR-4 glass epoxy base with thin copper foil laminated on both sides (not shown). For certain embodiments, a multilayer PCB can be used, with pre-preg and copper foil (not shown) used to make additional layers. For example, the multilayer PCB may include one or more dielectric layers, where each dielectric layer can be a photosensitive dielectric layer (not shown). For some embodiments, the PCB may have holes (not shown) drilled in the PCB, and the PCB may also include conductive copper traces, metallic pads, and holes (not shown).
The substrate 102 may be electrically coupled to the die 105 via the underfill layer 106, which may include solder balls/bumps (not shown) that connect pads (not shown) on the substrate 102 and the die 105. For example, the underfill layer 106 may be used on a ball grid array (BGA), a pin grid array (PGA), a land grid array (LGA), or any other connectivity packaging. For one embodiment, the underfill layer 106 may include controlled collapse chip connection (C4) bumps that connect pads (not shown) on the die 105 and the substrate 102.
In some optional embodiments, a mold layer 130 (or an encapsulation layer) may be disposed over and around the BCC stiffener 110, the die 105, the underfill layer 106, and the substrate 102. The mold layer 130 can be used to protect the semiconductor package 100 from the environment. For one embodiment, the mold layer 130 may be cured after the deposition (or overmolding). Note that the mold layer 130 may help to protect and cover the semiconductor package 100 from humidity, photons, corrosion and damage.
For one embodiment, the mold layer 130 may include an epoxy (e.g., a soft epoxy, a stiff epoxy, opaque epoxy, etc.) with one or more filler materials. For some embodiments, the mold layer 130 may be formed with one or more encapsulant materials that are dispensed onto the semiconductor package 100 rather than using injection, compression, or transfer mold processes. Note that, as shown in
As illustrated in
The BCC stiffener 110 may be optimized/tuned based on the selected final properties of the BCC (e.g., based on the pore size, the smaller pores lead to lower CTE). Additionally, the BCC 110 may include a porous ceramic that can be easily modified in terms of the porosity and pore size to allow a polymeric resin to flow through it (where the capillary forces within the porous ceramic may drive/control the resin flow). Further, the polymeric resin viscosity of the BCC stiffener 110 can be tailored for better filling and then the resin can be subjected to cure at high temperature. Moreover, the BCC stiffener 110 helps to (i) reduce the overall assembly (e.g., by using the pick-and-place process described herein) and (ii) improve the yield of thin packages, such as mobile products (or smartphones), tablets, and wearables.
Note that the semiconductor package 100 may include fewer or additional packaging components based on the desired packaging design.
As shown in
For one embodiment, the BCC stiffener 210 is formed directly on the top surface of the substrate 202 to mitigate warpage (i.e., the package warpage of semiconductor package 200) generated by the CTE mismatch between the die 205 and the substrate 202. As noted above, thin packages (e.g., such as substrate 202) are susceptible to the problem of deformation (or warping) due to temperature cycling between lower temperatures (e.g., room temperature) and higher temperatures (e.g., those required for mass reflow of solder bumps). Accordingly, as the embodiments described herein, the final properties selected for the formation of the BCC, which is implemented as a stiffener (e.g., BCC stiffener 210), may facilitate a warpage control solution for the thin package (e.g., substrate 202) at both room and reflow temperatures to overcome the problem above.
For example, the BCC stiffener 210 may increase the stiffness of the substrate 202 and reduce the warpage that is caused by the reflow process. Furthermore, the BCC stiffener 210 may reduce the difficulty of handling a thin and flexible substrate 202 as the BCC stiffener 210 provides rigidity to the otherwise flexible substrate 202. For example, the BCC stiffener 210 may enable for the substrate 202 to be handled and processed without specialized handling equipment that may be typically needed for such thin and flexible substrates.
For some embodiments, as described above, the BCC stiffener 210 may include one or more bicontinuous composite materials, including, but not limited to, polymeric resins, porous ceramics, and/or metals. For one embodiment, the one or more materials selected for the BCC stiffener 210 may be selected in order to optimize the effective CTE and modulus for producing minimal package warpage for the semiconductor package 200.
Note that the semiconductor package 200 may include fewer or additional packaging components based on the desired packaging design.
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Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to motherboard 702. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
At least one communication chip 706 enables wireless communications for the transfer of data to and from computing device 700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. At least one communication chip 706 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 700 may include a plurality of communication chips 706. For instance, a first communication chip 706 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 706 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
Processor 704 of computing device 700 includes an integrated circuit die packaged within processor 704. Device package 710 may be, but is not limited to, a packaging substrate, a PCB, and a motherboard. Device package 710 has a waveguide launcher system with a packaging having a microstrip feedline and one or more conductive layers, and a waveguide connector having a slot-line signal converter, one or more balun structures, and one or more tapered slot launchers, and the like—or any other components from the figures described herein—of the computing device 700. Device package 710 includes a waveguide launcher system that has a power-competitive solution that can support very high data rates, e.g., over short to medium distances, which would be extremely advantageous for interconnects within server and HPC architectures and/or autonomous/self-driving vehicles, according to some embodiments. Furthermore, device package 710 includes tapered-slot launchers and connectors for exciting the waveguides which facilitates an improvement in the manufacturing and assembly of waveguide interconnect systems. Device package 710 provides a tapered-slot waveguide launcher and connector enabling a wider bandwidth for thin package substrates as the demand for miniaturization persistently increases, and a decreased sensitivity to waveguide alignment and electrical contacts.
Note that device package 710 may be a single component/device, a subset of components, and/or an entire system, as the materials, features, and components may be limited to device package 710 and/or any other component that needs a waveguide launcher system.
For certain embodiments, the integrated circuit die may be packaged with one or more devices on a package substrate that includes a thermally stable RFIC and antenna for use with wireless communications and the device package, as described herein, to reduce the z-height of the computing device. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
At least one communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. For some embodiments, the integrated circuit die of the communication chip may be packaged with one or more devices on a package substrate that includes one or more device packages, as described herein.
In the foregoing specification, embodiments have been described with reference to specific exemplary embodiments thereof. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.
The following examples pertain to further embodiments:
Example 1 is a device package, comprising a die on a substrate. The die has a front side surface that is electrically coupled to the substrate and a back side surface that is opposite from the front side surface; and a bicontinuous ceramic composite (BCC) stiffener on the back side surface of the die.
In example 2, the subject matter of example 1 can optionally include the BCC stiffener is formed with one or more materials. The one or more materials include porous ceramics, polymeric resins, and metals.
In example 3, the subject matter of any of examples 1-2 can optionally include the BCC stiffener directly coupled to the back side surface of the die without an adhesive layer.
In example 4, the subject matter of any of examples 1-3 can optionally include the die electrically coupled to the substrate with an underfill layer.
In example 5, the subject matter of any of examples 1-4 can optionally include the BCC stiffener is disposed on the die to reduce warpage based on the substrate and the die.
In example 6, the subject matter of any of examples 1-5 can optionally include a mold layer disposed over and around the BCC stiffener, the die, the underfill layer, and the substrate; and a motherboard disposed below the substrate. The motherboard is electrically coupled to the substrate.
In example 7, the subject matter of any of examples 1-6 can optionally include the BCC stiffener formed with the one or more materials using at least one of a polymeric resin in a liquid state process and a resin pre-loaded in a ceramic process.
In example 8, the subject matter of any of examples 1-7 can optionally include the BCC stiffener disposed on the die at a unit level or a wafer level.
Example 9 is a method of forming a device package, the method comprising disposing a die on a substrate. The die has a front side surface that is electrically coupled to the substrate and a back side surface that is opposite from the front side surface; and disposing a BCC stiffener on the back side surface of the die.
In example 10, the subject matter of example 9 can optionally include the BCC stiffener formed with one or more materials. The one or more materials include porous ceramics, polymeric resins, and metals.
In example 11, the subject matter of any of examples 9-10 can optionally include the BCC stiffener directly coupled to the back side surface of the die without an adhesive layer.
In example 12, the subject matter of any of examples 9-11 can optionally include the die electrically coupled to the substrate with an underfill layer. The BCC stiffener is disposed on the die to reduce warpage based on the substrate and the die.
In example 13, the subject matter of any of examples 9-12 can optionally include disposing a mold layer over and around the BCC stiffener, the die, the underfill layer, and the substrate; and a motherboard disposed below the substrate. The motherboard is electrically coupled to the substrate.
In example 14, the subject matter of any of examples 9-13 can optionally include the BCC stiffener formed with the one or more materials using at least one of a polymeric resin in a liquid state process and a resin pre-loaded in a ceramic process. The BCC stiffener is disposed on the die at a unit level or a wafer level.
In example 15, the subject matter of any of examples 9-14 can optionally include the resin pre-loaded in the ceramic process, further comprises disposing a polymeric resin on a porous ceramic. The polymeric resin is impregnated in the pores of the porous ceramic; cutting the porous ceramic into one or more BCC stiffeners; disposing the die on the substrate; disposing the BCC stiffener of the one or more BCC stiffeners on the die that is disposed on the substrate; and curing the BCC stiffener on the die to form a bond between a bottom surface of the BCC stiffener and the back side surface of the die.
In example 16, the subject matter of any of examples 9-15 can optionally include the polymer resin in the liquid state process, further comprises cutting a porous ceramic into one or more ceramic stiffeners; disposing the die on the substrate; disposing a ceramic stiffener of the one or more ceramic stiffeners on the die that is disposed on the substrate; dispensing a polymeric resin on the ceramic stiffener. The polymeric resin is impregnated in the pores of the ceramic stiffener to form the BCC stiffener; and curing the BCC stiffener on the die to form a bond between a bottom surface of the BCC stiffener and the back side surface of the die.
In example 17, the subject matter of any of examples 9-16 can optionally include one or more BCC stiffeners includes at least one of a BCC die backside stiffener and a BCC picture frame stiffener.
Example 18 is a device package, comprising a die on a substrate. The die has a front side surface that is electrically coupled to the substrate and a back side surface that is opposite from the front side surface; and a BCC stiffener on a top surface of the substrate. The BCC stiffener surrounds the die.
In example 19, the subject matter of example 18 can optionally include the BCC stiffener formed with one or more materials. The one or more materials include porous ceramics, polymeric resins, and metals.
In example 20, the subject matter of any of examples 18-19 can optionally include the BCC stiffener directly coupled to the top surface of the substrate without an adhesive layer.
In example 21, the subject matter of any of examples 18-20 can optionally include the die electrically coupled to the substrate with an underfill layer.
In example 22, the subject matter of any of examples 18-21 can optionally include the BCC stiffener disposed on the edges of the substrate to reduce warpage based on the substrate and the die.
In example 23, the subject matter of any of examples 18-22 can optionally include a mold layer disposed over and around the BCC stiffener, the die, the underfill layer, and the substrate; and a motherboard disposed below the substrate. The motherboard is electrically coupled to the substrate.
In example 24, the subject matter of any of examples 18-23 can optionally include the BCC stiffener formed with the one or more materials using at least one of a polymeric resin in a liquid state process and a resin pre-loaded in a ceramic process.
In example 25, the subject matter of any of examples 18-24 can optionally include the BCC stiffener disposed on the die at a unit level or a wafer level.
In the foregoing specification, methods and apparatuses have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
