Patent Application
20240194680
The present disclosure relates to semiconductor structures and, more particularly, to a bidirectional device, methods of manufacture and methods of operation.
A high-electron-mobility transistor (HEMT) incorporates a junction between two materials with different band gaps (i.e. a heterojunction) as the channel, instead of a doped region (as is generally the case for a MOSFET). Commonly used material combinations are GaN or GaAs, although other materials can be used dependent on the application of the device.
HEMTs are able to operate at higher frequencies than ordinary transistors, up to millimeter wave frequencies. As the HEMTs are able to operate at higher frequencies, they can be used in high-frequency products such as cell phones, satellite television receivers, voltage converters, and radar equipment. For example, a HEMT may be used in satellite receivers and in low power amplifiers. In a bi-directional FET based on pGaN structure, operation of gate reliability and field reduction at the gate edge is very important compared to traditional unidirectional FETs. This is due to the fact that in operation the gate terminal can see high voltage.
In an aspect of the disclosure, a structure comprises: a first gate structure adjacent to a first source region; a second gate structure adjacent to a second source region; and field plates adjacent to the first gate structure, the second gate structure and a surface of an active layer of the first gate structure and the second gate structure.
In an aspect of the disclosure, a structure comprises: a first gate structure on an active semiconductor material and which comprises a first source region; a second gate structure on the active semiconductor material and which comprises a second source region; a first contact to the first source region; a second contact to the second source region; and field plates surrounding the first contact and the second contact.
In an aspect of the disclosure, a method comprises: forming a first gate structure adjacent to a first source region; forming a second gate structure adjacent to a second source region; and forming field plates adjacent to the first gate structure, the second gate structure and a surface of an active layer of the first gate structure and the second gate structure.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to a bidirectional device, methods of manufacture and methods of operation. More specifically, the present disclosure is directed to a field plated bidirectional HEMT structure. Advantageously, the field plated bidirectional HEMT structure provides improved gate reliability.
In embodiments, the bidirectional device includes two gate structures where either gate structure can assume high voltage. In embodiments, self-aligned field plates may be provided close to both gate structures and a surface of a semiconductor substrate comprising AlGaN/GaN. The gate structures and associated field plates completely enclose respective source terminals to avoid a gate crossing into an implanted isolation region, hence improving gate reliability.
The bidirectional device of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the bidirectional device of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the bidirectional device uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, precleaning processes may be used to clean etched surfaces of any contaminants, as is known in the art. Moreover, when necessary, rapid thermal anneal processes may be used to drive-in dopants or material layers as is known in the art.
A semiconductor material 16 and conductive material 18 may be formed, e.g., deposited and patterned, on the active semiconductor layer 20. The combination of the semiconductor material 16 and the conductive material 18 may be patterned to comprise gate structures 19a, 19b. In embodiments, the semiconductor material 16 comprises, e.g., p-doped GaN, and the conductive material 18 may be, e.g., TiN. In embodiments, the semiconductor material 16 may be epitaxially grown on the active semiconductor layer 20 with an in-situ doping, e.g., p-type doping, as is known in the art. The conductive material 18 may be deposited by a conventional deposition method (e.g., chemical vapor deposition (CVD)), followed by conventional lithography and etching processes for both materials 16, 18. In embodiments, the conductive material 18 may be pulled back slightly.
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In embodiments, the field plates 22 may physically be separated (e.g., electrically isolated) from a gate contact metal 26 contacting to the gate structures 19a, 19b. For example, sidewall spacers 21 formed on sidewalls of the gate contact metal 26 may electrically and physically isolate the gate contact metal 26 from an adjacent field plate 22. The gate contact metal 26 electrically connects (contacts) to the gate structures 19a, 19b and, more specifically, the conductive material 18.
An interlevel dielectric material 24, e.g., layers of oxide and/or nitride, may be formed over the field plates 22. The gate contact metal 26 may be, e.g., TiAl or TiN or Al or TaN, etc., formed by patterning of the interlevel dielectric material 24 to form a trench and which exposes the conductive material 18, e.g., TiN, followed by deposition of conductive material, e.g., TiN. In embodiments, the gate contact metal 26 and ohmic metals 26a, 27 for each of the source regions 23a, 23b may be the same metal materials formed in similar processes, e.g., conventional CMOS processes. Prior to forming the gate contact metal 26, the sidewall spacers 21 (e.g., nitride and/or oxide material) may be blanket deposited (e.g., lined) in a trench formed in the dielectric material 24 (and insulator material 24a) by a conventional deposition process, e.g., CVD, followed by conventional etching process.
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In operation, when both the gate structures 19a, 19b are turned ON with respect to their sources 23a, 23b, it is now possible to have a current flow from source region 23a to source region 23b or from the source region 23b to source region 23a. Also, in this configuration it is now possible to expose the gate structure 19a or the gate structure 19b to high voltage. For example, the voltage of the gate structure 19a and the voltage of the source region 23a can be high (Vg1=Vs1=HV), when the voltage of the gate structure 19b and the voltage of the source region 23b are 0V (Vg2=Vs2=0V). In this state, the device can block voltage in the OFF state from the source region 23a to the source region 23b. Similarly, the voltage of the gate structure 19b and the voltage of the source region 23b can be high when the voltage of the gate structure 19a and the voltage of the source region 23a are 0V. In this state, the device can block voltage in the OFF state from the source region 23b to the source region 23a. Moreover, by having the field plates 22 closely coupled to the gate structures 19a, 19b, gate reliability can be improved due to improved shielding of the gate structures 19a, 19b.
Further, the gate structures 19a, 19b may be formed on the active layer 20 by epitaxially growing the semiconductor material 16, e.g., GaN, on the active layer 20. In embodiments, an in-situ doping (e.g., p-type dopant) may be used during the epitaxial growth process. The conductive material 18 may be formed on the semiconductor material 16, e.g., GaN, by a deposition process, e.g., CVD. The conductive material 18 and the semiconductor material 16, e.g., GaN, may be patterned using conventional lithography and etching processes as described herein to form the gate structures 19a, 19b. The insulator material 24a may be formed over the gate structure 19 using conventional deposition methods, e.g., CVD.
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The trenches 50 may be formed by conventional lithography and etching methods known to those of skill in the art. For example, a resist formed over the dielectric material 24 is exposed to energy (light) and developed utilizing a conventional resist developer to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to transfer the pattern into the dielectric material 24 (and other materials, e.g., material 20) depending on the depth form one or more trenches 50.
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The bidirectional device can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things.
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
