Patent Application
20250062274
The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A bonding apparatus and a method of manufacturing an integrated circuit package using the bonding apparatus are provided. In accordance with some embodiments, the bonding apparatus may comprise a bonding head, a vacuum pump, a blower, and a controller. The bonding head may comprise vacuum channels and switchable channels, which may be switched between a vacuum mode and a blowing mode by the controller. The manufacturing an integrated circuit package may comprise placing an integrated circuit die on a wafer structure and bonding the integrated circuit die and a wafer structure. By utilizing the bonding apparatus to place the integrated circuit die on the wafer structure, the integrated circuit die may be first warped, then gradually flattened on the wafer structure, which may reduce or prevent voids between the integrated circuit die and the wafer structure during the bonding process, thereby improving the yield and the reliability of the integrated circuit package.
The bonding head 10 comprises a base 12 and an adapter 14 on a bottom surface of the base 12. The base 12 and the adapter 14 may be collectively referred to as a main body 15. A protrusion 20 is disposed on a bottom surface of the adapter 14. The adapter 14, along with the protrusion 20, may be disconnected from the base 12 and a different adapter with a different protrusion may be connected to the base 12, as described in greater detail below. A vacuum channel 16 and a switchable channel 18 are disposed on each side of the main body 15. Each switchable channel 18 is disposed between a sidewall of the main body 15 and the corresponding vacuum channel 16 on the same side of the main body 15. In some embodiments, the vacuum channels 16 and the switchable channels 18 are perpendicular to the bottom surface of the adapter 14.
The vacuum channels 16 and the switchable channels 18 are connected to the vacuum pump 300 by vacuum lines 302 and vacuum lines 304, respectively, so that the vacuum pump 300 may create vacuum in the vacuum channels 16 and the switchable channels 18 as directed by the controller 400. A vacuum valve 303 and a vacuum valve 305 are disposed on main lines of the vacuum lines 302 and the vacuum lines 304, respectively, and are communicatively coupled to the controller 400. The switchable channels 18 are connected to the blower 350 by gas lines 352, so that the blower 350, such as a mechanical blower, a compressed gas tank, or the like, may blow gas (e.g., air, nitrogen gas) through the switchable channels 18 as directed by the controller 400. A gas valve 353 is disposed on a main line of the gas lines 352 and is communicatively coupled to the controller 400. By directing the actions taken by the vacuum pump 300, the blower 350, the vacuum valve 303, the vacuum valve 305, and the gas valve 353, the controller 400 may direct actions in the vacuum channels 16 and the switchable channels 18 during the pick-and-place process as described in greater detail below. The bonding apparatus 450 may also include a motorized arm (not separately illustrated) that is connected to the bonding head 10 and communicatively coupled to the controller 400, so that the controller 400 may also direct the movement of the bonding head 10 during the pick-and-place process.
The adapter 14 of the main body 15 may have a width W1. The width W1 may be a distance from a first sidewall of the adapter 14 to a second sidewall of the adapter 14 opposite to the first sidewall. The vacuum channel 16 on a first side of the main body 15 may be spaced apart from the vacuum channel 16 on a second side of the main body 15 by a width W2, the second side being opposite to the first side. The width W2 may be a distance from an inner sidewall of the vacuum channel 16 on the first side of the main body 15 to an inner sidewall of the vacuum channel 16 on the second side of the main body 15. The width W2 may be larger than about half of the width W1. In some embodiments, the width W1 is larger than about 15 mm and the width W2 is larger than about 7.5 mm. The protrusion 20 may have a width W3 smaller than the width W2. The width W2 being larger than about half of the width W1 may lead to a width W3 of the protrusion 20 large enough to result in certain warpage of the integrated circuit die attached to the bonding head 10, which may be beneficial to the manufacturing of an integrated circuit package as described in greater detail below.
Top openings of the vacuum channels 16 and the switchable channels 18 may be connected with distribution manifolds (not separately illustrated), which are connected to the vacuum lines 302, the vacuum lines 304, and the gas lines 352.
The vacuum channels 16 and the switchable channels 18 may have circular bottom openings. The bottom openings of the vacuum channels 16 may have a diameter R1 and the bottom openings of the switchable channels 18 may have a diameter R2. The diameter R2 may be larger than or equal to the diameter R1. In some embodiment, the diameter R1 and the diameter R2 may be larger than about 0.1 mm. As described in greater detail below, the bottom openings of the vacuum channels 16 and the switchable channels 18 may exert an attaching force on the integrated circuit die and the bottom openings of the switchable channels 18 may exert a blowing force on the integrated circuit die in separate subsequent steps of the pick-and-place process, the diameter R1 and the diameter R2 being larger than about 0.1 mm may lead to sufficient attaching force and blowing force on the integrated circuit die, thereby improving the yield and the reliability of the integrated circuit package. The bottom openings of each plurality of the vacuum channels 16 and the switchable channels 18 may be arranged in a column extending along the first edge and the second edge of the main body 15. The top openings of the vacuum channels 16 and the switchable channels 18 may have same shapes and sizes as the bottom openings of the vacuum channels 16 and the switchable channels 18.
The bus 418 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus. The CPU 408 may comprise any type of electronic data processor, and the memory 410 may comprise any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM). The mass storage device 412 may comprise any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus 418. The mass storage device 412 may comprise, for example, one or more of a hard disk drive, a magnetic disk drive, or an optical disk drive. The memory 410 and/or mass storage device 412 may be a non-transitory computer readable medium having programming stored thereon. The programming may comprise instructions that, when executed by the CPU 408, cause the controller 400 to perform the controlling functionality described herein.
The video adapter 414 and the I/O interface 416 provide interfaces to couple external input and output devices to the processing unit 402. As illustrated in
In
The top integrated circuit die 50 may have a semiconductor substrate 52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or combinations thereof. The semiconductor substrate 52 may have an active surface (e.g., the surface facing downwards in
Devices (not separately illustrated) may be disposed at the active surface of the semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, or the like. An interconnect structure 54 may be disposed over the active surface of the semiconductor substrate 52. The interconnect structure 54 may interconnect the devices to form an integrated circuit. The interconnect structure 54 may be formed of metallization patterns (not separately shown) in dielectric layers (not separately shown). The dielectric layers may be low-k dielectric layers. The metallization patterns may include metal lines and vias, which may be formed in the dielectric layers by a damascene process, such as a single damascene process, a dual damascene process, or the like. The metallization patterns may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. The metallization patterns are electrically connected to the devices.
A bonding layer 56 may be disposed on the interconnect structure 54. The bonding layer 56 may be formed of an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a tetraethyl orthosilicate (TEOS) based oxide, or the like; a nitride, such as silicon nitride or the like. The bonding layer 56 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. One or more passivation layer(s) (not separately illustrated) may be disposed between the bonding layer 56 and the interconnect structure 54. Die connectors 58 may extend through the bonding layer 56. The die connectors 58 may include pads, conductive pillars, or the like, to which external connections can be made. In some embodiments, the die connectors 58 include bond pads at the front side of the top integrated circuit die 50 and vias that connect the bond pads to the metallization pattern of the interconnect structure 54. The die connectors 58, including the bond pads and the vias, may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The die connectors 58 may be formed of a conductive material, such as copper, aluminum, or the like, by a technique, such as plating or the like. A planarization process such as a chemical-mechanical polishing (CMP), a grinding process, an etch-back process, combinations thereof, or the like, may be performed on the bonding layer 56 and the die connectors 58. In some embodiments, after the planarization process, surfaces of the bonding layer 56 and the die connectors 58 may be substantially coplanar or level (within process variations).
In
In
The bottom integrated circuit die 100 may be a logic die (e.g., CPU, GPU, SoC, AP, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), a RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), a front-end die (e.g., AFE die), the like, or combinations thereof. The materials and manufacturing processes of the features in the bottom integrated circuit die 100 may be found by referring to the like features in the top integrated circuit die 50. The bottom integrated circuit die 100 may include a semiconductor substrate 102, which may have an active surface (e.g., the surface facing downwards in
The gap-fill layer 116 may be an insulating layer and may be formed of a dielectric material, such as silicon oxide, PSG, BSG, BPSG, a TEOS based oxide, or the like, which may be formed by a suitable deposition process such as CVD, ALD, or the like. Initially, the gap-fill layer 116 may cover the bottom integrated circuit die 100. A thinning process may be performed to level surfaces of the gap-fill layer 116, the semiconductor substrate 102, and the conductive vias 105. The thinning process may be a CMP process, a grinding process, an etch-back process, combinations thereof, or the like. Afterwards, the bonding layer 118 may be formed on the gap-fill layer 116 and the bottom integrated circuit die 100, and die connectors may be formed through the bonding layer 118 to connect to the conductive vias 105. The bonding layer 118 may be formed of an oxide such as silicon oxide, PSG, BSG, BPSG, a TEOS based oxide, or the like, which may be formed by a suitable deposition process such as CVD, ALD, or the like. The die connectors 120 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The die connectors 120 may be formed of a metal, such as copper, aluminum, or the like, which can be formed by plating or the like. A planarization process such as a CMP, a grinding process, an etch-back process, combinations thereof, or the like, may be performed on the bonding layer 118 and the die connectors 120. In some embodiments, after the planarization process, surfaces of the bonding layer 118 and the die connectors 120 may be substantially coplanar or level (within process variations).
In
In
Then the controller 400 first disables the blowing in the switchable channels 18 simultaneously by closing the gas valve 353. The duration of the blowing may be greater than 0.1 second, which may ensure sufficient blowing force is exerted on the peripheral portions of the top integrated circuit die 50 so that the top integrated circuit die 50 is sufficiently flattened. Afterwards, as shown in
The pick-and-place process described above with respect to
The bonding process may continue with a pressing step and an annealing step. In some embodiments, the pressing step is performed inside the bonding apparatus 450 and the annealing step is performed outside the bonding apparatus 450. During the pressing step, a small pressing force may be applied to press the top integrated circuit die 50 against the bonding layer 118 and the die connectors 120. The pressing step may be performed at a low temperature, such as room temperature. After the pressing step, the bonding between the bonding layer 56 of the top integrated circuit die 50 and the bonding layer 118 may be strengthened. The bonding between the bonding layer 56 and the bonding layer 118 may be further strengthened in the subsequent annealing step at a higher temperature. After the annealing step, the die connectors 58 of the top integrated circuit die 50 may be bonded to the respective die connectors 120. The die connectors 58 may be in physical contact with the die connectors 120 after the pressing step, or may expand to be brought into physical contact with the die connectors 120 during the annealing step. During the annealing step, the material of the die connectors 58 may intermingle or bond with the material of the die connectors 120, so that metal-to-metal bonds may be formed. After the annealing step the top integrated circuit die 50 may be electrically connected the bottom integrated circuit die 100 by the die connectors 120. Due to the flattening of the top integrated circuit die 50 on the wafer structure 150 during the pick-and-place process as described above, after the annealing step, interfaces between the peripheral portions, including respective edges, of the top integrated circuit die 50 and the wafer structure 150 may be free of voids.
In
In
The UBMs 218 may have portions extending along a surface of the dielectric layer 216 and portions extending through the dielectric layer 216 to physically and electrically connect to the die connectors 108. As an example to form the UBMs 218, the dielectric layer 216 may be patterned to form openings exposing the underlying die connectors 108. A seed layer (not separately illustrated) may be formed on the dielectric layer 216, in the openings through the dielectric layer 216, and on the exposed portions of the die connectors 108. The seed layer may be a metal layer and may be formed using a suitable deposition process, such as physical vapor deposition (PVD) or the like. A photoresist may be then formed and patterned on the seed layer. A conductive material may be formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroless plating, electroplating, or the like. Then the photoresist and portions of the seed layer on which the conductive material is not formed may be removed. The remaining portions of the seed layer and conductive material may form the UBMs 218.
Electrical connectors 220 may be formed on the UBMs 218. The electrical connectors 220 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. In some embodiments, the electrical connectors 220 comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof, and are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like, then reflowing the conductive material into the desired bump shapes. In some embodiments, the electrical connectors 220 comprise metal pillars, such as a copper pillar, formed by a sputtering, printing, electroplating, electroless plating, CVD, or the like, which are solder free and have substantially vertical sidewalls.
The processes discussed with respect to
In
The package substrate 228 may include active and passive devices (not separately illustrated), such as transistors, capacitors, resistors, combinations thereof, or the like. The package substrate 228 may comprise metallization layers and vias (not separately illustrated) physically and electrically connected to the bonding pads 230. The metallization layers may be formed over the active and passive devices and may electrically connect the active and passive devices to form functional circuitry. The metallization layers may be alternating layers of dielectric material and conductive material with vias interconnecting the layers of conductive material. In some embodiments, the package substrate 228 is free of active and passive devices.
During the bonding process the electrical connectors 220 may be reflowed to bond the integrated circuit package component 250′ to the bonding pads 230 of the package substrate 228. The electrical connectors 220 may electrically and physically connect the package substrate 228 to the integrated circuit package component 250′. In some embodiments, a solder resist (not separately illustrated) is disposed on the package substrate 228. The electrical connectors 220 may be disposed in openings in the solder resist to electrically and physically connect to the bond pads 230. The solder resist may be used to protect areas of the package substrate 228 from external damage. The underfill 234 may surround the electrical connectors 220 and protect the joints resulting from the reflowing of the electrical connectors 220. The underfill 234 may be formed by a capillary flow process after the integrated circuit package component 250′ is attached or by a suitable deposition method before the integrated circuit package component 250′ is attached. The underfill 234 may be subsequently cured. The structure shown in
Various embodiments are described above in the context of forming a system on integrated chips (SoIC) package configuration. It should be understood that various embodiments may also be adapted to apply to forming other package configurations, such as integrated fan-out on substrate (InFO), chip on wafer on substrate (CoWoS) or the like.
The embodiments may have some advantageous features. By utilizing the bonding apparatus 450 to place the top integrated circuit die 50 on the wafer structure 150, the top integrated circuit die 50 may be first warped, then gradually flattened on the wafer structure 150, and the air between the top integrated circuit die 50 and the wafer structure 150 may be gradually expelled, which may reduce or prevent voids between the top integrated circuit die 50 and the wafer structure 150 during the bonding process, thereby improving the yield and the reliability of the integrated circuit package 280.
In an embodiment, a bonding apparatus includes a vacuum pump; a blower; a controller communicatively coupled to the vacuum pump and the blower; and a bonding head, wherein the bonding head includes a main body; a first vacuum channel in the main body, wherein the first vacuum channel is connected to the vacuum pump; and a first switchable channel in the main body, wherein the first switchable channel is connected to the vacuum pump and the blower. In an embodiment, the first vacuum channel has a circular opening with a first diameter in a bottom-up view and the first switchable channel has a circular opening with a second diameter in the bottom-up view, and wherein the first diameter is larger than or equal to the second diameter. In an embodiment, the second diameter is greater than 0.1 mm. In an embodiment, the first switchable channel is between a first edge of the main body and the first vacuum channel in a bottom-up view. In an embodiment, the bonding apparatus further includes a second switchable channel in the main body and a protrusion on a bottom surface of the main body, wherein the protrusion is disposed in a central region of the bottom surface of the main body, wherein the protrusion is between the second switchable channel and the first vacuum channel in a bottom-up view, and wherein the second switchable channel is connected to the vacuum pump and the blower. In an embodiment, the bonding apparatus further includes a second vacuum channel in the main body, wherein the second vacuum channel is between the second switchable channel and the protrusion in the bottom-up view, and wherein the second vacuum channel is connected to the vacuum pump. In an embodiment, the main body has a first width, wherein the first vacuum channel is spaced apart from the second vacuum channel by a second width, and wherein the second width is greater than or equal to half of the first width.
In an embodiment, a bonding apparatus includes a controller; a vacuum pump, a first vacuum valve, and a second vacuum valve communicatively coupled to the controller; a blower and a gas valve communicatively coupled to the controller; and a bonding head, wherein the bonding head includes a main body; a protrusion on a central portion of a bottom surface of the main body; a first plurality of vacuum channels in the main body, wherein the first plurality of vacuum channels are connected to the vacuum pump through the first vacuum valve, and wherein the controller is configured to create vacuum in the first plurality of vacuum channels simultaneously; and a first plurality of switchable channels in the main body, wherein the first plurality of switchable channels are connected to the vacuum pump through the second vacuum valve and to the blower through the gas valve, wherein the controller is configured to create vacuum in the first plurality of switchable channels simultaneously or create blowing in the first plurality of switchable channels simultaneously. In an embodiment, the bonding apparatus further includes a second plurality of switchable channels in the main body, wherein the controller is configured to create vacuum in the first plurality of switchable channels and the second plurality of switchable channels simultaneously or create blowing in the first plurality of switchable channels and the second plurality of switchable channels simultaneously, wherein openings of the first plurality of switchable channels form a first column of openings along a first edge of the main body in a bottom-up view, and wherein openings of the second plurality of switchable channels form a second column of openings along a second edge of the main body opposite to the first edge in the bottom-up view. In an embodiment, the bonding apparatus further includes a second plurality of vacuum channels in the main body, wherein the controller is configured to create vacuum in the first plurality of vacuum channels and the second plurality of vacuum channels simultaneously, wherein openings of the first plurality of vacuum channels form one or more columns of openings between the first column of openings and the protrusion in the bottom-up view, and wherein the second plurality of vacuum channels form one or more columns of openings between the second column of openings and the protrusion in the bottom-up view. In an embodiment, each of the first plurality of vacuum channels has a same first diameter, wherein each of the first plurality of switchable channels has a same second diameter, and wherein the first diameter is greater than the second diameter.
In an embodiment, a method for forming an integrated circuit package includes attaching a first substrate to a bonding head by creating negative pressure in a first vacuum channel and a first switchable channel in the bonding head, wherein the first switchable channel is between a first sidewall of the bonding head and the first vacuum channel; placing the first substrate to a top surface of a second substrate and forming bonding between the first substrate and the second substrate; releasing the negative pressure in the first vacuum channel while maintaining the negative pressure in the first switchable channel; and after releasing the negative pressure in the first vacuum channel, releasing the negative pressure in the first switchable channel and blowing the first substrate away from the bonding head by creating positive pressure in the first switchable channel. In an embodiment, after attaching the first substrate to the bonding head, a central portion of the first substrate is in direct contact with a bottom surface of a protrusion of the bonding head and a peripheral portion of the first substrate is in direct contact with a bottom surface of a main body of the bonding head, and wherein the protrusion of the bonding head is on the bottom surface of the main body of the bonding head. In an embodiment, after placing the first substrate to the top surface of the second substrate, a central portion of the first substrate is in direct contact with the top surface of the second substrate and a peripheral portion of the first substrate is spaced apart from the top surface of the second substrate. In an embodiment, after blowing the first substrate away from the bonding head, the peripheral portion of the first substrate is in direct contact with the top surface of the second substrate. In an embodiment, blowing the first substrate away from the bonding head lasts for more than 0.1 second. In an embodiment, the first substrate is warped by the bonding head and then flattened by the bonding head. In an embodiment, the method further includes annealing the first substrate and the second substrate after releasing the negative pressure in the first switchable channel and blowing the first substrate away from the bonding head, wherein after annealing the first substrate and the second substrate, an interface between an edge of the first substrate and the second substrate is free of voids. In an embodiment, the method further includes annealing the first substrate and the second substrate after releasing the negative pressure in the first switchable channel and blowing the first substrate away from the bonding head, wherein annealing the first substrate and the second substrate strengthens the bonding between the first substrate and the second substrate. In an embodiment, the main body has a first width between the first sidewall of the main body and a second sidewall of the main body opposite to the first sidewall, wherein the first substrate has a second width, and wherein the first width is larger than the second width.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
