Patent Application
20250192037
The present invention generally relates to the field of microelectronic, and more particularly to formation of a jumper for a Mx lines within an interconnect structure.
Nanosheet is the lead device architecture in continuing CMOS scaling. However, nanosheet technology has shown issues when scaling down such that as the devices become smaller and closer together, they are interfering with each other. Forming connections between different metal lines can limit the size/dimension of other lines because it can lead to electrical shorts from the lines overlapping or being too close to each other.
Additional aspects and/or advantages will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the invention.
A microelectronic structure including an underlying device. An interconnect located on the underlying device. Interconnect includes a first Mx metal line and a second Mx metal line. The first Mx metal line is located adjacent to the second Mx metal line. A jumper connects the first Mx metal line to the second Mx metal line and the first Mx metal line extends higher than the jumper.
A microelectronic structure including an underlying device and an interconnect located on the underlying device. The interconnect includes a plurality of Mx metal lines where at least one Mx metal line of the plurality of Mx Metal lines includes an integral connecting via. At least one jumper connecting at least two adjacent Mx metal lines of the plurality of Mx metal lines. The at least one Mx metal line with the integral connecting via extends higher than the at least two adjacent Mx metal lines.
A microelectronic structure including an underlying device and an interconnect located on the underlying device. The interconnect includes a plurality of Mx metal lines. At least one or more jumpers connecting a group Mx metal lines of the plurality of Mx metal lines. The group of Mx metal lines includes three adjacent Mx metal lines. Each of the Mx metal lines in the group of Mx metal lines extends higher than the at least one or more jumpers.
A method including the steps of forming an underlying device and forming an interconnect located on the underlying device. Interconnect includes a first Mx metal line and a second Mx metal line. The first Mx metal line is located adjacent to the second Mx metal line. A jumper connects the first Mx metal line to the second Mx metal line and the first Mx metal line extends higher than the jumper.
The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the invention. In addition, descriptions of well-known functions and constructions may be omitted for clarity and conciseness.
The terms and the words used in the following description and the claims are not limited to the bibliographical meanings but are merely used to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustration purpose only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.
It is understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a component surface” includes reference to one or more of such surfaces unless the context clearly dictates otherwise.
Detailed embodiments of the claimed structures and the methods are disclosed herein: however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present embodiments.
References in the specification to “one embodiment,” “an embodiment,” an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art o affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purpose of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the disclosed structures and methods, as orientated in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, where intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating, or semiconductor layer at the interface of the two elements.
In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustrative purposes and in some instance may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.
Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or indirect coupling, and a positional relationship between entities can be direct or indirect positional relationship. As an example of indirect positional relationship, references in the present description to forming layer “A” over layer “B” includes situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other element not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiment or designs. The terms “at least one” and “one or more” can be understood to include any integer number greater than or equal to one, i.e., one, two, three, four, etc. The terms “a plurality” can be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, etc. The term “connection” can include both indirect “connection” and a direct “connection.”
As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrations or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. The terms “about” or “substantially” are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of the filing of the application. For example, about can include a range of +8%, or 5%, or 2% of a given value. In another aspect, the term “about” means within 5% of the reported numerical value. In another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.
Various processes are used to form a micro-chip that will packaged into an integrated circuit (IC) fall in four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etching process (either wet or dry), reactive ion etching (RIE), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implant dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage.
Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, where like reference numerals refer to like elements throughout. The present invention is directed towards an interconnect structure, for example, a back-end-of-the-line (BEOL) structure or a backside-power-distribution-network (BSPDN). These structures are comprised of different metal lines (e.g., Mx, Mx+1 metal lines), and connecting vias with the components distributed on multiple levels. The connecting vias (or via level) can be integrally formed with the Mx metal lines. The design for the interconnect can require that some of the different metal lines, for example, on the Mx level need to be connected to each other. When a connection is formed on top of the Mx metal lines (i.e., on top of the via level), e.g., in the form of a metal bridge, then the bridge placement interferes with the placement of the Mx+1 metal lines. When the Mx+1 metal lines are located close to the bridge which can lead to the formation of an electrical short. Furthermore, the placement/location of the bridge affects the sizing of the Mx+1 metal lines.
In contrast to the formation of the metal bridge (i.e., bridges on top of the via level) the present invention forms jumpers between adjacent Mx metal lines. The jumper is located at the base of the Mx metal lines thus the jumper does not affect the placement/size or interfere with the Mx+1 metal lines located on top of the via level. The Mx metal lines (with an integral via level), Mx metal lines (without an integral via level), and an integral jumper are formed from the same metal layer. The different components are formed by selectively removing different portions of the metal layer, which allows for the reduction of miss alignment processing errors.
Referring now to
A microelectronic structure including an underlying device 105. An interconnect 106 located on the underlying device 105. Interconnect 106 includes a first Mx metal line 152 and a second Mx metal line 154. The first Mx metal line 152 is located adjacent to the second Mx metal line 154. A jumper 140 connects the first Mx metal line 152 to the second Mx metal line 154 and the first Mx metal line 152 extends higher than the jumper 140.
The jumper 140 is located at the base of the first Mx metal line 152 and at the base of the second Mx metal line 154.
A first layer 110 located between the underlying device 105 and the first Mx metal line 152, and the first layer 110 is located between the underlying device 105 and the second Mx metal line 154. The first layer 110 is comprised of TiN or TaN. The jumper 140 is located on the first layer 110.
An interlayer dielectric layer 160 located above and around the first Mx metal line 152, the second Mx metal line 154, and the jumper 140. The interconnect 106 further includes a Mx+1 metal line 170 located on top of the interlayer dielectric layer 165. The first Mx metal line 152, the second Mx metal line 154, and the jumper 140 are located at a different height than the Mx+1 metal line 170. The interlayer dielectric layer 160 is located between the Mx+1 metal line 170 and the first Mx metal line 152, the second Mx metal line 154, and the jumper 140.
A microelectronic structure including an underlying device 105 and an interconnect 106 located on the underlying device 105. The interconnect 106 includes a plurality of Mx metal lines 119, 127, 152, 154, 156, where at least one Mx metal lines 119, 127 of the plurality of Mx Metal lines 119, 127, 152, 154, 156 includes an integral connecting via (i.e., the via level illustrated in the Figures). At least one jumper 140 connecting at least two adjacent Mx metal lines 152, 154 of the plurality of Mx metal lines 119, 127, 152, 154, 156. The at least one Mx metal line 119, 127 with the integral connecting via (i.e., the via level illustrated in the Figures) extends higher than the at least two adjacent Mx metal lines 152, 154.
The at least one jumper 140 is located at the base of the at least two adjacent Mx metal lines 152, 154.
A first layer 110 located between the underlying device 105 and the at least two adjacent Mx metal lines 152, 154. The first layer 110 is comprised of TiN or TaN. The at least one jumper 140 is located on the first layer 110.
The interconnect 106 further includes an interlayer dielectric layer 160 located above and around the at least one jumper 140 and the at least two adjacent Mx metal lines 152, 154. The interconnect 106 further includes at least one Mx+1 metal line 170 located on top of the interlayer dielectric layer 160. The at least one jumper 140 and the at least two adjacent Mx metal lines 152, 154 are located at a different height than the at least one Mx+1 metal line 170. The interlayer dielectric layer 160 is located between the at least one Mx+1 metal line 170 and the at least one jumper 140 and the at least two adjacent Mx metal lines 152, 154. The at least one Mx+1 metal line 170 is connected to a top surface of the at least one Mx metal line 119, 127 that includes the integral connecting via (as illustrated in
A microelectronic structure including an underlying device 105 and an interconnect 106 located on the underlying device 105. The interconnect 106 includes a plurality of Mx metal lines 119, 127, 202, 204, 205 (or 152, 154, 156). At least one or more jumpers 140, 200 connecting a group Mx metal lines 202, 204, 205 (or 152, 154, 156) of the plurality of Mx metal lines 119, 127, 202, 204, 205. The group of Mx metal lines 202, 204, 205 (or 152, 154, 156) includes three adjacent Mx metal lines 202, 204, 205. Each of the Mx metal lines 202, 204, 205 (or 152, 154, 156) in the group of Mx metal lines extends higher than the at least one or more jumpers 140, 200.
The at least one or more jumpers 140, 200 is a double jumper 200. The double jumper 200 extends laterally to connect the three adjacent Mx metal lines 202, 204, 205 of the group of Mx metal lines.
At least one or more jumpers 140 is comprised of two jumpers 140 to connect the three adjacent Mx metal lines 152, 154, 156 of the group of Mx metal lines. The two jumpers 140 are offset from each other as illustrated in
A method including the steps of forming an underlying device 105 and forming an interconnect 106 located on the underlying device 105. Interconnect 106 includes a first Mx metal line 152 and a second Mx metal line 154 and the first Mx metal line 152 is located adjacent to the second Mx metal line 154. A jumper 140 connects the first Mx metal line 152 to the second Mx metal line 154 and the first Mx metal line 152 extends higher than the jumper 140. The jumper 140 is located at the base of the first Mx metal line 152 and at the base of the second Mx metal line 154.
While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims and their equivalents.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the one or more embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
