Currently, a number of systems exist for testing various types of semiconductor-based devices. In general, such systems interface with the device-under-test (DUT) and perform various analyses to test the operation, functionality, etc. of the DUT. Typically, the results of these tests are logged to a results file for subsequent analysis to assess the processor design and/or the yield of the fabrication process.
Existing systems for analyzing the results file, however, are limited because of the large size of the file. The results file is typically very large because the test system performs a number of tests for each processor on each wafer in the lot.
Systems, methods, and computer programs for performing cache yield analysis of a processor design are provided. One embodiment is a method for testing cache performance of a processor design which comprises searching a file that contains test results for a lot of wafers; and identifying at least one processor on one of the wafers in the lot in which a cache array has passed a cache test.
Another embodiment is a system for testing cache performance of a processor design which comprises: a parser module for searching a file that contains test results for a lot of wafers; and a cache-testable processor identification module for identifying processors on wafers in the lot in which a cache array has passed a cache test.
A further embodiment is a computer program embodied in a computer-readable medium, such computer program comprising logic configured to search a file that contains test results for a lot of wafers; and logic configured to identify at least one processor on one of the wafers in the lot in which a cache array has passed a cache test.
Many aspects of the invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating principles in accordance with exemplary embodiments of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
This disclosure relates to various embodiments of systems, methods, and computer programs for testing cache performance of a processor design. Several embodiments will be described below with reference to
In one exemplary embodiment, a cache-testable processor identification system is configured to interface with a file that contains results of various tests performed on processor(s) in a collection of wafers (i.e., lot). The cache-testable processor identification system is configured-to search the file and identify processors on wafers in the lot for which a cache array has passed a cache test. For example, in one embodiment, the cache-testable processor identification system interprets the data in the file and determines processors in which the built-in-self-test (BIST) engine was able to execute the cache test. It should be appreciated that this information regarding which processors passed the cache test (i.e., the processor was cache-testable) may be useful to processor designers and/or manufacturers for performing additional analysis.
Referring to
Test criteria 118 may comprise a data file or logic that defines and/or controls the test(s) to be performed on processors 112. One of ordinary skill in the art will appreciate that any of a variety of types of tests may be performed on processors 112 and, therefore, test criteria 118 may be configured accordingly. Various embodiments of test criteria 118 may be configured to test the cache components (e.g., instruction cache, data cache, etc.) of processors 112.
As illustrated in
As known in the art, during operation of processor test system 106, the results of the tests performed on each processor 112, wafer 204, and/or the corresponding aspects of processors 112 or wafer 204 may be logged to test results file 120. Typically, due to the large number of tests being performed and the large number of processors 112, test results file 120 is relatively large. It should be appreciated that test results file 120 may be configured in a variety of ways. For example, test results file 120 may be represented in hexadecimal, binary, or other suitable data formats.
Referring to
Rather, cache array 402 defines a grid that may be identified by X-Y coordinates corresponding to a bit at a particular location in cache array 402. As known in the art, a cache test may be performed to test various aspects of the cache array 402. In this regard, it should be appreciated that test results file 120 contains data corresponding to the particular tests to be performed.
As briefly described above, cache-testable processor identification system 100 may be configured to interface with test results file 120. Cache-testable processor identification system 100 may be configured to search test results file 120 and identify cache-testable processors 112 on wafers 204 in lot 202. In one embodiment, cache-testable processor identification system 100 identifies processors 112 for which a cache array 402 has passed a cache test. In other embodiments, cache-testable processor identification system 100 interprets the data in test results file 120 and determines processors 112 in which built-in-self-test (BIST) engine 308 was able to execute the cache test.
One of ordinary skill in the art will appreciate that this type of information may be useful to designers and/or manufacturers for performing subsequent analysis of test results file 120. In this manner, cache-testable processor identification system 100 may perform a high-level search to identify cache-testable processors 112. After the cache-testable processors 112 are identified a more granular cache analysis may be performed.
One of ordinary skill in the art will appreciate that cache-testable processor identification system 100 may be implemented in software, hardware, firmware, or a combination thereof. Accordingly, in one embodiment, cache-testable processor identification system 100 is implemented in software or firmware that is stored in a memory and that is executed by a suitable instruction execution system. In software embodiments, cache-testable processor identification system 100 may be written any computer language. In one exemplary embodiment, cache-testable processor identification system 100 comprises a PERL script.
In hardware embodiments, cache-testable processor identification system 100 may be implemented with any or a combination of the following technologies, which are all well known in the art: a discrete logic circuit(s) having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array(s) (PGA), a field programmable gate array (FPGA), etc.
It should be appreciated that the process descriptions or blocks related to
Furthermore, cache-testable processor identification system 100 may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “computer-readable medium” can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a nonexhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM) (electronic), a read-only memory (ROM) (electronic), an erasable programmable read-only memory (EPROM or Flash memory) (electronic), an optical fiber (optical), and a portable compact disc read-only memory (CDROM) (optical). Note that the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.