Patent Application
20090009212
High-speed systems operation at very high frequencies employ dedicated calibration devices and methods to deal with signal reflections or interferences. Signal reflection causes noise, which lowers signal quality. In a high-speed data transfer system, high-quality signals are required.
Therefore, there is a need for improved calibration systems and methods.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. Like reference numerals designate corresponding parts.
Advantages and details of the present invention will become apparent to the reader of the present invention when reading the detailed description referring to preferred embodiments of the present invention.
Throughout the detailed description and the accompanying drawings same or similar components, units or devices will be referenced by same reference numerals for clarity purposes.
System calibration is often necessary for a system to meet specified operating conditions. For example, in a system employing a memory device, calibration of output drivers and termination resistors may be provided by means of external impedances (resistors) which are mounted on a printed circuit board PCB of the memory system or computer system, for instance.
Additionally a dedicated external impedance to calibrate the controller is provided. That is, two different impedances are used, the first one to calibrate the (memory) controller and the second one to calibrate the output drivers of the memory system. In addition, the two calibration sequences can operate independently from each other. Therefore, the controller calibration is provided independently from the memory calibration.
A memory system according to one embodiment of the present invention is shown in
The memory controller 100 employs a plurality of input/output terminals. For the sake of simplicity only the relevant ones are shown. The memory controller 100 includes a command and address path CMD/ADDR interconnecting each of the memory devices 111. According to one embodiment the memory devices 111 are dynamic random access modules (DRAM). The system may include any type of memory device, or any logic device. Additionally a clock signal path CLK is provided. The clock signal CLK is used to synchronize the data input/output to and out from each of the memory devices 111. The command path CMD may be used to convey commands like read or write to each memory device 111. Each memory device can be additionally equipped with a logic device or a controller, respectively. Information transfer is accomplished over a bi-directional data bus, referenced as DQ.
The memory controller 100 according to one embodiment of the present invention provides an on die termination device (ODT) 110, which is to be used to calibrate the memory system of
According to one embodiment of the invention the data bus DQ is used to convey calibration signals or information. That is, the data bus may be quiet during calibration, because of data interferences with other signals like data signals during usual operation of the data bus DQ for instance. The output drivers, namely the off-chip drivers of the memory devices 111 are calibrated or adjusted respectively based on the ODT 110 of the memory controller 100. The term off-chip means that the signals are driven out of the device. Each signal line of the data bus DQ is connected by means of an off-chip driver circuit of the corresponding memory modules 111 to the memory device. The signal mismatch of the pull-up and pull-down components of the output drivers may be reduced by calibrating the memory devices 111.
According to one embodiment the off-chip drivers of each memory device 111 includes a corresponding PMOS and NMOS leg (not shown). The corresponding legs are adapted to provide the pull-up and pull-down currents for driving the output signal of the memory system. By adjusting the pull-up and pull-down drive strength of the above-mentioned output drivers the output levels and the rise and fall times of the output signal can be optimized. The adjustment is provided by the calibration operation operated within each memory device 111. Therefore, an optimized impedance setting for each of the PMOS and NMOS legs is provided.
During the calibration operation the memory controller 100 calibrates itself against the external impedance 120. That is, the ODT 110 is now calibrated with reference to the external impedance 120. The impedance 120 shows a dedicated value, which may be set by a memory system manufacturer for instance. Subsequently, the memory devices 111 use the already calibrated ODT 110 as a basis for calibration. It should be noted that other external impedances 120 may be used.
For instance, the external impedance 120 can be embedded within the controller 100, but other architectures are feasible. The reference number 112 symbolizes the local connection between the ODT 110 and an I/O terminal (not shown in
With reference to
On a system-level according to one embodiment shown in
An embodiment of the calibration operation is shown with reference to
The controller calibrates itself on the basis of impedance 120 while holding the memory device 111 in a RESET mode. The RESET mode of the memory device 111 may be controlled by a reset line RESET, which is schematically shown in
The controller 100 activates the ODT 110 against e.g. high-level. The ODT-impedance 110 is calibrated on the basis of the impedance 120. The external impedance 120 may be implemented on the PCB of the system, for instance. Other implementations like, on package integration of the external impedance or similar are possible as well.
The RESET signal over the reset line is activated or released, which triggers the calibration operation of the memory device 111. According to this example the ODT 110 is calibrated against a high-level voltage (as described above), the memory device 111 calibration includes calibration of the pull-down leg against the controller-ODT 110. The pull-down leg is a functional part of the output driver of the memory device 111.
After a number of clock cycles, for example N/2 cycles of the system clock (not shown), the calibration of the pull-down leg is finished and the controller 100 switches off the ODT 120 such that the memory device 111 can calibrate the pull-up leg against its own (and already calibrated) pull-down leg. Thereby achieving a consistent calibration because only one external impedance 120 for calibration is necessary. The reference sign N corresponds to the number of clock cycles of the system clock, for instance.
Both the controller 100 and the memory 111 are configured to count the number of clock-cycles expired such that switching-off of controllers ODT 110 and switching-on of the calibration-mode of the memory 111 can be easily synchronized.
Thus, after N cycles, the calibration is finished. Consequently, external calibration resistors or impedances for the memory device 111 are not required and the calibration results of the memory device 111 and controller 100 are matched, because only one external resistor 120 has to be used in this embodiment. Further no copy of the output driver circuits for calibration on the memory device is required. That is, the calibration operation may be configured to use the usual output drivers of the integrated device.
During operation of the memory system the memory controller 100 may generate a reset signal RESET, which is conveyed to a memory device 111. Accordingly the memory device is switched into a calibration mode or state. Once the reset signal RESET is received the memory and/or the controller will count the clock cycles. The duration of one clock cycle is referenced as tCK according to
According to one embodiment the reset signal corresponds to a calibration start signal, that is the calibration start signal or reset signal indicates that a calibration mode is to be entered.
The calibration of the pull-down leg can be N/2 clock cycles from a reset. The calibration of the pull-down leg is performed on the basis of the ODT 110 of the controller 100. The ODT 110 of the controller is activated during N/2 time cycles. The ODT 110 may be switched off and the calibration of the pull-up leg of the driver is done based on the already calibrated pull-down leg.
According to one embodiment of the invention, the calibration of the pull-up leg takes N/2 clock cycles as well but other clock counts are possible. The CTRL ODT at the bottom of
After N cycles the memory device 111 is ready to be addressed and the calibration operation is completed. According to other embodiments of the calibration operation, the pull-down leg can be calibrated on the basis of the pull-up leg. That is, the calibration operation can be mirrored but other implementations are possible and will be within the skill of one of ordinary skill in the art.
In the following the calibration signals are conveyed by the data bus or DQ-bus 405. It should be understood that the same calibration operation could also be carried out by the command/address bus 406, for instance. According to one embodiment the calibration signals are transmitted via a calibration pattern. The general clock signal provided by the memory controller 425 may be used to control the calibration signal pattern or the calibration signal sequence.
According to one embodiment the memory controller 425 may perform the calibration operation during the initialization of the memory subsystem after power-up for instance. In another embodiment, calibration may be performed periodically or after leaving a sleep state of the system.
The memory controller includes an on die termination device ODT 402 can be used as a reference during the calibration of the memory circuits 415. The ODT 402 is calibrated with reference to an external device 401. The external device 401 may be a resistor for instance, and it could be implemented on the PCB. It is possible that the external device can be omitted and an integrated resistor is used. However, according to one possible embodiment the ODT 402 is calibrated on the basis of an external resistor 401.
During calibration of the memory circuits 415 it is assumed that the ODT 402 is already calibrated. The memory circuits receive a RESET signal for instance in a calibration mode, which is shown with reference to
According to one embodiment the DQ bus 405 may be used to transmit the calibration signals. During the calibration operation the memory circuit 415 calibrates its pull-up leg based on the already calibrated ODT 402 and the pull-down leg is in turn calibrated based on the already calibrated pull-up leg. An analogous calibration scenario could be achieved if the pull-down leg is calibrated first.
The system according to one embodiment of the present invention may be controlled by the CPU. The CPU 420 communicates with the other components by means of a system bus 410.
Additionally, the data system includes an extension bus 430 with an extension bus controller (not shown). The extension bus 430 communicates with a plurality of peripheral devices 460, 470, 480, 490, like for instance a keyboard, a hard disk, an I/O interface and a user I/O interface. Additional peripheral multimedia adapters or the like are also feasible.
Although the data system of
Embodiments of the present invention may be used for devices employing graphic memory systems like GDDR-Systems or the like. But also mobile devices, computer systems or the like may be equipped with a memory system according to embodiments of the present invention.
The memory device 111 according to embodiments of the invention may be any data storing semiconductor device, e.g., a PLA, PAL, or ROM device, for instance a PROM, EPROM, EEPROM, or flash memory device, etc., or e.g. a RAM device, for instance an SRAM or DRAM, e.g., a DDR-DRAM or DDR2-DRAM (DDR DRAM=Double Data Rate DRAM), etc. wherein calibration of drivers, for instance, is desired. Further the memory device 111 may comprise one single integrated circuit chip, e.g., one single memory, microprocessor, or microcontroller chip, etc. mounted into one single chip package, for instance. Alternatively, several integrated circuit chips may be mounted into one single chip package, e.g. two, three, or four chips, etc.
For instance, the chip package may comprise two or four DRAM chips, with one chip stacked upon the other, which correspond to a “stacked DRAM”.
In a first step S500 a DRAM or other circuitry may receive a reset signal from a controller indicating that a calibration operation is to be performed. According to the operational step S510 the output driver impedance of the circuitry is calibrated on the basis of an on die termination of the memory controller.
According to a step S520 a calibration pattern received by the circuitry is executed and the operation may come to an end S530. The operation may be restarted by means of a RESET signal, and thus a second iteration can be carried out.
Although the invention is described above with reference to embodiments according to the accompanying drawings, it is clear that the invention is not restricted thereto but can be modified in several ways within the scope of the appended claims.
