Patent Application
20250048658
Many modern day electronic devices include capacitors. The capacitance of a capacitor depends on multiple factors, including the surface area of a first and second electrode, the proximity of the first and second electrode, and the permittivity of a dielectric between the first and second electrode. The surface area of the first and second electrodes may be formed in horizontal formations across the electronic device, in vertical formations, or in both formations depending on the target capacitance and availability of space in the electronic device.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Capacitors are used for a variety of purposes in integrated devices, including memory, image processing, and sensing apparatus. The capacitance of a capacitor is dependent on multiple factors, including the surface area of a first and second electrode, the proximity of the first and second electrode, and the permittivity of a dielectric between the first and second electrode. When formed using back-end-of-line (BEOL) processes, capacitors may be formed having a surface area spread across a dielectric, with the surface area confined in trenches etched into the dielectric, or a combination of both of these distributions. Capacitors spread horizontally across the dielectric may be patterned using a single etching process and may have a large variety of capacitances without increasing the number of etches used, though they use a larger surface area of the integrated chip than a vertical capacitor. Vertical capacitors (e.g., capacitors formed in trenches) extend through the integrated device vertically, and therefore use a smaller surface area of the integrated chip than a horizontally spread capacitor, which may result in a greater density of capacitors fitting into a single layer of the integrated device. However, the method of forming vertical capacitors typically uses separate masks and etching steps to form trenches of different depths to form the vertical capacitors in, resulting in increased costs and low flexibility. Capacitors utilizing a combination of both horizontal and vertical structures increase the flexibility of the capacitor array, but lower the density of capacitor that may fit in a single layer of the integrated device. A capacitor array with the high density of capacitors available to arrays utilizing vertical capacitors, a low number of masking and etching steps, and the flexibility of capacitances available to arrays utilizing horizontally spread capacitors is desirable.
The present disclosure provides an integrated device comprising capacitors with bottom electrode structures of different widths and different depths. The capacitors are formed by etching a plurality of trenches with multiple depths into a dielectric layer. The plurality of trenches are etched using a single etching process and a masking layer with openings of varying widths. The widths of the openings in the masking layer result in the etch rate of the plurality of trenches to vary, due to the etch-loading effect. The differences in etch rate leads to the plurality of trenches having different depths. Capacitors are then formed in the plurality of trenches. Capacitors formed in the trenches with greater depths and widths have a greater surface area. The difference in surface area of the capacitors results in the capacitors having different capacitances without having large variations in the horizontal surface area used for each capacitor or multiple etch steps for the different depths. Therefore, the presented method is more cost effective and flexible than related methods of capacitor production.
An interconnect structure comprising an interlayer dielectric 108 is formed over a substrate 102. A first bottom electrode 112a, and a second bottom electrode 112b are formed over an upper surface 126 of the interlayer dielectric 108. In some embodiments, the first bottom electrode 112a and the second bottom electrode 112b are separated by a passivation layer 120 and are part of a first capacitor 104a and a second capacitor 104b, respectively.
A first dielectric 114a and a first top electrode 116a overly the first bottom electrode 112a. The first dielectric 114a separates the first bottom electrode 112a from the first top electrode 116a. A second dielectric 114b and a second top electrode 116b overly the second bottom electrode 112b. The second dielectric 114b separates the second bottom electrode 112b from the second top electrode 116b.
The first bottom electrode 112a has a first width w1 measured between outer sidewalls of the first bottom electrode 112a. The first bottom electrode 112a further has a first depth d1 measured from an upper surface 126 of the interlayer dielectric 108. The second bottom electrode 112a has a second width w2 measured between outer sidewalls of the second bottom electrode 112b. The second bottom electrode 112b further has a second depth d2 measured from an upper surface 126 of the interlayer dielectric 108. The first width w1 is greater than the second width w2, and the first depth d1 is greater than the second depth d2. The difference between the first depth d1 and the second depth d2 may be attributed to the difference in a magnitude of the etch-loading effect that occurs during an etching process before the formation of the first and second bottom electrodes 112a, 112b. The difference in the magnitude of the etch-loading effect is a result of the difference between the first width w1 and the second width w2, where a greater width results in a greater etch depth.
In some embodiments, the first width w1 is measured between outer sidewalls of a first bottom electrode structure 106a of the first bottom electrode 112a. Similarly, the second width w2 is measured between outer sidewalls of a second bottom electrode structure 106b of the second bottom electrode 112b. In further embodiments, the first depth d1 is measured from the upper surface 126 of the interlayer dielectric 108 to a bottom surface of the first bottom electrode structure 106a, and the second depth d2 is measured from the upper surface 126 of the interlayer dielectric 108 to a bottom surface of the second bottom electrode structure 106b. The first bottom electrode structure 106a extends from a first horizontal portion 130a of the first bottom electrode 112a overlying the upper surface 126 of the interlayer dielectric 108. The second bottom electrode structure 106b extends from a second horizontal portion 130b of the second bottom electrode 112b overlying the upper surface 126 of the interlayer dielectric 108. In some embodiments, the first horizontal portion 130a has a first area and the second horizontal portion 130b has a second area different from the first area. In some embodiments, the first bottom electrode structure 106a extends through one or more etch stop layers 110. In further embodiments, the second bottom electrode structure 106b does not extend through the one or more etch stop layers 110. In some embodiments, the first bottom electrode structure 106a and the second bottom electrode structure 106b are part of a single capacitor and are electrically coupled by a metal line (not shown) running continuously between the first bottom electrode structure 106a and the second bottom electrode structure 106b.
An anti-reflect coating (ARC) 118 overlies the first top electrode 116a and the second top electrode 116b. A passivation layer 120 conformally overlies the ARC 118, the first top electrode 116a, the second top electrode 116b, and the upper surface 126 of the interlayer dielectric 108. Additional dielectric layers 128 of the interlayer dielectric 108 are arranged above the passivation layer 120. A first wire level 124 is arranged in the additional dielectric layers 128. The first wire level 124 comprises wires 132 and vias 134 that are electrically coupled to the first capacitor 104a and the second capacitor 104b. In some embodiments, the first wire level 124 is separated from the additional dielectric layers 128 of the interlayer dielectric 108 by first barrier layers 122. In some embodiments, the first barrier layer 122 may comprise a metal-nitride such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination of the foregoing. In some embodiments, upper surfaces of the first bottom electrode 112a and the second bottom electrode 112b are electrically coupled to wires in the first wire level 124. In some embodiments, the upper surfaces are contacting the vias or the first barrier layers 122 surrounding the vias that are contacting the first wire level 124.
In some embodiments, the bottom surfaces of the first bottom electrode structure 106a and the second bottom electrode structure 106b are contacting second wire levels 202a, 202b, 202c beneath the bottom surfaces. By using the first wire level 124 to contact the first top electrode 116a and the second wire levels 202a, 202b, 202c to contact the first bottom electrode structure 106a, the embodiment reduces the horizontal area of the first capacitor 104a used to connect both electrodes to the first wire level 124. Lowering the horizontal area used by individual capacitors may increase the density of capacitors in the integrated chip.
In some embodiments, a third capacitor 104c may have a third bottom electrode structure 106c and a fourth bottom electrode structure 106d extending to the second wire levels 202a, 202b, 202c. A third dielectric 114c separates the third bottom electrode structure 106c and the fourth bottom electrode structure 106d from a third top electrode 116c. The third bottom electrode structure 106c and the fourth bottom electrode structure 106d both add to the capacitance of the third capacitor 104c. The variance in the number of bottom electrode structures extending from the first, second and third bottom electrodes 112a, 112b, 112c expands the variety of different profiles that may achieve similar capacitances, and extends the range of capacitances that may be provided using this method.
In some embodiments, the first bottom electrode structure 106a may have the first width w1 and the first depth d1, the second bottom electrode structure 106b may have the second width w2 and the second depth d2, and the third and fourth bottom electrode structures 106c, 106d may have a third width w3 and a third depth d3. The difference in depths of the bottom electrode structures correlates to the difference in widths of the bottom electrode structures. That is, the first bottom electrode structure 106a has the first width w1 which is greater than the second width w2 of the second bottom electrode structure 106b, and also has the first depth d1 which is greater than the second depth d2 of the second bottom electrode structure 106b. The difference in widths w1, w2 results in a difference in the magnitude of etch-loading effects during the forming of the first and second capacitor 104a, 104b, leading to different etch rates and different depths d1, d2 for the first and second capacitor 104a, 104b. Therefore, the difference between the first depth d1 and the second depth d2 is a result of the difference between the first width w1 and the second width w2. The third and fourth bottom electrode structures 106c, 106d have the third width w3 that is less than the second width w2, and therefore have the third depth d3 which is less than the second depth d2.
As shown in the cross-sectional view 300a of
In further embodiments, the second capacitor 104b may comprise the fourth bottom electrode structure 106d and a fifth bottom electrode structure 106e. The fourth bottom electrode structure 106d and the fifth bottom electrode structure may have a fourth width w4. That is, the fourth bottom electrode structure 106d may have a fourth width w4 that is substantially equal to the width of the fifth bottom electrode structure. The widths of the fourth bottom electrode structure 106d and the fifth bottom electrode structure 106e being substantially equal results in the depths of the fourth bottom electrode structure 106d and the fifth bottom electrode structure 106e being substantially equal. The fourth bottom electrode structure 106d and the fifth bottom electrode structure 106e have a fourth depth d4.
The first capacitor 104a and the second capacitor 104b may be part of a plurality of capacitors, which may respectively have a plurality of bottom electrode structures with depths different to the first, second, third, and fourth depths d1, d2, d3, d4. In some embodiments, the first bottom electrode structure 106a of the plurality of bottom electrode structures has a least width and a least depth. In further embodiments, bottom electrode structures of the plurality of bottom electrode structures with progressively greater widths up to a greatest width have progressively greater depths up to a greatest depth. In further embodiments, a second bottom electrode structure (e.g., the second bottom electrode structure 106b) of the plurality of bottom electrode structures has a median depth of the plurality of different depths and a median width of the plurality of different widths. A plurality of top electrodes extend between inner sidewalls of the plurality of bottom electrode structures.
In some embodiments, the first width w1 is between 80 nanometers and 120 nanometers, 95 and 105 nanometers, or the like. In some embodiments, the first depth d1 is between 500 nanometers and 800 nanometers, 625 and 675 nanometers, or the like. In some embodiments, the second width w2 is between 130 nanometers and 170 nanometers, 145 and 155 nanometers, or the like. In some embodiments, the second depth d2 is between 1000 nanometers and 1300 nanometers, 1100 and 1150 nanometers, or the like. In some embodiments, the third width w3 is between 90 nanometers and 130 nanometers, 105 and 115 nanometers, or the like. In some embodiments, the third depth d3 is between 750 nanometers and 1050 nanometers, 900 and 950 nanometers, or the like. In other embodiments, different ranges of widths and depths are used for one or more bottom electrode structures, and result in capacitors with different capacitances and cross-sectional profiles.
As shown in the cross-sectional view 300b of
As shown in the cross-sectional view 300c of
In some embodiments, the maximum radii of curvature R1, R2, R3 correlate to the widths w1, w2, w3 of the plurality of bottom electrode structures 106a, 106b, 106c, such that the bottom electrode structure with the least width (e.g., the first bottom electrode structure 106a) has the lowest maximum radius of curvature (e.g., the first maximum radius of curvature R1). Further, the bottom electrode structure with the greatest width (e.g., the second bottom electrode structure 106b) has the highest maximum radius of curvature (e.g., the third maximum radius of curvature R3). The fourth bottom electrode structure 106d and the fifth bottom electrode structure 106e of the second capacitor 104b have substantially equal widths w4, and therefore have substantially equal maximum radii of curvature R4. The difference in maximum radii of curvature R1, R2, R3, R4 between the plurality of bottom electrode structures may be the result of differing etch rates between the trenches 308a, 308b (See
As shown in the cross-sectional view 300d of
The difference in thicknesses between the first thickness t1, the second thickness t2, and the third thickness t3 is based on the etch-loading effects present in the etching of the first and second trenches 308a, 308b surrounding the first thickness t1 and the second thickness t2. The etch rate of the interlayer dielectric 108 and the hard mask 302 is lower for a first trench 308a filled by the first bottom electrode structure 106a than a second trench 308b filled by the second bottom electrode structure 106b. The difference in etch rates is due to the first trench 308a having a first width w1 less than the second width w2 of the second trench 308b. The width w1 being less than the width w2 results in a lower amount of etchant reacting with the hard mask and the interlayer dielectric in the first trench 308a, which further results in the removal of less material near the opening of the first trench 308a compared to the second trench 308b. The removal of a greater amount of material at the opening of the second trench 308b may result in upper portions of the hard mask being removed. The portions of the hard mask 302 directly between the plurality of bottom electrode structures (e.g., between the first bottom electrode structure 106a and the second bottom electrode structure 106b) may be etched from multiple directions, which may lead to a greater amount of the hard mask being etched and lead to a decrease in the thickness of the hard mask 302 at those positions.
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As shown in cross-sectional view 500 of
As shown in cross-sectional view 600 of
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As shown in the cross-sectional view 1000 of
As shown in the cross-sectional view 1100 of
While method 1200 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.
At 1202, an interlayer dielectric is formed over a substrate.
At 1204, a photoresist is deposited over an upper surface of the interlayer dielectric.
At 1206, the photoresist is patterned, resulting in a first opening and a second opening in the photoresist, the first opening having a first width and the second opening having a second width less than the first width.
At 1208, the dielectric is etched using a single etching process, resulting in a first trench directly beneath the first opening and a second trench directly beneath the second opening.
At 1210, a first capacitor is formed in the first trench and a second capacitor is formed in the second trench, the first trench having a first depth and the second trench having a second depth less than the first depth.
Therefore, the present disclosure relates to a new method of forming an integrated chip having a plurality of capacitors with bottom electrode structures of different depths and widths.
Accordingly, in some embodiments, the present disclosure relates to an integrated device, including a substrate; an interconnect structure disposed over the substrate, the interconnect structure including an interlayer dielectric; a first bottom electrode structure disposed in the interlayer dielectric, the first bottom electrode structure having a first width as measured between outer sidewalls of the first bottom electrode structure and a first depth as measured from an upper surface of the interlayer dielectric; and a second bottom electrode structure disposed in the interlayer dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width as measured between outer sidewalls of the second bottom electrode structure and a second depth as measured from the upper surface of the interlayer dielectric; where the first width is greater than the second width and the first depth is greater than the second depth.
In other embodiments, the present disclosure relates to a capacitor array, including a plurality of capacitors arranged in an interconnect structure, the capacitors comprising horizontal portions of bottom electrodes arranged at a first elevation; a plurality of bottom electrode structures of the plurality of capacitors extending from the horizontal portions of the bottom electrodes, the plurality of bottom electrode structures extending to a plurality of different depths measured from the first elevation, including a least depth and a greatest depth of the plurality of different depths, and having a plurality of different widths measured between outer sidewalls of the plurality of bottom electrode structures, including a least width and a greatest width of the plurality of different widths; where a first bottom electrode structure of the plurality of bottom electrode structures has the least depth and the least width, and wherein bottom electrode structures of the plurality of bottom electrode structures with progressively greater depths up to the greatest depth have progressively greater widths up to the greatest width.
In yet other embodiments, the present disclosure relates to a method of forming capacitors in an integrated device, including forming a dielectric over a substrate; depositing a photoresist over an upper surface of the dielectric; patterning the photoresist, resulting in a first opening and a second opening in the photoresist, the first opening having a first width and the second opening having a second width less than the first width; etching the dielectric using a single etching process, resulting in a first trench directly beneath the first opening and a second trench directly beneath the second opening; and forming a first capacitor in the first trench and a second capacitor in the second trench, the first trench having a first depth and the second trench having a second depth less than the first depth.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
