The present invention relates to a cavity SOI substrate (C-SOI substrate) which is used in a MEMS (Micro Electro Mechanical Systems) device, for example, and in which a first silicon substrate having a cavity and a second silicon substrate are bonded to each other with a silicon oxide film interposed therebetween.
In one known structure, a Silicon on Insulator (hereinafter called an “SOI”) layer on which a device, such as a movable component, is to be formed and a wafer serving as a support substrate for supporting the SOI layer are bonded to each other with an insulating layer interposed therebetween, the insulating layer including a cavity (see, for example, Patent Document 1).
In another known structure, a cavity is formed in one of two silicon substrates constituting a cavity SOI substrate, and a silicon oxide film (SiO2) is formed in a bonded region between the two silicon substrates (see, for example, Patent Document 2).
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-14461
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2015-123547
Another problem is that, when the first silicon substrate and the second silicon substrate are bonded to each other, cracks tend to generate in the first silicon substrate at an edge defining the cavity.
In consideration of the above-described situation, an object of the present invention is to provide a cavity SOI substrate that can suppress deterioration of flatness in a portion of a second silicon substrate, the portion being oppositely aligned with the cavity in a first silicon substrate.
The present invention provides a cavity SOI substrate that includes a first silicon substrate having a cavity; a second silicon substrate bonded to the first silicon substrate, wherein the second silicon substrate includes a first portion oppositely aligned with the cavity of the first silicon substrate and that is thicker than a second portion of the second silicon substrate that is bonded to the first silicon substrate; and a silicon oxide film interposed between the first silicon substrate and the second silicon substrate.
The cavity SOI substrate according to the present invention can suppress deterioration of flatness of the second silicon substrate in the portion oppositely aligned with the cavity in the first silicon substrate.
According to a first aspect, there is provided a cavity SOI substrate that includes a first silicon substrate having a cavity; a second silicon substrate bonded to the first silicon substrate, wherein the second silicon substrate includes a first portion oppositely aligned with the cavity of the first silicon substrate and that is thicker than a second portion of the second silicon substrate that is bonded to the first silicon substrate; and a silicon oxide film interposed between the first silicon substrate and the second silicon substrate.
According to a second aspect, in the cavity SOI substrate, a surface of the second silicon substrate on a side thereof bonded to the first silicon substrate has a thickness that increases linearly in a direction from the second portion bonded to the first silicon substrate toward the first portion oppositely aligned with the cavity, and that a central region of the first portion oppositely aligned with the cavity includes a zone with a constant thickness.
According to a third aspect, in the cavity SOI substrate, a surface of the second silicon substrate on a side thereof bonded to the first silicon substrate has a curved shape with a thickness that increases in a direction from the second portion bonded to the first silicon substrate toward the first portion oppositely aligned with the cavity, and that a central region of the first portion oppositely aligned with the cavity includes a zone with a constant thickness.
According to a fourth aspect, in the cavity SOI substrate, a surface of the second silicon substrate on a side thereof bonded to the first silicon substrate has a thickness that increases in a direction from the second portion bonded to the first silicon substrate toward a central region of the first portion, the thickness being maximum in the central region of the first portion oppositely aligned with the cavity.
According to a fifth aspect, in the cavity SOI substrate, the second silicon substrate may be curved starting from a boundary region between bonded surfaces of both the first silicon substrate and the second silicon substrate toward a central region of the first portion oppositely aligned with the cavity.
Cavity SOI substrates according to embodiments of the present invention will be described below with reference to the accompanying drawings. It is to be noted that substantially the same members in the drawings are denoted by the same reference signs.
<Cavity SOI Substrate>
The cavity SOI substrates 20 and 20a according to Embodiment 1 of the present invention are each a cavity SOI substrate in which a first silicon substrate 1 having a cavity 5 and a second silicon substrate 8 are bonded to each other with a silicon oxide film 6a interposed therebetween. In the second silicon substrate 8, a cavity-aligned portion 11 oppositely aligned with the cavity 5 in the first silicon substrate 1 is thicker than a bonded portion 12 that is bonded to the first silicon substrate 1. More specifically, a thickness b of the cavity-aligned portion 11 oppositely aligned with the cavity 5 is greater than a thickness a of the bonded portion 12 (a<b). The cavity-aligned portion 11 includes a projected portion 22 with the thickness b being greater than that of a flat surface portion of the second silicon substrate 8.
The cavity-aligned portion 11 is not limited to the case in which the projected portion 22 with the thickness b being greater than in the flat surface portion is present on a lower surface of the second silicon substrate 8 positioned to directly face the cavity 5 (
According to the cavity SOI substrates 20 and 20a as described above, in the second silicon substrate 8, the cavity-aligned portion 11 oppositely aligned with the cavity 5 is less susceptible to deformation, and deterioration of flatness can be suppressed.
Members constituting the cavity SOI substrates 20 and 20a will be described below.
<First Silicon Substrate>
The first silicon substrate 1 has a first surface where the cavity 5 is formed, and a second surface positioned in an opposite relation to the first surface. Moreover, the first silicon substrate 1 is bonded to the second silicon substrate 8 with the silicon oxide film 6a interposed therebetween. Another silicon oxide film may be further formed on the second surface of the first silicon substrate 1. As an alternative, a silicon oxide film (for example, a thermally grown oxide film) may be formed on an entire surface of the first silicon substrate 1 including the inside of the cavity 5.
<Second Silicon Substrate>
The second silicon substrate 8 is bonded to the first silicon substrate 1 so as to face the cavity 5 in the first silicon substrate 1. In the second silicon substrate 8, as described above, the cavity-aligned portion 11 oppositely aligned with the cavity 5 in the first silicon substrate 1 is thicker than the bonded portion 12 that is bonded to the first silicon substrate 1. In other words, the thickness b of the cavity-aligned portion 11 is greater than the thickness a of the bonded portion 12 (a<b). The thicknesses a and b are set depending on various conditions.
The first silicon substrate 1 and the second silicon substrate 8 may be bonded by, for example, direct bonding with a process called FUSION BONDING described later. A bonding method is not limited to that case.
<Manufacturing Method for Cavity SOI Substrate>
(1) The first silicon substrate 1 serving as a base substrate is prepared (
(2) The first silicon substrate 1 is thermally oxidized (
(3) A resist pattern 3 is formed on the silicon oxide film 2a by utilizing the photolithography technique (
(4) A portion of the silicon oxide film 2a, the portion being not covered with the resist pattern 3, and the silicon oxide film 2b are removed by wet etching (
(5) The resist pattern 3 is removed, for example, by ashing or with use of a resist peeling liquid (
(6) The cavity 5 is formed in the first surface of the first silicon substrate 1 by DRIE (Deep Reactive-Ion Etching) (
(7) The silicon oxide film 2a is removed by the wet etching using hydrogen fluoride or BHF (
(8) The first silicon substrate 1 is thermally oxidized. With this step, a silicon oxide film 6 to perform the FUSION BONDING is formed on the first silicon substrate 1 (
(9) A thickness of the silicon oxide film 6 is adjusted as appropriate, and the second silicon substrate 8 serving as a device substrate is prepared. A preparation step for the second silicon substrate 8 will be described later.
(10) The FUSION BONDING is performed through the steps of washing the first silicon substrate 1 having the cavity 5, which has been obtained through the above-described steps, together with the second silicon substrate 8 as appropriate, carrying out an activation process, and bonding the first silicon substrate 1 having the cavity 5 and the second silicon substrate 8 to each other.
The FUSION BONDING can be implemented through, for example, the following steps.
a) At least one of the first surface of the first silicon substrate 1 and a bonding surface of the second silicon substrate 8 is hydrophilized to form a water film.
b) The first surface of the first silicon substrate 1 and the bonding surface of the second silicon substrate 8 are temporarily bonded by a force of the water film present on the at least one substrate surface.
c) The first silicon substrate 1 and the second silicon substrate 8 are heated in a temporarily bonded state.
d) When reaching about 200° C., water and oxygen are purged out from an interface between the first surface of the first silicon substrate 1 and the bonding surface of the second silicon substrate 8, whereby the bonding at the interface turns to hydrogen bonding. As a result, bonding strength between the first surface of the first silicon substrate 1 and the bonding surface of the second silicon substrate 8 is increased.
e) During a period until reaching about 600° C., voids generating at the interface between the first surface of the first silicon substrate 1 and the bonding surface of the second silicon substrate 8 increases because water and oxygen are purged out.
f) When the temperature is raised to about 1000° C., water and oxygen are diffused into Si and voids are no longer present at the interface between the first surface of the first silicon substrate 1 and the bonding surface of the second silicon substrate 8. Hence the bonding strength between the first surface of the first silicon substrate 1 and the bonding surface of the second silicon substrate 8 is further increased.
In such a manner, the direct bonding between the first silicon substrate 1 and the second silicon substrate 8 can be realized. A method for realizing the direct bonding is not limited to the above-described steps and may be selected as appropriate insofar as the direct bonding can be realized.
(11) Then, an annealing process is performed in an atmosphere containing oxygen at 1000° C. to increase the bonding strength between the first surface of the first silicon substrate 1 and the bonding surface of the second silicon substrate 8, whereby the cavity SOI substrate 20 is obtained (
<Preparation Step of Second Silicon Substrate 8>
(a) First, the resist pattern 21 in the reverse tapered shape is formed on the one surface of the second silicon substrate 8 (
(b) Then, the one surface of the second silicon substrate 8 is processed by dry etching such that a central portion of the second silicon substrate 8, the central portion being oppositely aligned with the cavity 5 in the first silicon substrate 1 is thicker than a peripheral portion thereof (
The second silicon substrate 8 including the projected portion 22 in the cavity-aligned portion oppositely aligned with the cavity is obtained through the above-described steps (
According to the cavity SOI substrates 20 and 20a, in the second silicon substrate 8, the cavity-aligned portion 11 oppositely aligned with the cavity 5 in the first silicon substrate 1 is thicker than the bonded portion 12 that is bonded to the first silicon substrate 1. Therefore, even when a difference in air pressure exists between the inside of the cavity 5 in a vacuum state and the outside of the cavity 5 under an atmospheric pressure, the second silicon substrate 8 is less susceptible to deformation. As a result, deterioration of flatness in each of the cavity SOI (C-SOI) substrates 20 and 20a can be prevented.
Furthermore, since the thickness of the projected portion 22 formed in the central portion of the second silicon substrate 8 is controlled to be constant and shape control is uniformly carried out by the dry etching in the preparation step of the second silicon substrate 8, control of characteristics is easier to perform, and the yield can be increased.
<Cavity SOI Substrate>
Comparing with the cavity SOI substrate 20 according to Embodiment 1, the cavity SOI substrate 20b according to Embodiment 2 of the present invention is different in that the projected portion 22 formed in the cavity-aligned portion 11 has a curved shape.
Stated in another way, the one surface of the second silicon substrate 8 on the side bonded to the first silicon substrate 1 is formed such that the second silicon substrate 8 has a curved shape with a thickness increasing in a direction from a portion bonded to the first silicon substrate 1 toward a central portion, and that a central region of a portion oppositely aligned with the cavity 5 has a constant thickness.
Thus, since, in the second silicon substrate 8, the shape of the projected portion 22 is curved starting from a boundary region between the projected portion 22 and the bonded portion 12, the generation of cracks can be suppressed when the first silicon substrate 1 and the second silicon substrate 8 are bonded to each other, and the yield can be increased. Furthermore, by controlling the thickness and the shape of the second silicon substrate 8 in a combined manner, characteristics can be made easier to control.
<Manufacturing Method for Cavity SOI Substrate>
Comparing with the manufacturing method for the cavity SOI substrate 20 according to Embodiment 1, a manufacturing method for the cavity SOI substrate 20b according to Embodiment 2 of the present invention is different in the preparation step of the second silicon substrate. Other steps are substantially the same as those in the manufacturing method for the cavity SOI substrate according to Embodiment 1, and description of the other steps is omitted.
<Preparation Step of Second Silicon Substrate 8>
(a) First, a mask pattern 21 is formed using, for example, a silicon oxide film on the one surface of the second silicon substrate 8 (
(b) Then, the one surface of the second silicon substrate 8 on a side where the mask pattern 21 is formed is processed by the chemical mechanical polishing (CMP) such that a central portion of the second silicon substrate 8 is thicker than a peripheral portion thereof (
The second silicon substrate 8 with the projected portion 22 having the curved shape 25 and positioned in the cavity-aligned portion oppositely aligned with the cavity is obtained through the above-described steps (
According to the cavity SOI substrate 20b including the second silicon substrate 8 obtained as described above, the cavity-aligned portion 11 oppositely aligned with the cavity 5 in the first silicon substrate 1 is thicker than the bonded portion 12 that is bonded to the first silicon substrate 1. Therefore, even when a difference in air pressure exists between the inside of the cavity 5 in a vacuum state and the outside of the cavity 5 under an atmospheric pressure, the second silicon substrate 8 is less susceptible to deformation. As a result, deterioration of flatness of the cavity SOI (C-SOI) substrate 20b can be prevented. Furthermore, since the second silicon substrate 8 is curved starting from a boundary region between bonded surfaces of both the first silicon substrate 1 and the second silicon substrate 8, the generation of cracks can be suppressed when both the substrates are bonded to each other, and the yield can be increased.
<Cavity SOI Substrate>
Comparing with the cavity SOI substrates 20 and 20b according to Embodiments 1 and 2, the cavity SOI substrate 20c according to Embodiment 3 of the present invention is different in that the second silicon substrate 8 includes the projected portion 22 on each of a lower surface of the second silicon substrate 8, the lower surface being positioned to directly face the cavity 5 in the first silicon substrate 1, and an upper surface of the second silicon substrate 8, the upper surface being positioned not to directly face the cavity 5.
Stated in another way, on each of the lower surface of the second silicon substrate 8 on a side bonded to the first silicon substrate 1 and the upper surface of the second silicon substrate 8 on a side not bonded to the first silicon substrate 1, the second silicon substrate 8 includes the projected portion 22 with a thickness increasing in a direction from a portion bonded to the first silicon substrate 1 toward a central portion, the thickness being maximum in a central region of a portion oppositely aligned with the cavity 5.
<Manufacturing Method for Cavity SOI Substrate>
Comparing with the manufacturing methods for the cavity SOI substrates 20 and 20b according to Embodiments 1 and 2, a manufacturing method for the cavity SOI substrate 20c according to Embodiment 3 of the present invention is different in that the projected portion 22 is not previously formed in the preparation step of the second silicon substrate 8. In other words, the manufacturing method for the cavity SOI substrate 20c according to Embodiment 3 is different from the manufacturing methods for the cavity SOI substrates 20 and 20b according to Embodiments 1 and 2 in that, after bonding the first silicon substrate 1 and the second silicon substrate 8 to each other, polishing is carried out in a state under application of pressure. Other steps are substantially the same as those in the manufacturing method for the cavity SOI substrate 20 according to Embodiment 1, and description of the other steps is omitted.
(i) First, the cavity SOI (C-SOI) substrate is fabricated in a similar manner to that in Embodiments 1 and 2.
(ii) Then, the one surface of the second silicon substrate 8 on the side not bonded to the first silicon substrate 1 is polished in a state under application of pressure F (
(iii) Then, the pressure is released and the cavity SOI substrate 20c is obtained (
Through the above-described steps, the cavity SOI substrate 20c can be obtained in which the second silicon substrate 8 includes the projected portion 22 on each of the lower surface of the second silicon substrate 8 on the side positioned to directly face the cavity 5 in the first silicon substrate 1 and the upper surface of the second silicon substrate 8 on the side positioned not to directly face the cavity 5 in the first silicon substrate 1.
The cavity SOI substrate 20c according to Embodiment 3 can be manufactured by a simpler method than those according to Embodiments 1 and 2. As a result, the manufacturing cost can be reduced.
It is to be noted that the present disclosure may further include appropriate combinations of optionally selected features among the above-described embodiments and/or examples, and that those combinations can also provide similar advantageous effects to those obtained by the above-described embodiments and/or examples.
The cavity SOI substrate according to the present invention can be applied to MEMS devices.
1 first silicon substrate
2
a silicon oxide film
2
b silicon oxide film
3 resist pattern
4 opening
5 cavity
6 silicon oxide film
6
a silicon oxide film
6
b silicon oxide film
6
c silicon oxide film
7 resist pattern
8 second silicon substrate
11 cavity-aligned portion
12 bonded portion
20, 20a, 20b, 20c cavity SOI substrate
21 resist pattern
22 projected portion
23 end zone
24 mask pattern
50 cavity SOI substrate
51 first silicon substrate
55 cavity
56 silicon oxide film
58 second silicon substrate
61 cavity-aligned portion
62 bonded portion
Number | Date | Country | Kind |
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2019-091300 | May 2019 | JP | national |
The present application is a continuation of International application No. PCT/JP2020/012496, filed Mar. 19, 2020, which claims priority to Japanese Patent Application No. 2019-091300, filed May 14, 2019, the entire contents of each of which are incorporated herein by reference.
Number | Date | Country | |
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Parent | PCT/JP2020/012496 | Mar 2020 | US |
Child | 17481447 | US |