Claims
- 1. A chip mounting device comprising:a first recognition mark on a chip-retainable head side and a second recognition mark on a substrate-retainable stage side, said first and second recognition marks being vertically apart from each other; a first recognition means for recognizing said first recognition mark and a second recognition means for recognizing said second recognition mark; a third recognition means for recognizing said first and second recognition marks concurrently when said first recognition mark is brought close to or into contact with said second recognition mark; and a temperature detection means for detecting a beyond-allowance temperature change to output a signal for initiating a calibration based on the concurrent recognition of said recognition marks.
- 2. The chip mounting device according to claim 1, wherein said first recognition mark is provided on said head and said second recognition mark is provided on said stage.
- 3. The chip mounting device according to claim 2, wherein a suction hole provided on said head for retaining a chip is formed as said first recognition mark.
- 4. The chip mounting device according to claim 1, wherein said first recognition mark is provided on said head and said second recognition mark is provided on a substrate retained by said stage.
- 5. The chip mounting device according to claim 4, wherein a suction hole provided on said head for retaining a chip formed as said first recognition mark.
- 6. The chip mounting device according to claim 1, wherein said first recognition mark is provided on a chip retained by said head and said second recognition mark is provided on said stage.
- 7. The chip mounting device according to claim 1, wherein said first recognition mark is provided on a chip retained by said head and said second recognition mark is provided on a substrate retained by said stage.
- 8. The chip mounting device according to claim 1, wherein said first recognition means and said second recognition means are provided so as to be moved integrally.
- 9. The chip mounting device according to claim 1, wherein said temperature detection means is attached to said first recognition means or said second recognition means.
- 10. The chip mounting device according to claim 1, wherein said head is provided movably only in a vertical direction.
- 11. The chip mounting device according to claim 1, wherein said head has a heater.
- 12. The chip mounting device according to claim 1, wherein said stage is provided movably.
- 13. The chip mounting device according to claim 1, wherein said stage is provided movably at a condition of parallel translation and/or rotatably.
- 14. A calibration method in a chip mounting device comprising the steps of:recognizing a first recognition mark on a chip-retainable head side and a second recognition mark on a substrate-retainable stage side, said first and second recognition marks being vertically apart from each other; bringing said first recognition mark close to or into contact with said second recognition mark; concurrently recognizing said first and second recognition marks which have been brought close to or into contact with each other; and detecting a beyond-allowance temperature change to output a signal for initiating a calibration based on the concurrent recognition of said recognition marks.
- 15. A calibration method in a chip mounting device comprising the steps of:concurrently recognizing a first recognition mark on a chip-retainable head side and a second recognition mark on a substrate-retainable stage side, said first and second recognition marks being vertically apart from each other; and detecting a beyond-allowance temperature change to output a signal for initiating a calibration based on the concurrent recognition of said recognition marks.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2000-279454 |
Sep 2000 |
JP |
|
Parent Case Info
This application is the national phase under 35 U.S.C. 371 of PCT Internation Application No. PCT/JP01/07742, which has an International filing date of Sep. 6, 2001, which designated the United States of America and which claims priority on Japanese Patent Application number 2000-279454, filed Sep. 14, 2000.
PCT Information
Filing Document |
Filing Date |
Country |
Kind |
PCT/JP01/07742 |
|
WO |
00 |
Publishing Document |
Publishing Date |
Country |
Kind |
WO02/25720 |
3/28/2002 |
WO |
A |
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5225026 |
Ozawa et al. |
Jul 1993 |
A |
Foreign Referenced Citations (4)
Number |
Date |
Country |
11-87432 |
Mar 1999 |
JP |
2000-269241 |
Sep 2000 |
JP |
2000-269242 |
Sep 2000 |
JP |
2001-102397 |
Apr 2001 |
JP |
Non-Patent Literature Citations (3)
Entry |
English Language Translation of JP 2000-269241 (Reference submitted in IDS).* |
English Language Translation of JP 2000-269242 (Reference submitted in IDS).* |
English Language Translation of JP 2001-102397 (Reference submitted in IDS). |