Patent Application
20070187821
The present invention relates to a chip having a bump structure, and more particularly, to a structure of bumps that includes metal terminals for the electrical connections of the chip.
For conventional chips with bumps using for integrated circuit (IC), chips include metallized portions formed by semiconductor processes for electrically outputting/inputting bonding pads thereof, and bumps are electrically connected to the metallized portions for outputting/inputting the same. In order to accommodate to the probes in chip test systems or bonding wire devices in chip package processes, bumps of such chips usually have large flat areas for ensuring the reliabilities during testing or wiring. However, the chip size becomes smaller due to the development of semiconductor technology. The distances between the bonding pads thus become closer to fabricate the minimized chips. Unfortunately, the sizes of chips are limited by test instruments and wire bonding devices. Therefore, an improved bump structure that reduces the areas of chips is provided by the applicants to overcome the aforesaid disadvantages.
It is the primary object of the invention to provide a chip with a bump structure that serves as electrical terminals for the chip.
It is another object of the invention to provide a chip with a bump structure, in which bumps for electrical input/output of the chip are arranged compactly.
In accordance with the objects of the invention, a chip having a bump structure is provided. The structure comprises a chip, a plurality of pads and a plurality of bumps. The chip includes a microcircuit manufactured by integrated circuit technique. The pads are metallized portions of the chip for electrical connections. The bumps are metal bulges on the pads of the chip for electrically connecting the pads with terminals of other components. The bumps are arranged in a horizontal direction, and each of the bumps includes a first section and a second section, wherein the first section and the second section are electrically connected to each other along a vertical direction. The first section electrically contacts the pad. The size of the second section in the horizontal direction is larger than that of the first section. The second section is used for electrically connecting the chip to other components. The first section and the second section of adjacent bumps are interlaced.
Additionally, the bump may include a strip-shaped first section and a circular second section, which are electrically connected with each other. Alternatively, the bump may be a trapezoid form, part of which is defined as the first section and the second section.
The foregoing aspects, as well as many of the attendant advantages and features of this invention will become more apparent by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
The aforesaid bumps 3 are arranged in a horizontal direction 4. Each of the bumps 3 includes a first section 31 and a second section 32. The first section 31 and the second section 32 are electrically connected to each other. The first section 31 electrically contacts the corresponding pad 2 of the chip 1. The size of the second section 32 in the horizontal direction 4 is larger than that of the first section 31. The second section 32 is used to connect the chip 1 to terminals of other components. For example, the second section 32 is electrically connected with other components through bonding wire. A first vertical direction 5 is defined from the first section 31 to the second section 32, and a second vertical direction 6 is defined from the second section 32 to the first section 31. The first vertical direction 5 and the second vertical direction 6 are perpendicular to the horizontal direction 4, and the first sections 31 and the second sections 32 of adjacent bumps 3 are interlaced. Hence, the adjacent bumps 3 are interlaced in the first vertical direction 5 and the second vertical direction 6. According to the deployment of the first sections 31 and the second sections 32 of the bumps 3, the interval between the bumps 3 is closer in such a way that the area of the chip is reduced.
Each of the bumps 3 includes a smaller horizontal size at one end along the vertical direction, and a larger horizontal size at the other end. Two ends of the bumps 3 separately with relatively small size and large size are reversed, so as to compact the arrangement of the bumps 3. Consequently, bumps 3 occupy less flat space, and the area of the chip 1 is reduced.
Moreover, the embodiments described above are exemplars only, and those skilled in the art may modify the profiles of the first sections 31 and the second sections 32 of the bumps 3, which will not depart from the scope of the invention.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, these are, of course, merely examples to help clarify the invention and are not intended to limit the invention. It will be understood by those skilled in the art that various changes, modifications, and alterations in form and details may be made therein without departing from the spirit and scope of the invention, as set forth in the following claims.
