Patent Application
20240215159
This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0184350 filed in the Korean Intellectual Property Office on Dec. 26, 2022, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a circuit board and a manufacturing method thereof.
Recently, a system in package (SIP) has been used to implement a high-performance central processing unit (CPU) by bundling two or more ICs into one package to operate as a single chip. Since a memory is mounted together on one circuit board, a silicon interposer is applied to the SIP. Accordingly, a size of the circuit board increases so that a defect due to warpage is likely to occur.
In addition, a thin package is required in the high-performance central processing unit (CPU), and a coreless substrate without a core member having a predetermined thickness is used for this purpose. Since the coreless substrate does not have the core member, the coreless substrate may be formed thin while forming more layers when the coreless substrate is compared with a circuit board having the same thickness, but the defect due to warpage is likely to occur.
When the package is assembled, the defect due to warpage that occurs in the coreless substrate includes a crack that occurs in a bump when a die and the bump are connected, a crack that occurs in a via layer due to thermal stress, a solder bridge where solder balls are shorted, or the like.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Embodiments are to provide a circuit board and a manufacturing method thereof capable of minimizing a defect due to warpage such as bending, twisting, or the like.
However, problems to be solved by the embodiments are not limited to the above-described problem and may be variously extended in a range of technical ideas included in the embodiments.
A circuit board according to an embodiment includes: a first insulating layer; a conductive pad that protrudes above a surface of the first insulating layer; and a second insulating layer that includes a material different from the first insulating layer, is disposed below the first insulating layer, and includes a reinforcing material. A corner of the conductive pad has a curved shape.
A portion of the conductive pad may be buried in the first insulating layer.
The circuit board may further include: a first via layer disposed at the first insulating layer; first circuit wiring connected to the first via layer; a second via layer disposed at the second insulating layer; and second circuit wiring connected to the second via layer. The conductive pad may be connected to the first via layer.
The corner of the conductive pad having the curved shape may be an upper corner of the conductive pad, and each of a corner of the first circuit wiring and a corner of the second circuit wiring may have an angular shape.
A radius of curvature of the corner of the conductive pad may be greater than a radius of curvature of a corner of the first circuit wiring or a radius of curvature of a corner of the second circuit wiring.
The circuit board may further include a solder resist layer that is disposed below the second insulating layer and has an opening overlapping the second circuit wiring.
The circuit board may further include: a first auxiliary pad covering the conductive pad; and a second auxiliary pad covering a surface of the second circuit wiring overlapping the opening.
Each of the first auxiliary pad and the second auxiliary pad may include a plating layer.
A minimum diameter of the second via layer may be greater than a minimum diameter of the first via layer.
The first insulating layer may include a silica filler, the second insulating layer may include a silica filler and the reinforcing material, and the reinforcing material may include a glass cloth.
The first insulating layer may not include the reinforcing material.
The corner of the conductive pad having the curved shape may protrude from the first insulating layer, and a radius of curvature of the corner of the conductive pad protruding from the first insulating layer may be greater than a radius of curvature of a corner of the conductive pad embedded in the first insulating layer.
A manufacturing method of a circuit board according to an embodiment includes: forming a conductive pad on a carrier substrate; forming a first insulating layer that covers the conductive pad on the carrier substrate; forming a second insulating layer that includes a reinforcing material on the first insulating layer; separating the carrier substrate from the first insulating layer; etching a surface of the first insulating layer to make the conductive pad protrude above the surface of the first insulating layer; and processing a corner of the conductive pad to make the corner of the conductive pad into a curved shape.
The manufacturing method may further include: forming a first via layer penetrating the first insulating layer; forming first circuit wiring connected to the first via layer on the first insulating layer; forming a second via layer penetrating the second insulating layer; and forming second circuit wiring connected to the second via layer on the second insulating layer.
A minimum diameter of the second via layer may be larger than a minimum diameter of the first via layer.
The manufacturing method may further include: forming a solder resist layer having an opening overlapping the second circuit wiring on the second insulating layer; and simultaneously forming a first auxiliary pad covering the conductive pad and a second auxiliary pad covering a surface of the second circuit wiring overlapping the opening using a plating process.
The manufacturing method may further include turning over the first insulating layer and the second insulating layer separated from the carrier substrate.
An upper corner of the conductive pad may be formed to have a curved shape.
A circuit board according to an embodiment includes: a first insulating layer; and a conductive pad including a portion protruding from the first insulating layer and another portion embedded in the first insulating layer. A corner of the portion of the conductive pad protruding from the first insulating layer has a radius of curvature greater than that of a corner of the another portion of the conductive pad embedded in the first insulating layer.
The circuit board may further include: a second insulating layer disposed below the first insulating layer and including a reinforcing material; a first via disposed in the first insulating layer; first circuit wiring connected to the conductive pad through the first via; a second via disposed in the second insulating layer; and second circuit wiring connected to the first circuit wiring through the second via.
The radius of curvature of the corner of the portion of the conductive pad protruding from the first insulating layer may be greater than a radius of curvature of a corner of the first circuit wiring or a radius of curvature of a corner of the second circuit wiring.
The circuit board may further include a solder resist layer disposed below the second insulating layer and having opening overlapping the second circuit wiring.
The circuit board may further include: a first auxiliary pad covering the conductive pad; and a second auxiliary pad disposed in the opening to cover the second circuit wiring.
A minimum diameter of the second via may be greater than a minimum diameter of the first via.
According to the embodiments, some insulating layers of a coreless substrate may include a reinforcing material to prevent warpage of the coreless substrate in one direction.
In addition, since an upper corner of a conductive pad protruding from the coreless substrate has a curved shape, a defect such as a crack or the like in the conductive pad may be prevented even when warpage occurs in the coreless substrate.
In addition, diameters of some via layers penetrating some insulating layers including the reinforcing material may be formed larger than diameters of other via layers penetrating other insulating layers not including the reinforcing material, so that it is possible to prevent a defect such as a crack or the like from occurring in some via layers by stress concentrated in some insulating layers.
As described above, since reliability of a circuit board including the coreless substrate may be improved, thinning of a package may be improved.
It is obvious that an effect of the embodiments is not limited to the above-described effect, and may be variously extended without departing from the spirit and scope of the present disclosure.
The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.
In order to clearly describe the present disclosure, parts or portions that are irrelevant to the description are omitted, and identical or similar constituent elements throughout the specification are denoted by the same reference numerals.
Further, the accompanying drawings are provided only in order to allow embodiments disclosed in the present specification to be easily understood and are not to be interpreted as limiting the spirit disclosed in the present specification, and it is to be understood that the present disclosure includes all modifications, equivalents, and substitutions without departing from the scope and spirit of the present disclosure.
Further, in the drawings, the size and thickness of each element are arbitrarily illustrated for ease of description, and the present disclosure is not necessarily limited to those illustrated in the drawings. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, for ease of description, the thicknesses of some layers and areas are exaggerated.
It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being “on” or “above” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, in the specification, the word “on” or “above” means positioned on or below the object portion, and does not necessarily mean positioned on the upper side of the object portion based on a gravitational direction.
In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
Further, throughout the specification, the phrase “in a plan view” or “on a plane” means viewing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side.
Furthermore, throughout the specification, “connected” does not only mean when two or more elements are directly connected, but also when two or more elements are indirectly connected through other elements, and when they are physically connected or electrically connected, and further, it may be referred to by different names depending on a position or function, and may also be referred to as a case in which respective parts that are substantially integrated are linked to each other.
Hereinafter, various embodiments and variations will be described in detail with reference to the drawings.
Referring to
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The first layer portion 100 may be disposed above or on the second layer portion 200. The first layer portion 100 may include a first insulating layer 110, a first via layer 120, and first circuit wiring 130.
The first insulating layer 110 may include a thermosetting resin such as epoxy resin, polyimide, or the like, or a thermoplastic resin such as polyethylene (PE), polycarbonate (PC), polyvinyl chloride (PVC), or the like. For example, the first insulating layer 110 may include an Ajinomoto build-up film (ABF) or the like. The ABF may be a polymeric epoxy film available from Ajinomoto Fine-Techno Company, Inc. The first insulating layer 110 may include a silica filler.
The first via layer 120 may pass through the first insulating layer 110, and may be connected to the first circuit wiring 130. The first via layer 120 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like. A side surface of the first via layer 120 may be formed to be tapered. That is, the side surface of the first via layer 120 may have an obtuse angle with respect to a plane parallel to a surface of the first insulating layer 110.
The first circuit wiring 130 may be disposed below the first insulating layer 110, and may transmit an electrical signal. The first circuit wiring 130 may be disposed in various patterns. The first circuit wiring 130 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like.
In the present embodiment, three first layer portions 100 are stacked, but the present disclosure is not necessarily limited thereto, and various numbers of first layer portions 100 may be stacked.
The second layer portion 200 may include a second insulating layer 210, a second via layer 220, and second circuit wiring 230.
The second insulating layer 210 may include a thermosetting resin such as epoxy resin, polyimide, or the like, or a thermoplastic resin such as polyethylene (PE), polycarbonate (PC), polyvinyl chloride (PVC), or the like. For example, the second insulating layer 210 may include an Ajinomoto build-up film (ABF) or the like. The second insulating layer 210 may include a silica filler.
In addition, the second insulating layer 210 may further include a reinforcing material 211 capable of preventing warpage (or deformation) due to a physical external force. The reinforcing material 211 may include a glass cloth or the like. As described above, since the second insulating layer 210 includes the reinforcing material 211, warpage in one direction of the coreless substrate CLS due to thermal stress or the like during a manufacturing process may be prevented.
The second via layer 220 may pass through the second insulating layer 210, and may be connected to the second circuit wiring 230. The second via layer 220 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like. A side surface of the second via layer 220 may be formed to be tapered. That is, the side surface of the second via layer 220 may have an obtuse angle with respect to a plane parallel to a surface of the second insulating layer 210.
The second circuit wiring 230 may be disposed below the second insulating layer 210, and may transmit an electrical signal. The second circuit wiring 230 may be disposed in various patterns. The second circuit wiring 230 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), an alloy thereof, or the like.
In the present embodiment, two second layer portions 200 are stacked, but the present disclosure is not necessarily limited thereto, and various numbers of second layer portions 200 may be stacked.
The conductive pad 300 may be connected to the first circuit wiring 130 through the first via layer 120, and may protrude above a surface 110u of the first insulating layer 110. In addition, a lower surface of the conductive pad 300 may be buried within the first insulating layer 110.
The conductive pad 300 may be bonded to a solder bump 20 attached to a die 10 to transmit an electrical signal to the die 10. The conductive pad 300 may include a conductive material such as copper (Cu), gold (Au), silver (Ag), a double layer of nickel (Ni) and gold (Au), or the like.
In this case, an upper corner 300a of the conductive pad 300 protruding above the surface 110u of the first insulating layer 110 has a curved shape, and a lower corner 300b buried within the first insulating layer 110 may have an angular shape. Accordingly, a radius of curvature of the upper corner 300a of the conductive pad 300 may be greater than a radius of curvature of the lower corner 300b.
In addition, unlike a corner 130a of the first circuit wiring 130 and a corner 230a of the second circuit wiring 230 having an angular shape, the upper corner 300a of the conductive pad 300 has a curved shape. That is, the radius of curvature of the upper corner 300a of the conductive pad 300 may be greater than a radius of curvature of the corner 130a of the first circuit wiring 130 or a radius of curvature of the corner 230a of the second circuit wiring 230.
Therefore, since stress is not concentrated on the protruding upper corner 300a of the conductive pad 300 even when warpage occurs in the coreless substrate CLS, occurrence of a defect such as a crack or the like in the conductive pad 300 may be prevented.
The solder resist layer 400 may be disposed below the second insulating layer 210, and may cover the second circuit wiring 230. The solder resist layer 400 may have an opening (or an opening portion) OH overlapping the second circuit wiring 230 on a plane. The solder resist layer 400 may include an insulating material such as a solder resist or the like.
The first auxiliary pad 510 may cover the conductive pad 300. The first auxiliary pad 510 may include a plating layer. The plating layer may be formed by an electroless plating process, and may include gold (Au), silver (Ag), nickel (Ni), palladium (Pd), or the like.
The second auxiliary pad 520 may cover a surface of the second circuit wiring 230 overlapping the opening OH of the solder resist layer 400. The second auxiliary pad 520 may be adjacent to the second insulating layer 210. The second auxiliary pad 520 may include a plating layer. The plating layer is formed by a plating process and may include gold (Au), silver (Ag), nickel (Ni), palladium (Pd), or the like.
The second insulating layer 210 adjacent to the second auxiliary pad 520 includes the reinforcing material 211 to minimize warpage of the coreless substrate CLS so that solder balls 30 bonded to the second auxiliary pad 520 are prevented from being shorted each other.
As described above, in the circuit board according to the embodiment, the second insulating layer 210 of the coreless substrate CLS may include the reinforcing material 211, and the upper corner 300a of the protruding conductive pad 300 may have a curved shape. As a result, even when warpage occurs in the coreless substrate CLS, occurrence of a defect such as a crack or the like in the conductive pad 300, the second via layer 220, or the like may be minimized.
In one example, the first insulating layer 110 of the coreless substrate CLS may not include the reinforcing material 211, although the present disclosure is not limited thereto.
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As described above, since the second insulating layer 210 of the coreless substrate CLS includes the reinforcing material 211 in the embodiment, it is possible to prevent warpage in one direction of the coreless substrate CLS.
In addition, the upper corner 300a of the conductive pad 300 protruding from the coreless substrate CLS may have a curved shape so that occurrence of a defect such as a crack or the like in the conductive pad 300 is prevented even when warpage occurs in the coreless substrate CLS.
On the one hand, in the above embodiment, a minimum diameter of the first via layer and a minimum diameter of the second via layer are the same, but another embodiment in which the minimum diameter of the second via layer is larger than the minimum diameter of the first via layer is also possible.
Hereinafter, a circuit board according to another embodiment will be described in detail with reference to
The other embodiment shown in
As shown in
Here, a minimum diameter d2 of the second via layer 220 of the second layer portion 200 may be greater than a minimum diameter d1 of the first via layer 120 of the first layer portion 100.
As described above, the minimum diameter d2 of the second via layer 220 penetrating the second insulating layer 210 including the reinforcing material 211 may be formed larger than the minimum diameter d1 of the first via layer 120 penetrating the first insulating layer 110 not including the reinforcing material 211, so that a defect such as a crack or the like is prevented from occurring in the second via layer 220 by stress concentrated in the second insulating layer 210.
Referring to
The other embodiment shown in
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While this disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0184350 | Dec 2022 | KR | national |
