Patent Application
20240413073
The embodiment relates to a circuit board, and in particular, to a circuit board and semiconductor package comprising the same.
A printed circuit board (PCB) is formed by printing a circuit line pattern on an electrically insulating substrate with a conductive material such as copper, and refers to a board immediately before mounting electronic components. That is, in order to densely mount many types of electronic devices on a flat plate, it means a circuit board on which a mounting position of each part is determined and a circuit pattern connecting the parts is printed on the flat plate surface and fixed.
Components mounted on the printed circuit board may transmit a signal generated from the component by a circuit pattern connected to each component.
On the other hand, recent portable electronic devices and the like are becoming highly functional, in order to perform high-speed processing of large amounts of information, high-frequency signals are being developed, and accordingly, there is a demand for a circuit pattern of a printed circuit board suitable for high-frequency applications.
The circuit pattern of the printed circuit board should minimize signal transmission loss and enable signal transmission without deteriorating the quality of the high-frequency signal.
The transmission loss of a circuit pattern of a printed circuit board mainly consists of a conductor loss due a metal thin film such as copper and a dielectric loss such as an insulating layer.
The conductor loss due to the metal thin film is related to a surface roughness of the circuit pattern. That is, as the surface roughness of the circuit pattern increases, transmission loss may increase due to a skin effect.
Accordingly, when the surface roughness of the circuit pattern is reduced, there is an effect of preventing a reduction in transmission loss, but there is a problem in that the adhesion between the circuit pattern and the insulating layer is reduced.
In addition, a material having a low dielectric constant may be used as an insulating layer of the circuit board in order to reduce a dielectric constant.
However, in the circuit board for high frequency applications, the insulating layer requires chemical and mechanical properties for use in the circuit board in addition to the low dielectric constant.
In details, it should have isotropy of electrical properties for ease of circuit pattern design and process, low reactivity with metal wiring materials, low ionic conductivity, sufficient mechanical strength to withstand processes such as chemical mechanical polishing (CMP), low moisture absorption, which can prevent delamination or increase in dielectric constant, heat resistance that can overcome the processing temperature, a low coefficient of thermal expansion to eliminate cracking due to temperature change, and furthermore, various conditions such as adhesion, crack resistance, low stress, and low high-temperature gas generation to minimize various stresses and peeling that may be generated at the interface with other materials must be satisfied.
In addition, the insulating layer used in the circuit board for high-frequency applications must satisfy various conditions such as an adhesion property that can minimize various stresses and peeling that can occur at interfaces with other materials (eg, metal thin films), a crack resistance property, a low stress property, a low high-temperature gas generation property.
Accordingly, the insulating layer used in the circuit board for high frequency use preferentially must have low dielectric constant and low thermal expansion coefficient properties, and accordingly, an overall thickness of the circuit board can be reduced.
However, when a circuit board is manufactured using an insulating layer of a low dielectric constant material that is thinner than a threshold, this can cause reliability issues such as warping, cracking, and delamination. In addition, when the number of insulating layers of low dielectric material increases, reliability problems such as warping, cracking and delamination become more severe.
Therefore, there is a need for a method that can implement fine circuit patterns while slimming the circuit board using an insulating layer made of low dielectric material, and can also solve reliability problems such as warping, cracking, and peeling.
An embodiment provides a circuit board that can be slimmed and a semiconductor package including the same.
Additionally, the embodiment provides a circuit board capable of minimizing signal transmission loss and a semiconductor package including the same.
Additionally, the embodiment provides a circuit board with improved adhesion between an insulating layer and a circuit pattern layer and a semiconductor package including the same.
The technical problems to be achieved in the proposed embodiment are not limited to the technical problems mentioned above, and other technical problems not mentioned in the embodiments will be clearly understood by those of ordinary skill in the art to which the embodiments proposed from the description below.
A circuit board according to an embodiment includes an insulating layer; and a circuit pattern layer disposed on the insulating layer, wherein the insulating layer includes a surface layer containing fluorine (F), and the circuit pattern layer is disposed on the surface layer of the insulating layer.
In addition, the surface layer is a region ranging in depth from 10 nm to 100 nm from the surface of the insulating layer.
In addition, the surface layer includes a first portion adjacent to an upper surface of the insulating layer, and a second portion adjacent to a lower surface of the insulating layer.
In addition, the circuit pattern layer includes a first metal layer disposed on the surface layer of the insulating layer, and a second metal layer disposed on the first metal layer.
In addition, the first metal layer is an electroless plating layer, and the second metal layer is an electrolytic plating layer formed using the first metal layer as a seed layer.
In addition, the first metal layer has a thickness ranging from 1 um to 2.5 um.
In addition, a centerline average roughness value (Ra) of at least one of the first metal layer and the surface layer of the insulating layer satisfies a range between 200 nm and 600 nm.
In addition, a maximum section height value (Rt) of at least one of the first metal layer and the surface layer of the insulating layer satisfies the range of 2 um to 6 um.
In addition, the circuit board further comprises a through electrode disposed in a through hole passing through the insulating layer, wherein the surface layer of the insulating layer includes a third portion formed on an inner wall of the through hole, and wherein the through electrode includes a third metal layer disposed on the third portion of the surface layer; and, a fourth metal layer disposed on the third metal layer and filling the through hole.
Meanwhile, a circuit board according to another embodiment an insulating layer including through holes; and a through electrode disposed in the through hole of the insulating layer, wherein the insulating layer includes a surface layer corresponding to the inner wall of the through hole and containing fluorine (F), the through electrode includes a first metal layer disposed on the surface layer; and a second metal layer disposed on the first metal layer and filling the through hole.
In addition, the surface layer is a region with a horizontal depth ranging from 10 nm to 100 nm from the inner wall of the through hole of the insulating layer.
In addition, an atomic ratio of fluorine (F) in the surface layer satisfies a range of 10% to 50%.
In addition, the first metal layer has a thickness ranging from 1 um to 2.5 um, the centerline average roughness value (Ra) of at least one of the first metal layer and the surface layer satisfies a range between 200 nm and 600 nm, and a maximum section height value (Rt) of the surface of at least one of the first metal layer and the surface layer satisfies a range of 2 um to 6 um.
Meanwhile, a semiconductor package according to the embodiment comprises an insulating layer including through holes; a circuit pattern layer disposed on the insulating layer; a through electrode disposed within a through hole of the insulating layer; and a chip mounted on the circuit pattern layer, wherein the insulating layer includes a surface layer containing fluorine (F) including a first portion adjacent to the circuit pattern layer and a second portion adjacent to the through electrode, the circuit pattern layer includes a first metal layer disposed on the first portion of the surface layer, and a second metal layer disposed on the first metal layer, wherein the through electrode includes a third metal layer disposed on the second portion of the surface layer; and a fourth metal layer is disposed on the third metal layer to fill the through hole, the surface layer is a region with a depth ranging from 10 nm to 100 nm from the surface of the insulating layer, and an atomic ratio of fluorine (F) in the surface layer satisfies the range of 10% to 50%.
The circuit board in the embodiment comprises an insulating layer including a surface layer and a circuit pattern layer disposed on the insulating layer. The surface layer may mean a depth range of 10 nm to 100 nm from a surface of the insulating layer. The surface layer of the insulating layer contains fluorine. That is, the surface layer of the insulating layer contains carbon (C)—fluorine (F). At this time, the fluorine (F) can lower the polarity of a surface of the insulating layer.
That is, the embodiment allows the insulating layer to be plasma treated using CF4. At this time, the surface layer of the insulating layer before the plasma treatment includes a C—H bond portion. And, the C—H bond portion of the surface layer of the insulating layer after the plasma treatment is replaced with a C—F bond. In addition, C—F has lower electronic polarizability than C—H, and thus the polarity of the surface of the insulating layer can be lowered. At this time, as the usage frequency of the application to which the circuit board is applied increases, the signal flow moves to a surface of a conductor due to the skin effect. Therefore, the polarity of a dielectric surface in contact with the conductor is important. At this time, the embodiment allows fluorine (F) with low electrical polarity to be included in the surface layer within a certain depth range from the surface of the insulating layer, thereby minimizing signal transmission loss due to skin effect. As a result, communication performance can be improved.
Additionally, as the dielectric constant of the insulating layer or the polarity of the surface increases, signal loss increases and signal transmission speed decreases accordingly. At this time, the coefficient of thermal expansion and dielectric constant of the insulating layer are in a mutual trade-off relationship, and accordingly, when the polarity of the insulating layer is lowered, the coefficient thermal expansion of the insulating layer increases and the warpage characteristic accordingly deteriorates. At this time, the embodiment does not modify the polarity of the entire region of the insulating layer, but only performs polarity modification of the surface layer at a certain depth from the surface of the insulating layer through plasma treatment. Through this, the embodiment can modify only the polarity of the surface layer of the insulating layer while maintaining the coefficient of thermal expansion of the insulating layer. Accordingly, it is possible to minimize signal loss and increase signal transmission speed while maintaining the bending characteristics of the circuit board.
Additionally, the embodiment ensures that highly electronegative fluorine (F) is present in the surface layer of the insulating layer. At this time, the fluorine (F) can delocalize the distribution of electrons within the molecules of the insulating layer, thereby lowering the overall polarity of the polymer. Through this, the embodiment can lower a packing density of the polymer and increase a free volume, thereby lowering a dielectric constant of the insulating layer. Through this, high reliability can be maintained even in products that use high frequencies.
Meanwhile, the circuit pattern layer in the embodiment includes a first metal layer and a second metal layer. The first metal layer may have a thickness ranging from 1 um to 2.5 um. Preferably, the first metal layer may have a thickness ranging from 1.2 um to 2.3 um. Preferably, the first metal layer may have a thickness ranging from 1.4 um to 2.2 um. Through this, the embodiment can further improve the adhesion between the first metal layer and the insulating layer, and further improve the adhesion between the insulating layer and the circuit pattern layer. Through this, in the embodiment, the electrical reliability of the circuit pattern layer can be improved, and thus product satisfaction can be improved. In addition, the embodiment improves the adhesion between the insulating layer and the circuit pattern layer, so that the line width of the trace constituting the circuit pattern layer can be refined, and as a result, the circuit integration degree can be increased or the overall volume of the circuit board can be reduced.
Additionally, the centerline average roughness value (Ra) of the first metal layer in the embodiment may range between 200 nm and 600 nm. The centerline average roughness value (Ra) of the first metal layer may be 300 nm to 500 nm. Additionally, the maximum section height value (Rt) of the first metal layer may be 2 um to 6 um. For example, the maximum section height value (Rt) of the first metal layer may be 3 um to 5 um. In an embodiment, the centerline average roughness value (Ra) or maximum section height value (Rt) may be controlled to correspond to the thickness of the first metal layer, and accordingly, the anchoring effect can be further improved as the thickness of the first metal layer increases. Furthermore, the embodiment can improve the plating thickness uniformity of the first metal layer through control of the centerline average roughness value (Ra) and maximum section height value (Rt). Furthermore, when etching the first metal layer, the embodiment prevents a portion of the first metal layer from remaining on the surface of the insulating layer, thereby improving the electrical reliability of the circuit board and improving the yield of the circuit board.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the spirit and scope of the present invention is not limited to a part of the embodiments described, and may be implemented in various other forms, and within the spirit and scope of the present invention, one or more of the elements of the embodiments may be selectively combined and substituted for use.
In addition, unless expressly otherwise defined and described, the terms used in the embodiments of the present invention (including technical and scientific terms may be construed the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and the terms such as those defined in commonly used dictionaries may be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art.
Further, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular forms may also include the plural forms unless specifically stated in the phrase, and may include at least one of all combinations that may be combined in A, B, and C when described in “at least one (or more) of A (and), B, and C”.
Further, in describing the elements of the embodiments of the present invention, the terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the elements from other elements, and the terms are not limited to the essence or order of the elements.
In addition, when an element is described as being “connected”, “coupled”, or “contacted” to another element, it may include not only when the element is directly “connected” to, “coupled” to, or “contacted” to other elements, but also when the element is “connected”, “coupled”, or “contacted” by another element between the element and other elements.
In addition, when described as being formed or disposed “on (over)” or “under (below)” of each element, the “on (over)” or “under (below)” may include not only when two elements are directly connected to each other, but also when one or more other elements are formed or disposed between two elements.
Further, when expressed as “on (over)” or “under (below)”, it may include not only the upper direction but also the lower direction based on one element.
Before explaining the present embodiment, a circuit board according to a comparative example will first be described.
Referring to
For example, the circuit board of the first comparative example includes an insulating layer 10 including prepreg. At this time, the prepreg has a structure in which glass fibers are dispersed inside.
At this time, a base member for manufacturing the circuit board of the first comparative example has a structure in which a primer layer 20 is disposed on an insulating layer 10 and a copper foil layer 30 is laminated on the primer layer 20.
Meanwhile, a method of manufacturing the circuit board includes MSAP (Modified Semi Additive Process) and SAP (Semi Additive Process) methods. The MSAP method proceeds with a process of forming a circuit pattern layer with the copper foil layer 30 laminated, and the SAP method proceeds with the process of forming a circuit pattern layer after removing the copper foil layer 30.
At this time, in the MSAP method, a portion of the circuit pattern layer includes a copper foil layer 30. Accordingly, the MSAP method has limitations in reducing the width or spacing of wires in the circuit pattern layer, and thus has limitations in increasing circuit integration.
Meanwhile, in the case of manufacturing the circuit pattern layer using the SAP method in the first comparative example, a primer layer 20 must be included on the insulating layer 10 to ensure adhesion. Therefore, there is a problem that manufacturing costs increase or the overall thickness of the circuit board increases.
Furthermore, the prepreg used as the insulating layer 10 in the first comparative example contains glass fibers therein, it is difficult to reduce the thickness of the glass fiber. This is because the glass fibers included in the prepreg may come into contact with the circuit pattern layer disposed on the surface of the prepreg when the thickness of the prepreg decreases, resulting in a risk of cracking. Accordingly, when reducing the thickness of the prepreg, the circuit board in the first comparative example may have suffered dielectric breakdown and damage to the circuit pattern layer. Accordingly, the circuit board in the comparative example had a limit in reducing the overall thickness due to the thickness of the glass fibers constituting the prepreg.
Meanwhile, in the second comparative example, RCC (resin coated copper) is used to solve the problem of the first comparative example.
As shown in (a) of
At this time, as shown in (b) of
In the second comparative example, a chemical copper plating layer 60 is formed on the insulating layer 40 from which the copper foil layer 50 has been removed, and electroplating is performed using the chemical copper plating layer 60 as a seed layer to form a circuit pattern layer.
At this time, the chemical copper plating layer 60 in the second comparative example is disposed on the insulating layer 40 from which the copper foil layer 50 has been removed. That is, a lower surface of the chemical copper plating layer 60 is in direct contact with an upper surface of the insulating layer 40. The adhesion between the chemical copper plating layer 60 and the insulating layer 40 is affected by the line width of the trace of the circuit pattern formed using the chemical copper plating layer 60. At this time, if the line width of the trace is 10 um or less, there is a problem in that adhesion between the chemical copper plating layer 60 and the insulating layer 40 is not secured, and thus the trace is separated from the insulating layer 40.
In addition, the chemical copper plating layer 60 in the second comparative example has a thickness of less than 0.9 μm. However, when a thickness of the chemical copper plating layer 60 in the second comparative example is less than 0.9 μm, adhesion between the insulating layer 40 and the chemical copper plating layer 60 is not secured. Accordingly, when a certain force is applied in the trace shearing direction, there is a problem in that the circuit pattern layer disposed on the insulating layer 40 is separated or peeled from the insulating layer 40.
Accordingly, the embodiment allows to increase the signal transmission speed while minimizing signal transmission loss by lowering the polarity of the surface of the insulating layer. In addition, the embodiment increases the thickness of the chemical copper plating layer to improve the adhesion between the chemical copper plating layer and the insulating layer. Furthermore, the embodiment reduces the surface roughness of the insulating layer to minimize signal transmission loss. Furthermore, the embodiment allows one value to be determined depending on at least one of the surface roughness value of the insulating layer and the thickness of the chemical copper plating layer, thereby improving the overall reliability of the circuit board.
Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various semiconductor devices may be mounted on a package substrate. The semiconductor device may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as a central processor (e.g., CPU), graphics processor (e.g., GPU), antenna chip, digital signal processor, encryption processor, microprocessor, and microcontroller, logic chips such as analog-digital converters and application-specific ICs (ASIC).
In addition, the embodiment provides a circuit board and a semiconductor package that enable the pitch of the pad to be refined and to mount at least two different types of chips on one board according to the refinement of the pitch. Furthermore, the embodiment provides a circuit board and a semiconductor package that allow more traces to be placed between mounting pads having a smaller pitch than the comparative example.
In addition, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, or the like. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.
Referring to
The circuit board includes an insulating layer 110.
The insulating layer 110 may be RCC (Resin coated copper).
The insulating layer 110 may include a resin and a filler 111 dispersed in the resin. The insulating layer 110 may be a resin for a semiconductor package. The embodiment allows the dielectric constant of the insulating layer 110 to be lowered to 3.2Dk or less through a change in the content of the composition in the insulating layer 110 constituting the resin for the semiconductor package. Preferably, the embodiment allows the dielectric constant of the insulating layer 110 to be lowered to 3.0Dk or less through a change in the content of the composition in the insulating layer 110 constituting the resin for the semiconductor package. More preferably, the embodiment allows the dielectric constant of the insulating layer 110 to satisfy a range of 2.9Dk to 3.2Dk through a change in the content of the composition in the insulating layer 110 constituting the resin for the semiconductor package.
The insulating layer 110 is a composite of a resin and a filler 111. The insulating layer 110 may have a specific third dielectric constant due to a combination of a first dielectric constant of the resin and a second dielectric constant of the filler 111. In addition, the third dielectric constant may satisfy a range of 2.9Dk to 3.2Dk. Accordingly, the insulating layer 110 in the embodiment can be applied to a circuit board suitable for high frequency applications. Accordingly, the embodiment can minimize signal loss by the insulating layer 110 and solve the problem of exposing the filler 111 to the surface of the resin, and accordingly, the embodiment allows for improved reliability.
The resin may have a low dielectric constant. In this case, Table 1 shows a type of general resin and a dielectric constant according to the type of resin.
As described above, the resin may include various materials. In this case, the resin including phenolic, general epoxy, and cyanate has a dielectric constant (Dk) of 2.6 or more. In addition, the resin including PTFE has a low dielectric constant of about 2.2Dk, but a high process temperature condition is required. For example, a resin generally requires a process temperature of 250° C., but the PTFE requires a process temperature of 300° C. or more. In addition, the PTFE requires a bonding sheet during the lamination process to manufacture a multi-layered circuit board, which increases the overall thickness of the circuit board, causing problems in slimming the circuit board. Accordingly, the embodiment allows the dielectric constant of the resin of the insulating layer 110 to be lowered by using a modified epoxy or a maleimide series. However, the embodiment is not limited thereto, and the dielectric constant may be made including general epoxy or cyanate. In addition, the filler 111 may have a certain level of dielectric constant. For example, the filler 111 may be formed of a ceramic filler. In this case, Table 2 shows the dielectric constant according to the type of ceramic filler.
As described above, when the filler 111 is formed of Al2O3, the dielectric constant of the filler 111 is about 9.0 Dk, and accordingly, there is a limit to lowering the dielectric constant of the insulating layer 110, which is a composite of resin and filler, to 3.2 Dk or less only with the dielectric constant of the resin. Therefore, in the embodiment, the filler 111 is constructed using any one of SiO2, ZrO3, HfO2, and TiO2. Accordingly, the filler 111 may have a dielectric constant in a range of 3.7 to 4.2 Dk. On the other hand, the filler 111 can be divided into a plurality of groups based on a diameter. For example, the filler 111 may be divided into at least three groups based on their diameters. For example, the filler 111 may include a first filler group having a first diameter range, a second filler group having a second diameter range smaller than the first diameter range, and a third filler group having a third diameter range smaller than the second diameter range. Specifically, the filler 212 includes a first filler group having a first diameter, a second filler group having a second diameter smaller than the first diameter, and a third filler group having a third diameter smaller than the second diameter. In addition, the first diameter of the first filler group may satisfy the first diameter range. Also, the second diameter of the second filler group may satisfy the second diameter range. Also, the third diameter of the third filler group may satisfy the third diameter range. In the embodiment, when dispersing the filler 111 in the resin, the filler 111 is divided into at least three filler groups based on different diameter ranges, and the at least three filler groups are dispersed in the resin. Accordingly, the embodiment allows the insulating layer 110 to have a certain level of strength or higher while allowing the insulating layer 110 to have a low dielectric constant of 2.9 to 3.2Dk. Furthermore, the embodiment minimizes the exposure of the filler 111 after de-smearing under the condition that the insulating layer 110 has the dielectric constant and strength within the above range, thereby minimizing migration growth. In addition, the insulating layer 110 in the embodiment may have a coefficient of thermal expansion of 30 to 42 ppm.
To this end, the filler 111 may have a high content in the insulating layer 110. For example, a content of the filler 111 in the insulating layer 110 in the embodiment may be 68 wt % to 76 wt %. When the content of the filler 111 in the insulating layer 110 is smaller than 68 wt %, the insulating layer 110 may not have a certain level of strength or higher and may not have a coefficient of thermal expansion within the above range. In addition, when the content of the filler 111 in the insulating layer 110 is greater than 76 wt %, the insulating layer 110 may not have a low dielectric constant. Therefore, the embodiment allows the filler 111 in the insulating layer 110 to satisfy a range of 65 wt % to 76 wt %. Meanwhile, in the embodiment, the fillers 112 may be divided into a plurality of groups having different diameter ranges. Also, a plurality of groups of the filler 111 may have different contents.
For example, the filler 111 may be divided into at least three filler groups having different diameter ranges. Specifically, the filler 111 may include a first filler group having a first diameter range. The first diameter range of the first filler group may be 2 μm to 3.5 μm. A diameter of the first filler group may be greater than a diameter of other filler groups constituting the filler 111. For example, the first filler group may have a greatest diameter range among diameter ranges of at least three filler groups included in the filler 111. The filler 111 may include a second filler group having a second diameter range. The second diameter range of the second filler group may be 1 μm to 2 μm. The second filler group may be a filler group having a greatest content among filler groups constituting the filler 111. For example, the second filler group may include fillers having a medium diameter range among a plurality of filler groups constituting the filler 111. In addition, the second filler group having the medium diameter range may have a greatest content among the contents of each of the plurality of filler groups constituting the filler 111. The filler 111 may include a third filler group having a third diameter range. The third diameter range of the third filler group may be 0.5 μm to 1 μm. The third filler group of the first embodiment may include fillers with a smallest diameter range among a plurality of filler groups constituting the filler 111. The third filler group may control a direction of resin flow in the insulating layer 110 while maintaining the dielectric constant that the insulating layer 110 should have within the content range of the filler 111.
For example, the filler 111 as described above includes a first filler group 112a, a second filler group 112b, and a third filler group 112c. In this case, the resin flow between the filler 111 including the plurality of filler groups may be regular. For example, the first filler group in the embodiment has a greatest diameter range. Accordingly, the second filler group and the third filler group having a smaller diameter may be disposed between the fillers constituting the first filler group 112a. Therefore, in the embodiment, the resin flow may be performed along the second filler group and the third filler group between the first filler group having the greatest diameter in a state where the filler 111 including a plurality of filler groups as described above is provided.
The embodiment allows the first filler group to be included in the filler 111 in a range of 5 wt % to 20 wt %. When the content of the first filler group is less than 5 wt %, the insulating layer 110 may not have a certain level of rigidity. In addition, when the content of the first filler group is greater than 20 wt %, it may cause a problem that the filler is exposed to the surface of the insulating layer 110 in the de-smear process due to the increase in the content of the first filler group 112a. In addition, it can cause migration growth.
In addition, the embodiment allow the second filler group to be included in the filler 111 in a range of 60 wt % to 80 wt %. When the content of the second filler group is less than 60 wt %, the insulating layer 110 may not have a certain level of rigidity. In addition, when the content of the second filler group is greater than 80 wt %, the insulating layer 110 may not satisfy the required low dielectric constant. In addition, when the content of the second filler group is greater than 80 wt %, it may cause a problem that the filler is exposed to the surface of the insulating layer 110 in the de-smear process.
In addition, the embodiment allows the third filler group to have a content of 10 wt % to 30 wt % in the filler 111. When the content of the third filler group is less than 10 wt %, the content of the first filler group or the second filler group should be increased by the decrease in the content of the third filler group 112c, and accordingly, a reliability problem may occur. In addition, when the content of the third filler group is greater than 30 wt %, resin flowability may decrease as the content of the third filler group increases.
Meanwhile, although it has been described above that the filler 111 included in the insulating layer 110 is divided into at least three groups according to diameter, the embodiment is not limited thereto. For example, the diameters of the fillers 111 included in the insulating layer 110 may all be the same, or alternatively, they may be divided into two groups depending on the diameters.
The insulating layer 110 may have a thickness ranging from 10 μm to 30 μm. For example, the insulating layer 110 may have a thickness ranging from 15 μm to 25 μm.
Meanwhile, although it has been described above that the filler 111 in the insulating layer 110 is divided into at least three groups according to diameter, the present invention is not limited thereto. For example, the diameters of the fillers 111 included in the insulating layer 110 may all be the same, or alternatively, they may be divided into two groups depending on the diameters.
The insulating layer 110 includes a surface layer 110S. At this time, the surface layer 110S does not mean a layer separately laminated on the insulating layer 110, but may mean a region adjacent to a surface in an entire region of the insulating layer 110.
For example, the surface layer 110S of the insulating layer 110 may mean a region with a certain depth at a surface of the insulating layer 110. For example, the surface layer 110S of the insulating layer 110 may mean a depth region ranging from 10 nm to 100 nm at the surface of the insulating layer 110. For example, the surface layer 110S of the insulating layer 110 may refer to a depth region ranging from 12 nm to 70 nm at the surface of the insulating layer 110. For example, the surface layer 110S of the insulating layer 110 may mean a depth region ranging from 15 nm to 50 nm at the surface of the insulating layer 110.
The surface layer 110S of the insulating layer 110 may include a plurality of portions.
For example, the surface layer 110S of the insulating layer 110 may include a first portion 110TS adjacent to an upper surface of the insulating layer 110. For example, the surface layer 110S of the insulating layer 110 may include a second portion 110BS adjacent to a lower surface of the insulating layer 110. For example, the surface layer 110S of the insulating layer 110 may include a third portion 110WS adjacent to an inner wall of a through hole (not shown) of the insulating layer 110.
The first portion 110TS, the second portion 110BS, and the third portion 110WS of the surface layer 110S of the insulating layer 110 may each include fluorine (F). The first portion 110TS, the second portion 110BS, and the third portion 110WS may have substantially the same characteristics, and accordingly, will be described below as the surface layer 110S.
The surface layer 110S of the insulating layer 110 includes fluorine (F). That is, in the embodiment, plasma treatment is performed at the surface layer 110S corresponding to a certain depth region at the surface of the insulating layer 110. That is, in the embodiment, properties of the surface of the insulating layer 110 are modified by plasma treatment.
For example, as shown in (a) of
And, in the embodiment, as shown in (b) of
And, in an embodiment, when plasma treatment is performed on the surface of the insulating layer 110 using CF4, the surface layer 110S of the insulating layer 110 may be modified.
Specifically, when plasma processing is performed using CF4, C—H in the surface layer 110S of the insulating layer 110 may be replaced with C—F. Through this, in the embodiment, fluorine (F) may be included in the surface layer 110S of the insulating layer 110.
That is, the surface layer 110S with a depth ranging from 10 nm to 100 nm from the surface of the insulating layer 110 includes a carbon (C)—fluorine (F) bond portion. At this time, the fluorine (F) can lower the polarity of the surface of the insulating layer.
At this time, the C—F bond has lower electronic polarizability than the C—H bond, and thus the polarity of the surface of the insulating layer 110 can be lowered.
Specifically, as an usage frequency of the application to which the circuit board is applied increases, the signal flow moves to a surface of a conductor (circuit pattern layer) due to a skin effect.
Accordingly, the polarity of the surface layer 110S of the insulating layer 110 in contact with the conductor determines the overall communication performance of the circuit board.
That is, as shown in (a) of
And, as shown in (b) of
In addition, as shown in (c) of
Accordingly, the signal has the characteristic of flowing to the surface of the conductor as the frequency of the signal increases, and the polarity on the surface of the conductor is important.
Additionally, the polarity at the surface of the conductor substantially corresponds to the polarity at the surface layer 110S of the insulating layer 110 in contact with the conductor.
At this time, the polarity of the surface layer 110S of the insulating layer 110 containing fluorine (F) in the embodiment has a lower polarity than C—H before the plasma treatment. Accordingly, in the embodiment, plasma treatment is performed using CF4 so that the surface layer 110S of the insulating layer 110 includes fluorine (F) with low polarity. Accordingly, the embodiment can lower the polarity of the surface layer 110S of the insulating layer 110, thereby lowering the polarity of the surface of the circuit pattern layer compared to the comparative example. Through this, the signal transmission loss of the circuit pattern layer can be reduced and the signal transmission speed can be improved.
For example, the surface layer 110S includes a first portion 110TS, a second portion 110BS, and a third portion 110WS. Accordingly, the transmission loss of the signal flowing through the first circuit pattern layer 120, the second circuit pattern layer 130, and the through electrode 140 described below can be minimized. Additionally, signal transmission speed can be improved.
Meanwhile, the surface layer 110S in the embodiment may include a plurality of elements. For example, the surface layer of the insulating layer 110 in the embodiment may include carbon (C), oxygen (O), nitrogen (N), silicon (Si), and fluorine (F).
At this time, an atomic ratio of the plurality of elements in the surface layer 110S in the embodiment may be different from an atomic ratio in the existing surface layer before plasma treatment.
Here, the atomic ratio may mean a ratio between the numbers of each metal element included in the surface layer 110S.
The ratio of each element in the surface layer in the embodiment and comparative examples may be as shown in Table 3 below.
Meanwhile, Table 3 does not include element ratios for some elements, and accordingly, the surface layer in embodiment or comparative examples may contain elements other than the elements in Table 3. For example, the surface layer in the examples and comparative examples may further include at least one element selected from chromium (Cr), nickel (Ni), and zinc (Zn).
Referring to Table 3, it was confirmed that fluorine (F) was not detected in the surface layer of the insulating layer in the comparative examples 1 and 2.
Unlike this, in the embodiment, the plasma treatment was performed using CF4 on the surface layer of the insulating layer, accordingly, it was confirmed that fluorine (F) was detected in the surface layer.
At this time, the atomic ratio of fluorine (F) in the surface layer 110S in the embodiment may satisfy a range of 8% to 50%. Preferably, the atomic ratio of fluorine (F) in the surface layer 110S may satisfy the range of 9% to 40%. More preferably, the atomic ratio of fluorine (F) in the surface layer 110S may satisfy the range of 10% to 30%.
If the atomic ratio of fluorine (F) in the surface layer (110S) is less than 8%, the effect of reducing signal transmission loss of the circuit pattern layer due to the fluorine (F) may be minimal. This may make it difficult to apply to products that use high frequencies. Also, if the atomic ratio of fluorine (F) in the surface layer (110S) exceeds 50%, adhesion between the insulating layer 110 and circuit pattern layers or through electrodes due to the fluorine (F) may be reduced, and this may cause a reliability problem in which the circuit pattern layers or through electrodes are separated from the insulating layer.
As described above, in the embodiment, fluorine (F) with low electrical polarity is included in the surface layer 110S within a certain depth range from the surface of the insulating layer 110, thereby minimizing signal transmission loss due to skin effect. As a result, communication performance can be improved.
Meanwhile, as the dielectric constant or polarity of the insulating layer 110 increases, signal loss increases and signal transmission speed accordingly decreases. However, if the dielectric constant or polarity of the insulating layer 110 is lowered without any reference, the warpage characteristics of the insulating layer may be reduced accordingly.
Specifically, the thermal expansion coefficient and dielectric constant of the insulating layer 110 are in a mutual trade-off relationship, and accordingly, when the polarity of the insulating layer 110 is lowered, the thermal expansion coefficient of the insulating layer 110 increases, as a result, warpage characteristics decreases. At this time, in the embodiment, the polarity of the entire region of the insulating layer 110 is not modified, but only modifies the polarity of the surface layer 110S at a certain depth from the surface of the insulating layer 110 through plasma treatment. Through this, the embodiment can modify only the polarity of the surface layer 110S of the insulating layer 110 while maintaining the thermal expansion coefficient of the insulating layer 110, and accordingly, it is possible to minimize signal loss and increase signal transmission speed while maintaining the warpage characteristics of the circuit board.
Additionally, the fluorine (F) can delocalize the distribution of electrons within the molecules of the insulating layer, thereby lowering the overall polarity of the polymer. Through this, the embodiment can lower the packing density of the polymer and increase the free volume, thereby lowering the dielectric constant of the insulating layer 110. Therefore, the embodiment can maintain high reliability even in products that use high frequencies.
At this time, the signal transmission loss in the case where the surface layer of the insulating layer 110 in the embodiment includes fluorine (F) and when the fluorine (F) is not included is shown in Table 4 below.
Referring to Table 4, when fluorine (F) is included in the surface layer (110S) of the insulating layer 110 through plasma treatment as in the embodiment, it was confirmed that the signal transmission loss was lower than that before conventional plasma processing.
Meanwhile, a circuit pattern layer may be disposed on a surface of the insulating layer 110 in the embodiment.
For example, a first circuit pattern layer 120 may be disposed on an upper surface of the insulating layer 110 (preferably, the first portion of the surface layer of the insulating layer). Additionally, a second circuit pattern layer 130 may be disposed on a lower surface of the insulating layer 110 (preferably, the second portion of the surface layer of the insulating layer).
The first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed using a semi-additive process (SAP) method.
The first circuit pattern layer 120 and the second circuit pattern layer 130 may include traces and pads, respectively.
At this time, a line width of each trace of the first circuit pattern layer 120 and the second circuit pattern layer 130 may satisfy a range of 2 μm to 15 μm. For example, a line width of each trace of the first circuit pattern layer 120 and the second circuit pattern layer 130 may satisfy a range of 2.2 μm to 12 μm. For example, a width of each trace of the first circuit pattern layer 120 and the second circuit pattern layer 130 may satisfy a range of 2.5 μm to 10 μm.
Preferably, the traces of the first circuit pattern layer 120 and the second circuit pattern layer 130 may be fine patterns having a line width in the range of 2.5 μm to 10 μm.
Accordingly, fluorine (F) is included between the insulating layer 110 and the first circuit pattern layer 120, and between the insulating layer 110 and the second circuit pattern layer 130, and accordingly the embodiment can reduce signal transmission loss transmitted through the first circuit pattern layer 120 and the second circuit pattern layer 130.
In addition, the embodiment may control a surface roughness value and the thickness of each first metal layer of the first circuit pattern layer 120 and the second circuit pattern layer 130, which will be described below, and therefore, it is possible to improve the adhesion between the insulating layer 110 and the first circuit pattern layer 120 and the second circuit pattern layer 130.
The first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed of at least one metal material selected from among gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed of paste or solder paste including at least one metal material selected from among gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which are excellent in bonding force. Preferably, the first circuit pattern layer 120 and the second circuit pattern layer 130 may be formed of copper (Cu) having high electrical conductivity and a relatively low cost.
The first circuit pattern layer 120 and the second circuit pattern layer 130 may have a thickness ranging from 5 μm to 20 μm. For example, the first circuit pattern layer 120 and the second circuit pattern layer 130 may have a thickness ranging from 6 μm to 17 μm. The first circuit pattern layer 120 and the second circuit pattern layer 130 may have a thickness ranging from 7 μm to 13 μm. When the thickness of the first circuit pattern layer 120 and the second circuit pattern layer 130 is less than 5 μm, resistance may increase. If the thickness of the first circuit pattern layer 120 and the second circuit pattern layer 130 exceeds 20 μm, it may be difficult to refine the trace.
Meanwhile, the first circuit pattern layer 120 and the second circuit pattern layer 130 may each have a plurality of layer structures.
For example, the first circuit pattern layer 120 may include a first metal layer 121 and a second metal layer 122. Correspondingly, the second circuit pattern layer 130 may include a first metal layer 131 and a second metal layer 132. At this time, the first circuit pattern layer 120 and the second circuit pattern layer 130 have substantially the same layer structure, and hereinafter, the description will be based on the layer structure of the first circuit pattern layer 120.
The first circuit pattern layer 120 may include a first metal layer 121 disposed on an upper surface of the insulating layer 110. The first metal layer 121 may be an electroless plating layer. Preferably, the first metal layer 121 may be a chemical copper plating layer.
The first circuit pattern layer 120 may include a second metal layer 122 disposed on the first metal layer 121. The second metal layer 122 may be an electrolytic plating layer. For example, the second metal layer 122 may be a layer formed by electrolytic plating using the first metal layer 121 as a seed layer.
A thickness of the first metal layer 121 may satisfy a range of 10% to 100% of a line width of the trace of the first circuit pattern layer 120. For example, a ratio of a line width of the trace of the first circuit pattern layer 120 to a thickness of the first metal layer 121 may satisfy a range of 1 to 10 times. The thickness of the first metal layer 121 may satisfy a range of 5% to 50% of a total thickness of the first circuit pattern layer 120. For example, a ratio of a total thickness of the first circuit pattern layer 120 to a thickness of the first metal layer 121 may satisfy a range of 2 to 20 times. The thickness of the first metal layer 121 may satisfy a range of 6% to 100% of the thickness of the second metal layer 122. For example, the ratio of the thickness of the second metal layer 122 to the thickness of the first metal layer 121 may satisfy a range of 1 to 19 times.
Specifically, the first metal layer 121 may have a thickness ranging from 1 μm to 2.5 μm. Preferably, the first metal layer 121 may have a thickness ranging from 1.2 μm to 2.3 μm. Preferably, the first metal layer 121 may have a thickness ranging from 1.4 μm to 2.2 μm.
If the thickness of the first metal layer 121 is less than 1 μm, a size of the plating particles constituting the first metal layer 121 is small, and accordingly, the adhesion between the insulating layer 110 and the first metal layer 121 may be reduced. Additionally, if the adhesion between the first metal layer 121 and the insulating layer 110 decreases, a problem may occur in which the first circuit pattern layer 120 is separated into the insulating layer 110.
If the thickness of the first metal layer 121 is greater than 2.5 μm, it may be difficult to miniaturize the first circuit pattern layer 120. For example, if the thickness of the first metal layer 121 is greater than 2.5 μm, it may be difficult to form the line width of the trace of the first circuit pattern layer 120 to 10 μm or less.
In the embodiment, the thickness of the first metal layer 121 is increased compared to the comparative example, and thus the adhesion between the insulating layer 110 and the first metal layer 121 can be improved.
Below, the difference in adhesion according to the difference in plating thickness of the first metal layer between the comparative example and the example is shown in Table 5 below.
Referring to Table 5, in the embodiment, the thickness of the first metal layer 121 corresponding to the chemical copper plating layer increases compared to the comparative example, and accordingly, it was confirmed that the adhesion between the first metal layer 121 and the insulating layer 110 increased. In particular, in the embodiment e, when the line width of the trace of the first circuit pattern layer 120 was 10 μm or less, it was confirmed that the adhesion between the first metal layer 121 and the insulating layer 110 was further improved compared to the comparative example. Meanwhile, in order to further improve the adhesion between the first metal layer 121 and the upper surface of the insulating layer 110, it is preferable that the surface roughness value of the upper surface of the insulating layer 110 is determined based on the thickness of the first metal layer 121.
Here, the surface roughness value described below may mean the surface roughness value of the surface layer 110S of the insulating layer 110 or the surface roughness value of the first metal layer.
For example, a centerline average roughness value (Ra) of the insulating layer 110 may be 12% to 50% of a thickness of the first metal layer 121.
For example, the centerline average roughness value (Ra) of the upper surface of the insulating layer 110 may range between 200 nm and 600 nm. For example, the centerline average roughness value (Ra) of the upper surface of the insulating layer 110 may be 300 nm to 500 nm.
If the centerline average roughness value (Ra) of the upper surface of the insulating layer 110 is less than 200 nm, the anchoring effect that can be expected when plating the first metal layer 121 on the insulating layer 110 may be reduced.
In addition, if the centerline average roughness value (Ra) of the upper surface of the insulating layer 110 exceeds 600 nm, the centerline average roughness value (Ra) of the upper surface of the insulating layer 110 is great, so the first metal layer 121 cannot be formed with a uniform thickness on the upper surface of the insulating layer 110. Accordingly, the adhesion between the insulating layer 110 and the first metal layer 121 may decrease. Furthermore, if the centerline average roughness value (Ra) of the upper surface of the insulating layer 110 is greater than 600 nm, a problem may occur in which the first metal layer 121 remains between the roughness of the upper surface of the insulating layer 110 in a process of etching the first metal layer 121 on the insulating layer 110, and the remaining metal may cause electrical reliability problems such as circuit shorts. Furthermore, if the centerline average roughness value (Ra) of the upper surface of the insulating layer 110 is greater than 600 nm, signal transmission loss may increase due to skin effect.
Preferably, the maximum section height value (Rt) of the upper surface of the insulating layer 110 may satisfy a range between 80% and 600% of the thickness of the first metal layer 121.
For example, the maximum section height value (Rt) of the upper surface of the insulating layer 110 may be 2 μm to 6 μm. For example, the maximum section height value (Rt) of the upper surface of the insulating layer 110 may be 3 μm to 5 μm.
For example, if the maximum section height value (Rt) of the upper surface of the insulating layer 110 is less than 2 μm, the anchoring effect that can be expected when plating the first metal layer 121 on the insulating layer 110 may be reduced.
In addition, if the maximum section height value (Rt) of the upper surface of the insulating layer 110 exceeds 6 μm, the maximum section height value (Rt) of the upper surface of the insulating layer 110 is large, so the first metal layer 121 cannot be formed with a uniform thickness on the upper surface of the insulating layer 110. Accordingly, the adhesion between the insulating layer 110 and the first metal layer 121 may decrease. Furthermore, if the maximum section height value (Rt) of the upper surface of the insulating layer 110 is greater than 6 μm, a problem may occur in which the first metal layer 121 remains between the roughness of the upper surface of the insulating layer 110 in the process of etching the first metal layer 121 on the insulating layer 110, and the remaining metal may cause electrical reliability problems such as circuit shorts. Furthermore, if the maximum section height value (Rt) of the upper surface of the insulating layer 110 is greater than 6 μm, signal transmission loss may increase due to skin effect.
Meanwhile, a thickness range of the first metal layer 131 of the second circuit pattern layer 130 may also same as the thickness range of the first metal layer 121 of the first circuit pattern layer 120. Additionally, a centerline average roughness value (Ra) and/or maximum section height value (Rt) of the lower surface of the insulating layer 110 may same as the centerline average roughness value (Ra) and/or maximum section height value (Rt) of the upper surface of the insulating layer 110.
Meanwhile, the centerline average roughness value (Ra) and maximum section height value (Rt) of the upper surface of the insulating layer 110 can correspond to centerline average roughness value (Ra) and maximum section height value (Rt) of the lower surface of the first metal layer 121 in contact with the upper surface of the insulating layer 110.
Additionally, the adhesion between the insulating layer and the first metal layer 121 according to the centerline average roughness value (Ra) and maximum section height value (Rt) as described above is shown in Table 4 below.
As shown in Table 6, the embodiment can control the centerline average roughness value (Ra) and the maximum section height value (Rt) of the surface of the insulating layer 110 or the first metal layer 121 to correspond to the thickness of the first metal layer 121, as a result, it was confirmed that the adhesion was further improved. Meanwhile, a through electrode 140 may be formed within the insulating layer 110. The through electrode 140 may passes through the insulating layer 110. For example, the through electrode 140 may electrically connect the first circuit pattern layer 120 and the second circuit pattern layer 130. For example, an upper surface of the through electrode 140 may be connected to the first circuit pattern layer 120, and a lower surface of the through electrode 140 may be connected to the second circuit pattern layer 130. The through electrode 140 can be formed by forming a through hole (not shown) passing through the insulating layer 110 and filling the inside of the formed through hole with a conductive material.
In this case, the through hole may be formed by any one of mechanical, laser, and chemical processing. When the via hole is formed by machining, it can be formed using methods such as milling, drilling, and routing. When the via hole is formed by laser processing, it can be formed using methods such as UV or CO2 laser. When the via hole is formed by chemical processing, it can be formed using a chemical containing amino silane, ketones, or the like.
Meanwhile, the laser processing is a cutting method that concentrates optical energy on a surface to melt and evaporate a part of the material to take a desired shape, accordingly, complex formations by computer programs can be easily processed, and even composite materials that are difficult to cut by other methods can be processed.
In addition, the laser processing has a cutting diameter of at least 0.005 mm, and has a wide range of possible thicknesses.
As the laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. YAG laser is a laser that can process both copper foil layers and insulating layers, and CO2 laser is a laser that can process only insulating layers.
When the through hole is formed, the through part 140 of the embodiment may be formed by filling the inside of the through hole with a conductive material. The metal material forming the through part 140 may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material filling may use any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink-jetting and dispensing. Meanwhile, the through electrode 140 may include a first metal layer 141 and a second metal layer 142.
The first metal layer 141 of the through electrode 140 may correspond to the first metal layer 121 of the first circuit pattern layer 120, and the second metal layer 142 of the through electrode 140 may correspond to the second metal layer 122 of the first circuit pattern layer 120.
Accordingly, the first metal layer 141 of the through electrode 140 can satisfy a thickness ranging from 1 um to 2.5 um. Preferably, the first metal layer 141 of the through electrode 140 may satisfy a thickness ranging from 1.2 um to 2.3 um. Preferably, the first metal layer 141 of the through electrode 140 may satisfy a thickness ranging from 1.4 um to 2.2 um.
Additionally, a centerline average roughness value (Ra) of an inner wall of the through hole of the insulating layer 110 may range between 200 nm and 600 nm. For example, the centerline average roughness value (Ra) of the inner wall of the through hole of the insulating layer 110 may be 300 nm to 500 nm.
Additionally, the maximum section height value (Rt) of the inner wall of the through hole of the insulating layer 110 (Specifically, the third portion of the surface layer of the insulating layer) may be 2 um to 6 um. For example, the maximum section height value (Rt) of the inner wall of the through hole of the insulating layer 110 may be 3 um to 5 um.
The embodiment may control the surface roughness value of the surface layer 110S of the insulating layer 110 while including fluorine (F) in the surface layer 110S of the insulating layer 110 as described above. Furthermore, the embodiment may control the thickness of the first metal layer in contact with the surface layer 110S of the insulating layer 110. Therefore, the embodiment can reduce signal transmission loss of the circuit pattern layer or through electrode and improve adhesion to the insulating layer.
As shown in
For example, in the comparative example, it was confirmed that traces in some regions were separated at a line width (W6) of 7 um and did not remain on the insulating layer.
Unlike this, the embodiment can secure adhesion between the insulating layer 110 and the circuit pattern layers by increasing the thickness of the first metal layer constituting the circuit pattern layer compared to the comparative example. Through this, as shown in (b) of
The circuit board in the embodiment comprises an insulating layer including a surface layer and a circuit pattern layer disposed on the insulating layer. The surface layer may mean a depth range of 10 nm to 100 nm from a surface of the insulating layer. The surface layer of the insulating layer contains fluorine. That is, the surface layer of the insulating layer contains carbon (C)—fluorine (F). At this time, the fluorine (F) can lower the polarity of a surface of the insulating layer.
That is, the embodiment allows the insulating layer to be plasma treated using CF4. At this time, the surface layer of the insulating layer before the plasma treatment includes a C—H bond portion. And, the C—H bond portion of the surface layer of the insulating layer after the plasma treatment is replaced with a C—F bond. In addition, C—F has lower electronic polarizability than C—H, and thus the polarity of the surface of the insulating layer can be lowered. At this time, as the usage frequency of the application to which the circuit board is applied increases, the signal flow moves to a surface of a conductor due to the skin effect. Therefore, the polarity of a dielectric surface in contact with the conductor is important. At this time, the embodiment allows fluorine (F) with low electrical polarity to be included in the surface layer within a certain depth range from the surface of the insulating layer, thereby minimizing signal transmission loss due to skin effect. As a result, communication performance can be improved.
Additionally, as the dielectric constant of the insulating layer or the polarity of the surface increases, signal loss increases and signal transmission speed decreases accordingly. At this time, the coefficient of thermal expansion and dielectric constant of the insulating layer are in a mutual trade-off relationship, and accordingly, when the polarity of the insulating layer is lowered, the coefficient thermal expansion of the insulating layer increases and the warpage characteristic accordingly deteriorates. At this time, the embodiment does not modify the polarity of the entire region of the insulating layer, but only performs polarity modification of the surface layer at a certain depth from the surface of the insulating layer through plasma treatment. Through this, the embodiment can modify only the polarity of the surface layer of the insulating layer while maintaining the coefficient of thermal expansion of the insulating layer. Accordingly, it is possible to minimize signal loss and increase signal transmission speed while maintaining the bending characteristics of the circuit board.
Additionally, the embodiment ensures that highly electronegative fluorine (F) is present in the surface layer of the insulating layer. At this time, the fluorine (F) can delocalize the distribution of electrons within the molecules of the insulating layer, thereby lowering the overall polarity of the polymer. Through this, the embodiment can lower a packing density of the polymer and increase a free volume, thereby lowering a dielectric constant of the insulating layer. Through this, high reliability can be maintained even in products that use high frequencies.
Meanwhile, the circuit pattern layer in the embodiment includes a first metal layer and a second metal layer. The first metal layer may have a thickness ranging from 1 um to 2.5 um. Preferably, the first metal layer may have a thickness ranging from 1.2 um to 2.3 um. Preferably, the first metal layer may have a thickness ranging from 1.4 um to 2.2 um. Through this, the embodiment can further improve the adhesion between the first metal layer and the insulating layer, and further improve the adhesion between the insulating layer and the circuit pattern layer. Through this, in the embodiment, the electrical reliability of the circuit pattern layer can be improved, and thus product satisfaction can be improved. In addition, the embodiment improves the adhesion between the insulating layer and the circuit pattern layer, so that the line width of the trace constituting the circuit pattern layer can be refined, and as a result, the circuit integration degree can be increased or the overall volume of the circuit board can be reduced.
Additionally, the centerline average roughness value (Ra) of the first metal layer in the embodiment may range between 200 nm and 600 nm. The centerline average roughness value (Ra) of the first metal layer may be 300 nm to 500 nm. Additionally, the maximum section height value (Rt) of the first metal layer may be 2 um to 6 um. For example, the maximum section height value (Rt) of the first metal layer may be 3 um to 5 um. In an embodiment, the centerline average roughness value (Ra) or maximum section height value (Rt) may be controlled to correspond to the thickness of the first metal layer, and accordingly, the anchoring effect can be further improved as the thickness of the first metal layer increases. Furthermore, the embodiment can improve the plating thickness uniformity of the first metal layer through control of the centerline average roughness value (Ra) and maximum section height value (Rt). Furthermore, when etching the first metal layer, the embodiment prevents a portion of the first metal layer from remaining on the surface of the insulating layer, thereby improving the electrical reliability of the circuit board and improving the yield of the circuit board.
Hereinafter, a method of manufacturing a circuit board according to an embodiment will be described.
Referring to
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At this time, the first metal layers 121, 131 and 141 may have a thickness ranging from 1 um to 2.5 um. Preferably, the first metal layers 121, 131 and 141 may have a thickness ranging from 1.2 um to 2.3 um. Preferably, the first metal layers 121, 131 and 141 may have a thickness ranging from 1.4 um to 2.2 um.
Next, referring to
For example, the embodiment may proceed with a process of stacking a first dry film (DF1) including a first opening (OR1) that vertically overlaps the region where the first circuit pattern layer 120 will be disposed, and a process of laminating a second dry film (DF2) including a second opening (OR2) that vertically overlaps the region where the second circuit pattern layer 130 will be disposed.
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The insulating substrate including the first to third insulating parts 310, 320, and 330 may have a flat structure. The insulating substrate may be PCB. Here, the insulating substrate may be implemented as a single substrate, or alternatively, may be implemented as a multilayer substrate in which a plurality of insulating layers are sequentially stacked.
Accordingly, the insulating substrate may include a plurality of insulating parts 310, 320, and 330. As shown in
The first insulating part 310, the second insulating part 320, and the third insulating part 330 may include different insulating materials. Preferably, the first insulating part 310 may include glass fiber. Also, the second insulating part 320 and the third insulating part 330 may not include glass fibers, unlike the first insulating part 310. Preferably, the second insulating part 320 and the third insulating part 330 may include the RCC shown in
Accordingly, a thickness of each insulating layer constituting the first insulating part 310 may be different from a thickness of each insulating layer constituting the second insulating part 320 and the third insulating part 330. In other words, the thickness of each insulating layer constituting the first insulating part 310 may be greater than the thickness of each insulating layer constituting the second insulating part 320 and the third insulating part 330.
That is, the first insulating part 310 includes glass fiber, and the glass fiber generally has a thickness of 12 um. Accordingly, the thickness of each insulating layer constituting the first insulating part 310 includes the glass fiber and may range from 19 um to 23 um.
In contrast, the second insulating part 320 does not include glass fiber. Preferably, each insulating layer constituting the second insulating part 320 may be composed of RCC.
Additionally, the third insulating part 330 does not include glass fiber. Preferably, each insulating layer constituting the third insulating part 330 may be RCC.
That is, the insulating part constituting the circuit board in the comparative example includes a plurality of insulating layers, and the plurality of insulating layers are all composed of prepreg containing glass fiber. At this time, it is difficult to reduce the thickness of the glass fiber in the circuit board of the comparative example based on the prepreg. This is because the glass fibers included in the prepreg may come into contact with the circuit pattern layer disposed on the surface of the prepreg when the thickness of the prepreg decreases, resulting in a risk of cracking. Accordingly, when reducing the thickness of the prepreg, the circuit board in the first comparative example may have suffered dielectric breakdown and damage to the circuit pattern layer. Accordingly, the circuit board in the comparative example had a limit in reducing the overall thickness due to the thickness of the glass fibers constituting the prepreg.
Additionally, the circuit board in the comparative example has a high dielectric constant because it is composed of an insulating layer made only of prepreg containing glass fiber. However, in a case of dielectrics with high dielectric constants, it is difficult to approach them as a high-frequency substitute. That is, because the circuit board in the comparative example has a high dielectric constant of glass fiber, a phenomenon in which the dielectric constant is destroyed in the high frequency band occurs.
Accordingly, the embodiment allows at least some of the layers in the multilayer circuit board to include the RCC shown in
The first insulating part 310 may include a first insulating layer 311, a second insulating layer 312, a third insulating layer 313, and a fourth insulating layer 314 from below. In addition, glass fiber may be included in each of the first insulating layer 311, the second insulating layer 312, the third insulating layer 313, and the fourth insulating layer 314. For example, the first insulating layer 311, the second insulating layer 312, the third insulating layer 313, and the fourth insulating layer 314 may each include prepreg.
Meanwhile, the insulating substrate in the embodiment of the present application may be composed of 8 layers based on the insulating layer. However, the embodiment is not limited thereto, and the total number of layers of the insulating layer may be increased or decreased.
Additionally, in the first embodiment, the first insulating part 310 may be composed of four layers. For example, in the first embodiment, the first insulating part 310 may be composed of four layers of prepreg.
Additionally, the second insulating part 320 may include a fifth insulating layer 321 and a sixth insulating layer 322 from below. The fifth insulating layer 321 and the sixth insulating layer 322 constituting the second insulating part 320 may include RCC.
Additionally, the third insulating part 330 may include a seventh insulating layer 331 and an eighth insulating layer 332 from above. The seventh insulating layer 331 and the eighth insulating layer 332 constituting the third insulating part 330 may include RCC.
Accordingly, the circuit pattern layers disposed on the second insulating part 320 and the third insulating part 330 may have a structure corresponding to the first and second circuit pattern layers shown in
That is, the circuit pattern layer 340 may be disposed on a surface of the insulating layer constituting each of the first insulating part 310, the second insulating part 320, and the third insulating part 330.
Preferably, a circuit pattern layer 340 may be disposed on at least one surface of the first insulating layer 311, the second insulating layer 312, the third insulating layer 313, the fourth insulating layer 314, the fifth insulating layer 321, the sixth insulating layer 322, the seventh insulating layer 331 and the eighth insulating layer 332.
At least one through electrode 350 is formed in at least one of the plurality of insulating layers constituting the first insulating part 310, the second insulating part 320, and the third insulating part 330. The through electrode 350 is disposed to pass through at least one insulating layer among the plurality of insulating layers. The through electrode 350 may pass through only one insulating layer among the plurality of insulating layers. Alternatively, the through electrode 350 may be formed to commonly pass through at least two insulating layers among the plurality of insulating layers. Accordingly, the through electrode 350 electrically connects circuit patterns disposed on surfaces of different insulating layers to each other.
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And, the first insulating part 310a may include two layers of prepreg 311a and 312a.
Additionally, the second insulating part 320a may include three layers of RCCs 321a, 322a, and 323a.
Additionally, the third insulating part 330a may include three layers of RCCs 331a, 332a, and 333a.
Referring to
Additionally, the insulating part 310b may all include RCCs 311b, 312b, 313b, 314b, 315b, 316b, 317b and 318b.
Referring to
For this purpose, the multilayer circuit board constituting the semiconductor package includes a first insulating part 410 including a plurality of insulating layers 411, 412, 413, and 414, a second insulating part 420 including a plurality of insulating layers 421 and 422, and a third insulating part 430 including a plurality of insulating layers 431 and 432. In addition, the second insulating part 420 and the third insulating part 430 may include RCC, and first and second circuit pattern layers as shown in
Meanwhile, the semiconductor package includes a first protective layer SR1 disposed on an uppermost insulating layer and a second protective layer SR2 disposed on a lowermost insulating layer.
Additionally, the semiconductor package includes a connection part 500 disposed on a circuit pattern layer disposed on an uppermost side. The connection part 500 may be a solder ball, but is not limited thereto.
Additionally, the semiconductor package may include a chip 600 attached to the connection part 500.
The chip 600 may be a processor chip. For example, the chip 600 may be an application processor (AP) chip of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller.
In addition, although not shown in the drawing, the semiconductor package of the embodiment may further include an additional chip. For example, in an embodiment, at least two chips of a central processor (e.g., CPU), a graphics processor (e.g., GPU), digital signal processor, an encryption processor, a microprocessor, and a microcontroller may be disposed separately on the circuit board at a regular distance. For example, the chip 600 in the embodiment may include a central processor chip and a graphics processor chip, but is not limited thereto.
Meanwhile, the plurality of chips may be spaced apart from each other at a predetermined distance on the circuit board. For example, the distance between the plurality of chips may be 150 μm or less. For example, the distance between the plurality of chips may be 120 μm or less. For example, the distance between the plurality of chips may be 100 μm or less.
Preferably, the distance between the plurality of chips may range from 60 um to 150 um. Preferably, the distance between the plurality of chips may range from 70 um to 120 um. Preferably, the distance between the plurality of chips may range from 80 um to 110 um. If the distance between the plurality of chips is less than 60 μm, problems with operation reliability may occur due to mutual interference between the plurality of chips. If the distance between the plurality of chips is greater than 150 μm, signal transmission loss may increase as the distance between the plurality of chips increases. If the distance between the plurality of chips is greater than 150 μm, the volume of the semiconductor package may increase.
The circuit board in the embodiment comprises an insulating layer including a surface layer and a circuit pattern layer disposed on the insulating layer. The surface layer may mean a depth range of 10 nm to 100 nm from a surface of the insulating layer. The surface layer of the insulating layer contains fluorine. That is, the surface layer of the insulating layer contains carbon (C)—fluorine (F). At this time, the fluorine (F) can lower the polarity of a surface of the insulating layer.
That is, the embodiment allows the insulating layer to be plasma treated using CF4. At this time, the surface layer of the insulating layer before the plasma treatment includes a C—H bond portion. And, the C—H bond portion of the surface layer of the insulating layer after the plasma treatment is replaced with a C—F bond. In addition, C—F has lower electronic polarizability than C—H, and thus the polarity of the surface of the insulating layer can be lowered. At this time, as the usage frequency of the application to which the circuit board is applied increases, the signal flow moves to a surface of a conductor due to the skin effect. Therefore, the polarity of a dielectric surface in contact with the conductor is important. At this time, the embodiment allows fluorine (F) with low electrical polarity to be included in the surface layer within a certain depth range from the surface of the insulating layer, thereby minimizing signal transmission loss due to skin effect. As a result, communication performance can be improved.
Additionally, as the dielectric constant of the insulating layer or the polarity of the surface increases, signal loss increases and signal transmission speed decreases accordingly. At this time, the coefficient of thermal expansion and dielectric constant of the insulating layer are in a mutual trade-off relationship, and accordingly, when the polarity of the insulating layer is lowered, the coefficient thermal expansion of the insulating layer increases and the warpage characteristic accordingly deteriorates. At this time, the embodiment does not modify the polarity of the entire region of the insulating layer, but only performs polarity modification of the surface layer at a certain depth from the surface of the insulating layer through plasma treatment. Through this, the embodiment can modify only the polarity of the surface layer of the insulating layer while maintaining the coefficient of thermal expansion of the insulating layer. Accordingly, it is possible to minimize signal loss and increase signal transmission speed while maintaining the bending characteristics of the circuit board.
Additionally, the embodiment ensures that highly electronegative fluorine (F) is present in the surface layer of the insulating layer. At this time, the fluorine (F) can delocalize the distribution of electrons within the molecules of the insulating layer, thereby lowering the overall polarity of the polymer. Through this, the embodiment can lower a packing density of the polymer and increase a free volume, thereby lowering a dielectric constant of the insulating layer. Through this, high reliability can be maintained even in products that use high frequencies.
Meanwhile, the circuit pattern layer in the embodiment includes a first metal layer and a second metal layer. The first metal layer may have a thickness ranging from 1 um to 2.5 um. Preferably, the first metal layer may have a thickness ranging from 1.2 um to 2.3 um. Preferably, the first metal layer may have a thickness ranging from 1.4 um to 2.2 um. Through this, the embodiment can further improve the adhesion between the first metal layer and the insulating layer, and further improve the adhesion between the insulating layer and the circuit pattern layer. Through this, in the embodiment, the electrical reliability of the circuit pattern layer can be improved, and thus product satisfaction can be improved. In addition, the embodiment improves the adhesion between the insulating layer and the circuit pattern layer, so that the line width of the trace constituting the circuit pattern layer can be refined, and as a result, the circuit integration degree can be increased or the overall volume of the circuit board can be reduced.
Additionally, the centerline average roughness value (Ra) of the first metal layer in the embodiment may range between 200 nm and 600 nm. The centerline average roughness value (Ra) of the first metal layer may be 300 nm to 500 nm. Additionally, the maximum section height value (Rt) of the first metal layer may be 2 um to 6 um. For example, the maximum section height value (Rt) of the first metal layer may be 3 um to 5 um. In an embodiment, the centerline average roughness value (Ra) or maximum section height value (Rt) may be controlled to correspond to the thickness of the first metal layer, and accordingly, the anchoring effect can be further improved as the thickness of the first metal layer increases. Furthermore, the embodiment can improve the plating thickness uniformity of the first metal layer through control of the centerline average roughness value (Ra) and maximum section height value (Rt). Furthermore, when etching the first metal layer, the embodiment prevents a portion of the first metal layer from remaining on the surface of the insulating layer, thereby improving the electrical reliability of the circuit board and improving the yield of the circuit board.
The characteristics, structures and effects described in the embodiments above are included in at least one embodiment but are not limited to one embodiment. Furthermore, the characteristics, structures, and effects and the like illustrated in each of the embodiments may be combined or modified even with respect to other embodiments by those of ordinary skill in the art to which the embodiments pertain. Thus, it should be construed that contents related to such a combination and such a modification are included in the scope of the embodiment.
The above description has been focused on the embodiment, but it is merely illustrative and does not limit the embodiment. A person skilled in the art to which the embodiment pertains may appreciate that various modifications and applications not illustrated above are possible without departing from the essential features of the embodiment. For example, each component particularly represented in the embodiment may be modified and implemented. In addition, it should be construed that differences related to such changes and applications are included in the scope of the embodiment defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0133237 | Oct 2021 | KR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/KR2022/014748 | 9/30/2022 | WO |
