Patent Application
20060252266
1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a chemical mechanical polishing (CMP) process of high selectivity.
2. Description of the Related Art
CMP is a very important technology in modern semiconductor processes. In a typical CMP process, a substrate is pressed onto a rotated polishing pad, while polishing slurry is provided onto the polishing pad so that the surface of the substrate is polished. In the cases where only one or few materials on the substrate surface are to be polished, the selectivity of the polishing slurry to the material(s) is preferably as high as possible to reduce damages of the other material layer(s) on the substrate to a minimum.
Most of high-selectivity slurries (HSS) are chemistry dominated slurries, and are conventionally used in combination with a polishing pad 100 having concentric circular grooves 110 thereon, which is illustrated in
In view of the foregoing, this invention provides a CMP process of high selectivity, wherein the polishing pad used has grid-like grooves thereon, rather than concentric circular grooves.
The CMP process of high selectivity of this invention is described as follows. A substrate having a first material and a second material thereon is provided. A polishing pad that has multiple first grooves and multiple second grooves crossing the first grooves thereon is provided. The polishing pad and a polishing slurry are then used together to polish the substrate, wherein the polishing slurry has higher selectivity to the first material than to the second material.
By using the polishing pad with grid-like grooves thereon, the uniformity of polishing the first material with a high-selectivity slurry can be significantly improved, as will be demonstrated by the preferred embodiments of this invention.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
GRV %=(X-width of groove/X-pitch of groove)×(Y-width of groove/Y-pitch of groove)
The groove density is generally about 1-30%, preferably about 1-15%, according to the preferred embodiment of this invention.
The selectivity of the high-selectivity slurry used in combination with the pad 200 is preferably about 10 or higher, and the HSS may be one specifically for polishing copper, tungsten or silicon oxide. For example, the CMP process of high selectivity may be a part of a damascene process, which may be a Cu-damascene process wherein a copper layer is formed on an insulator with a trench therein and then a HSS specifically for polishing copper is used to polish the Cu layer to form a conductive line. Analogously, the damascene process may be a W-damascene process wherein a tungsten layer is formed on an insulator with a via hole therein and then a HSS specifically for polishing tungsten is used to polish the tungsten layer to form a conductive plug. In such cases, the higher the selectivity of the polishing slurry to Cu or W than to the insulator, the fewer the damages of the insulator caused by the CMP process. The selectivity is preferably about 10 or higher.
The CMP process of high selectivity of this invention can also be applied to a shallow trench isolation (STI) process. In the STI process, for example, the hard mask material is silicon nitride, the trench-filling material is silicon oxide, and the high-selectivity slurry used has higher selectivity to silicon oxide than to silicon nitride. Similarly, the selectivity is preferably about 10 or higher.
In addition, though the polishing pad 200 illustrated in
In addition, though the X-grooves and the Y-grooves on the polishing pad 200 illustrated in
As shown in
In this example, a silicon oxide layer formed as a trench-filling material of a STI process is polished to form an STI structure, while a patterned silicon nitride layer as a hard mask and shallow trenches have been formed on the wafers previously. The selectivity of the high-selectivity slurry to silicon oxide is about 30 relative to its selectivity to silicon nitride. A polishing pad of GRV %>5% and another polishing pad of GRV %=0 are used respectively to show the NU-reduction effect of this invention. In addition, two different polishing heads are used respectively to prove that the NU-reduction effect is not caused by the polishing head.
After the CMP process, RR and NU % are estimated through diameter scan of the thickness of the remaining silicon oxide layers (labeled with “Line” in Table 1) and through polar mapping of the thickness (labeled with “Polar”), respectively, to prove that the NU-reduction effect is not caused by the estimating method of RR and NU %. In the former estimating method, the thickness of the remaining oxide layer is measured along some lines passing the center of the wafer; while in the later method, the polar map of thickness of the remaining oxide layer is made for estimating RR and NU %. The results are shown in Table. 1
According to the results shown in Table 1, when RR and NU % are estimated through diameter scan of thickness (Line), the removal rates of using the pad of GRV %=0 are found to be lower than those of using the pad of GRV %>5%. When the estimation is made through polar mapping of thickness, the removal rates of using the former are found to be approximately the same as those of using the latter. However, no matter how the non-uniformity of the oxide layers estimated, the polishing pad of GRV %>5% makes much smaller non-uniformity as compared with the flat polishing pad of GRV %=0.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
