The present invention relates generally to logic networks, including but not limited to neural networks, that have components that are based on spin transport and spin magnet interactions.
The term “neural network” often refers to models employed in statistics, cognitive psychology and artificial intelligence. Neural network models emulate, to some degree, the central nervous system. Neural networks can be characterized by principles of non-linear, distributed, parallel and local processing and adaptation. Neural networks can be implemented in software and digital logic. Modern software implementations of artificial neural networks are based on statistics and signal processing. In some of these systems, neural networks or parts of neural networks (like artificial neurons) form components in larger systems that combine both adaptive and non-adaptive elements.
A neural network can be described as a type of statistical model that consists of a set of inputs that can produce a set of outputs using sets of adaptive weights. The weights affect how the inputs are combined to produce logical outputs. A classic model of a neural network has a set of input nodes, a set of output nodes, and a set in intermediate or hidden nodes. Sets of inputs are connected to sets of intermediate nodes, and intermediate nodes are connected to sets of output nodes. Adaptive weights are used to determine how the value of each input node influences the output of the intermediate node. The combination of values from the intermediate nodes at each output influences that output. Many variants of this type of model have been implemented in circuitry and software.
Implementing neural networks in digital circuits can have space consumption issues due to the need for granularity of the weighting values and the binary nature of digital circuits. Since the advent of electronic circuits, the miniaturization of transistors and logic devices has been a universal goal to advance the capabilities and applicability of electronic devices. Neural networks implemented in circuitry are no exception.
There is a need therefore, for an implementation of neural networks that increasingly miniaturizes circuit implementation of at least some forms of neural networks.
A circuit element includes first and second nanomagnets, at least first fixed magnet and a weighting circuit. The first nanomagnet is inductively coupled to a first current carrying element, and is configured to change polarity responsive to current in the first current carrying element. The second nanomagnet is magnetically coupled to the first nanomagnet and inductively coupled to a second current carrying element. The first fixed magnet is disposed on the second nanomagnet and has a first fixed polarity. The weighting circuit is operably coupled to provide a voltage to the first fixed magnet.
The above-described features and advantages, as well as others, will become more readily apparent to those of ordinary skill in the art by reference to the following detailed description and accompanying drawings.
A key component to miniaturization is the reduction in operating voltage. One of the alternative approaches that that has recently received attention is nanomagnet logic (NML) using a nanomagnet to switch another nanomagnet using electron spin currents.
U.S. patent application Ser. No. 13/345,588, filed Jan. 6, 2012, which is incorporated herein by reference in its entirety, teaches an all-spin logic nanomagnetic circuit in which a first nanomagnet imparts its current magnetic state to a second nanomagnet via spin currents that propagate through a spin coherent channel between the nanomagnets. Referring briefly to
In particular, upon application of the bias voltages, the bias voltage interacts with the current magnetic state of the first nanomagnet 12 to impart a spin current onto the spin coherent channel 16. The spin current has a magnetic polarity that corresponds to the magnetic state of the first nanomagnet 12. Thus, the spin current carries the information that is stored in the first nanomagnet 12. The spin current propagates to the second nanomagnet 14. The operation of the spin current and the bias voltage on the second nanomagnet 14 causes the second nanomagnet 14 to assume the “state” of the first nanomagnet 12.
A drawback to the circuit shown in
Accordingly, there is a need for a practical implementation of a nanomagnet device that avoids at least some of the shortcomings of all-spin logic nanomagnetic devices and allows for versatility and scalable circuits. The above-described need, as well as others, are satisfied by at least some embodiments of a nanomagetic circuit that employs charged-coupled spin logic.
A first embodiment is a circuit element that includes first and second nanomagnets and first and second fixed magnets. The first nanomagnet is inductively coupled to a first current carrying element, and is configured to change polarity responsive to current in the first current carrying element. In one example, the first current carrying element includes a spin Hall effect substrate. The second nanomagnet is magnetically coupled to the first nanomagnet, and is inductively coupled to a second current carrying element. The first fixed magnet is disposed on the second nanomagnet and has a first fixed polarity, and second fixed magnet disposed on the second nanomagnet and has a second fixed polarity.
The first and second fixed magnets can be used, upon application of appropriate bias voltages, to cooperate with the second nanomagnet to produce a current flow having a direction that is indicative of the magnetic state or spin state of the second nanomagnet. The produced current thus carries “information” that is not reliant on spin currents alone, and can be readily employed in larger circuit combinations.
In general, the device 200 further includes a first fixed magnet 205, a second fixed magnet 208, at least one oxide layer 210, a conductor 212, a giant spin Hall effect (“GSHE”) channel or substrate 214, and a terminal impedance 216. The first fixed magnet 205 is preferably formed as a nanopillar of permalloy, CoFeB or other magnetic material. The first fixed magnet 205 has a predetermined, and, for practical purposes, fixed polarity or magnetic state. For example, the first fixed magnet 205 may have a magnetization direction extending out from the paper as shown in
Similarly, the second fixed magnet 208 has a similar structure and also has a predetermined and fixed polarity or magnetic state which is anti-parallel of that of the first fixed magnet 205. In this example, the second fixed magnet 208 may have a magnetization direction extending into the paper as shown in
The first fixed magnet 205 and the second fixed magnet 208 are separated by from the first nanomagnet 202 by portions of the oxide layer 210. The oxide layer 210 should be configured to allow a spin valve or magnetic tunnel junction to develop between each of the fixed magnets 205, 208 and the first nanomagnet 202 the first nanomagnet 202 is in the corresponding state. The details generating spin valves and magnetic tunnel junctions are known.
The first nanomagnet 202 is disposed on the conductor 212. The conductor 212 may be any suitable conductor, including, but not limited to, a copper or other conductive substance. The conductor 212 is operably coupled to a first end of the GSHE channel 214. The termination impedance 216 is operably connected to the second (opposite) end of the GSHE channel 214. GSHE channel 214 is preferably a thin layer of tantalum, tungsten or platinum, although other materials may be used. The second nanomagnet 204 is disposed on the GSHE channel 214 at a location between the first end and the second end as shown.
In general, the device 200 actually includes two component devices: a read element 230 and a write element 232. The read element 230 includes the first nanomagnet 202, the fixed magnets 205, 208, the at least one oxide layer 210, and the conductor 212. As will be discussed below, the read element 230 is designed to “read out” the state of the nanomagnet 202 using the current I in the conductor 212. The write element 232 includes the GSHE channel or substrate 214, the second nanomagnet 204, and the terminal impedance 216. As will be discussed below, the write element is designed to “write” information, based on the current I, to the second nanomagnet 204. The device 200 thus operates to read out the information of the magnetic state of the first nanomagnet 202 and write that information to the second nanomagnet 204.
In the operation of the device 200, a positive bias voltage V+ is applied to the first fixed magnet 205, and a negative bias voltage V− is applied to the second fixed magnet 208. The orientation of the magnetic polarity of the nanomagnet 202 creates a spin valve or magnetic tunnel junction between the first nanomagnet 202 and one of the two fixed magnets 205, 208. Thus, if the first nanomagnet 202 has a first magnetic state (e.g. a first polarity), then a magnetic tunnel junction is created between the first fixed magnet 205 and the nanomagnet 202. If the first nanomagnet 202 has the second magnetic state (i.e. a second polarity), then a magnetic tunnel junction is created between the second fixed magnet 208 and the first nanomagnet 202. The magnetic tunnel junction creates a low impedance path through which the bias voltage V+ or V− may flow from the fixed magnets 205 or 208 to the terminal impedance 216.
The direction of the current I through the conductor 212 and the GSHE substrate 214 controls the magnetic state of the second nanomagnet 204. This control is a result of the spin Hall effect. In particular, if the current flows in a first direction (from V+ to ground), then the second nanomagnet 204 will change to (or stay in) the first magnetic state. If, however, the current flows in the second direction (from ground to V−), then the second nanomagnet 204 will change to (or stay in) the second magnetic state. To this end, the GSHE substrate 214 operates to create a spin Hall effect at or near the second nanomagnet 204. The spin Hall effect is one in which electrons of different polarity spin currents are separated into different directions. To this end, the GSHE substrate material causes the electrons with a first polarity spin to propagate a first spin current in a first direction away from the main current flow, and electrons with a second polarity spin to propagate a second spin current in a second direction away from the main current flow. As a result, current flowing from V+ to ground forces e+ spin electrons in a first direction and e− spin electrons in a second direction. By contrast, current flowing from ground to V− forces e− spin electrons in the first direction and e+ spin electrons in the second direction.
The clustering of the spin electrons in opposite sides imparts a magnetic state onto the nanomagnet 204. Thus, current flowing from V+ to ground causes the nanomagnet 204 to be in the first magnetic state, and current flowing from ground to V− causes the nanomagnet 204 to be in the second magnetic state. Accordingly, the overall operation is such that the state of the first nanomagnet 202 dictates the state of the second nanomagnet 204, provided the current I is of sufficient magnitude, which will be discussed further below.
One of the advantages of the device 200 is that the current flowing through the conductor 212 and GSHE substrate 214 can be of significant magnitude, thus allowing for separation of the nanomagnets 202, 204 using a conductor 212 of significant length. Because the “information” about the state of the first nanomagnet 202 is carried by the “direction” of the current, making the length of conductor 212 or amount of separation between the nanomagnets 202, 204 less significant. By contrast, the prior art all-spin logic device 100 relied on spin currents to carry information, which can only propagate information over short distances, and further requires a spin coherent channel 16 for the entire distance.
In further analytical detail, assume that G and ΔG represent the sum and difference, respectively, of the parallel (GP) and anti-parallel (GAP) conductances of the actual magnetic tunnel junctions through the oxide layer(s) 210. This circuit leads straightforwardly to the following expression for the current I:
The current is thus proportional to the component of the input magnetization along a fixed direction {circumflex over (M)} determined by the fixed magnets 205, 208. It should be noted that the magnitude of the current I for a given voltage V is determined by ΔG=GP−GAP. It has been shown that a magnetic tunnel junction between a CoFeB fixed magnet (e.g. 205, 208) and a MgO nanomagnet (e.g. 202) has a resistance-area product of A/GP=18 ohm-μm2. As a result, the GP=0.45 mS can be estimated, which with a tunnel magnetoresistance (“TMR”) of 150% should provide
ΔG=GP*TMR/(TMR+1)=0.25 mS
It should also be noted that the corresponding conductance G is ˜(1.5 kilo-ohm)−1 so that for a resistance r<<1 kilo-ohm, the denominator in Eq.(1) can be ignored.
Referring again to
{right arrow over (Is)}=βIz (2a)
where
β=Spin−Hall Angle*(As/A) (2b)
where As and A are the cross-sectional areas for the spin current and charge currents, respectively. For a magnet with length L=80 nm, this ratio could be ˜50 if the thickness t0 of the high spin-orbit metal layer (GSHE substrate 214) is 2 nm. Based on the demonstrated spin-Hall angle of 0.2 in tantalum, this would give a charge to spin amplification factor of β=8.
If Is,c represents the critical spin current required to switch the magnet, then the charge current I that is needed is given by I≧Is,c/β. Thus, the voltages V+ and V− in
Js,c=(2q/)αμ0Mst0(HK+Ms/2)˜3×106 A/cm2
where the damping parameter α˜0.01, saturation magnetization μ0Ms˜1 T, thickness t0˜1.6 nm and the coercive field HK<<Ms. This gives a critical spin current Is,c˜240 μA for a nanomagnet 204 of width W˜100 nm in the direction perpendicular to the page in
The principles of the device 200 can be employed, along with other features, to create a concatenable spin device.
In general, the switch 400 can be programmed to one of two magnetic states via the input current Iin provided to the write unit 430. To read out the present magnetic state of the device, bias voltages V+ and V− are applied to the read unit 432, producing a current Iout that carries the magnetic state information. As will be discussed below in connection with
The circuit element 400 of
The first nanomagnet 402 and the second nanomagnet 404 may suitably have the same structure as the nanomagnets 202, 204 of
As shown in
As discussed above, the second nanomagnet 404 is magnetically coupled to the first nanomagnet 402. To this end, the second nanomagnet 404 may suitably be disposed immediately above the first nanomagnet 402, even though for purposes of clarity the second nanomagnet 404 is shown in
The first fixed magnet 418 is disposed proximate the second nanomagnet 404 and has a first fixed polarity. The first fixed magnet 418 is arranged on the second nanomagnet 404 in the same manner as the first fixed magnet 205 is arranged on the first nanomagnet 202 of
In operation, the switch 400 has two steady states. In a first state, the first nanomagnet 402 is in a first magnetic state, and the second nanomagnet 404 is in the opposite or second magnetic state (i.e. polarity). In the second state, the first nanomagnet 402 is in the second magnetic state and the second nanomagnet 404 is in the first magnetic state. In general, the current input 410 may be used to “write” information to the device 400, whereby the steady state of the circuit element 400 may be changed. The bias inputs 422, 424, on the other hand, may be used to read the current state of the circuit element 400 via the current output 412.
A first write operation involves applying a positive input current Iin to the current input 410. Assuming the applied current Iin has sufficient magnitude (discussed further below), the positive input current causes the switch 400 to be in the first state. A second write operation involves applying a negative input current Iin to the current input 410. Assuming the current magnitude is sufficient, the negative input current causes the switch 400 to be in the second state. It will be appreciated that the circuit element 400 has hysteresis, and a certain of positive or negative current is required to change the current state.
Assuming a positive current Iin is provided to the current input 410, the current Iin propagates through the GSHE substrate 406 to the first impedance 414. Because the current input 410 and the first impedance 414 are proximate opposing ends 406a, 406b, respectively of the GSHE substrate 406, the current Iin flows past the surface of the first nanomagnet 402. The GSHE substrate 406 generates the spin Hall effect to split off up spin electrons e+ and the down spin electrons e− in a manner that induces the first nanomagnet 402 to be in the first magnetic state, similar to the operation of the GSHE substrate 214 of
Accordingly, assuming a positive current Iin (i.e. flowing from the input 410 to the impedance 414) of sufficient magnitude is received at the current input 410, then the circuit device 400 can change from the second state to the first state. Otherwise, a positive current Iin has no effect.
Similarly, if a negative current Iin of sufficient magnitude (Iin≧Is,c/β) is received at the current input 410 (i.e. flowing from the impedance 414 to the current input 410), then the circuit device 400 can change from the first state to the second state. In particular, the negative current Iin propagates through the GSHE substrate 406 from the first impedance 414 to the current input 410, past the surface of the first nanomagnet 402. The GSHE substrate 406 employs the spin Hall effect to split off up spin electrons e+ and the down spin electrons e− in a manner that induces the first nanomagnet 402 to be in the second magnetic state, similar to the operation of the GSHE substrate 214 of
While the above operations illustrate how information is written to the switch 400 using the write unit 430, it is the application of bias voltages to the bias inputs 422, 424 to the read unit 432 that reads out the written information. To read out information, a positive bias voltage V+ is applied to the first bias input 422, and a negative bias voltage V− is applied to the second bias input 424. As discussed above in connection with the operation of the fixed magnets 205, 208 and nanomagnet 202 of
As a consequence, by providing suitable positive and negative voltages on the inputs 422, 424, the state of the circuit device 400 can be determined by the sign of the current at the current output 412. It will be appreciated that the magnitude of the output current (for either direction) can be adjusted by adjusting the magnitude of the bias voltages V+ and/or V−. As will be discussed below, adjustment of these voltages may be used to create combinatorial gates of the multiple units of the circuit device 400.
Given that the nanomagnet 404 (like the nanomagnet 402) has its easy axis along {circumflex over (Z)}, and the two fixed magnets 418 and 420 point along +{circumflex over (Z)} and −{circumflex over (Z)} respectively, so that Iout is governed by
depending on whether the nanaomagnet 404 points along (or aligns with) the first fixed magnet 418 or the second fixed magnet 420.
To see why the spin switch should give rise to the input-output characteristics in
A more detailed quantitative analysis can be carried out using a pair of Landau-Lifshitz-Gilbert (“LLG”) equations to model the pair of nanomagnets 402, 404 as two macrospins {circumflex over (m)}′ and {circumflex over (m)}, respectively, coupled by the dipolar interaction.
Here γ is the gyromagnetic ratio, α, α′, the damping parameter and Ns=MsV/μB, Ns′=(MsV)′/μB are the number of spins comprising each magnet (μB: Bohr magneton). Also,
={right arrow over (H)}=HkmZ{circumflex over (Z)}−Hdmyŷ−Hf{circumflex over (m)}′ (5a)
{right arrow over (H)}′=H′km′Z{circumflex over (Z)}−H′dm′yŷ−Hf{circumflex over (m)} (5b)
represent the easy axis fields (Hk, H′k), the demagnetizing fields (Hd, H′d) plus the dipolar fields.
An exact treatment of the dipolar fields would require a detailed consideration of the shape of each magnet, but the approximate expression in Eqs. 5(a) and 5(b) should be adequate with Hf=(MsAs)′/d2, Hb=(MsAs)/d2, Ms, Ms′ being the saturation magnetizations, As, As′, the areas (in x-z plane) and d, the distance (along x) between the magnets.
Since it is desired for the Write (first) nanomagnet 402 ({circumflex over (m)}′) to switch the Read (second) nanomagnet 404 ({circumflex over (m)}), it helps speed up the process if the forward interaction Hf is designed to be larger than the backward one Hb. The simplest way to achieve this is to make the write magnet 402 larger than the read magnet 404, but more sophisticated approaches based on engineering material parameters may be possible too.
The input-output characteristics shown in
α=0.01, H′k=Hk, H′d=Hd=50 Hk,
Hf=1.1Hk, Hb=0.9Hk
The normalizing factor Is,0 is defined as
Is,0≡qNs|γ|μ0Hk=(2q/
With Hk=200 Oe, Ms=106 A/m and magnet dimensions 100 nm×80 nm×1.6 nm, (
Is,c≈0.6,Is,0≈460 μA
Smaller critical currents are obtained if a forward to backward dipolar interaction ratio larger than the present one (11:9) is assumed.
Combinations of switches having the structure of the switch 400 necessarily involve connecting the read unit 432 of first switch 400 with a write unit, not shown, of a further switch, not shown. Assuming the write unit of the further switch has a β of 8 as estimated earlier following Eq.(2), this would require an input current of ˜60 μA from the read circuit 432 of the first switch 430. With a ΔG of 0.25 mS as estimated earlier for 100 nm×80 nm cross-section, this would need a V˜250 mV. Note that that the read currents are approximately (⅛) of the write current and the simulations based on Eqs.(4) show that they do not interfere significantly with the writing process, except to slow it or speed it up a little. Indeed larger read currents should be possible allowing a fan-out of 2 to 4. This is a key feature arising from the charge to spin gain associated with the SHE.
In an exemplary operation, the first device 601 provides a positive current from its read unit 601b to the second device 602. In response to receiving the positive current, the second device 602 generates a negative current at its read unit 602b. The second device 602 thereby provides the negative current to the write unit 603a of the third device 603. The third device 603 receives the negative current and generates a positive current at its read unit 603b responsive thereto. The third device 603 provides the positive current to the write unit 601a of the first device 601 via the read unit 603b. The first device 601 receives the positive current and generates a negative current therefrom. The first device 601 provides the negative current from its read unit 601b to the second device 602. Thus, due to the inverter operation provided by each of the devices 601, 602, 603, the current at the current output of the read unit 601b changes from a positive output, discussed further above, to a negative output. A corresponding change occurs in the output current at each of the devices 602, 603. Because there are an odd number of inverting devices 601, 602, 603, no steady state is reached and an oscillator is formed.
As discussed further above, it is also possible to manipulate the bias voltages to create more complex analog/digital logical structures. For example, it is possible to interconnect the spin switches having the design of the circuit device 400 to implement hardware neural networks like the non-limiting example shown in
In
In general, the plurality of devices 7021,1, 7021,2, 7022,1, etc. can be interconnected in a combinatorial manner to carry out any neural network design having a set of interconnected nodes and a set of weights associated with each of the nodes. The devices 7021,1, 7021,2, 7022,1, etc. represent the nodes, and the weights are implemented via the corresponding voltages V1,1, V1,2, V2,1, etc. provided to the bias inputs (e.g. inputs 422, 424) of each device 702i,j by the control circuit. Adjusting the size or area of the first (write) nanomagnet (e.g. nanomagnet 402) may also be used to adjust the weighting factors. For example, by making the first (write) nanomagnet smaller in a node x, y, it will require a greater sum of currents from the various devices that feed the node x, y.
Using present day technology it should be possible to implement weights large enough to exceed switching thresholds, but even subthreshold networks could find use in probabilistic logic as discussed for ASL in B. Behin-Aein, A. Sarkar and S. Datta, “Modeling spins and circuits for all-spin logic”, Proc. ESSDERC (2012), which is incorporated herein by reference in its entirety.
It should be noted that ordinarily it may be advisable to use resistances rj (e.g. 414, 416 of
Referring again to
One advantage of the devices of
Since the output current (see Eq. (1)) of each Read unit is a product of V (˜Xn) and mz (˜Yn), it is determined by XnYn which are all added up to drive the output magnet. If {X} is an exact match to {Y}, then the output voltage will be N, since every Xn*Yn will equal +1, being either +1*+1 or −1*−1. If {X} matches {Y} in (N−n) instances with n mismatches, the output will be N−(2*n) since every mismatch lowers output by 2. If the threshold for the output magnet is set to N−(2*Ne) then the output will respond for all {X} that matches the reference {Y} within a tolerance of Ne errors.
Other novel applications are possible based on the fact that since magnets provide the digitization, the voltages can be used for “weighting” instead of “gating.”
Below a simulation illustrating the operation of a multistage Boolean gate constructed using the basic circuit devices 400 discussed above is provided.
The first-stage devices 814, 816, 818 drive the second-stage device 820, which in turn drives the two third-stage devices 822 and 824. The two third-stage devices 822 and 824 drive the write unit output devices 810, 812. For generality, a capacitor C has been added in parallel with the resistor r in the write units of the devices 814, 816, 818, 820, 822, and 824.
Since this gate includes six switches/devices 814, 816, 818, 820, 822, and 824, each having a write and a read unit, the dynamics of twelve magnetization vectors {circumflex over (m)}1W, {circumflex over (m)}1R, . . . , {circumflex over (m)}6W, {circumflex over (m)}6R described by LLG equations (Eq. (4)) need to be modeled. An expression is needed for the spin currents driving the different write units which are derived from the read units of the previous stage. Again, this relationship is similar to that of
Both the read and write spin currents can be determined using the equivalent circuit for a single read unit driving a single write unit (
The total current flowing into the Write unit is the sum of the currents flowing through G1 and G2:
However, this is true of a single Read unit driving a single Write unit. With ni identical Write units driving no identical Read units the equivalent circuit is shown in
The Write spin current equals the amplification factor β times the charge current:
Finally the twelve LLG equations for the circuit of
Following are some results obtained from the solution of 44 coupled first-order differential equations, 36 for the three components of the twelve magnetization vectors, and 8 for the charge on each capacitor. All W magnets were initialized in the −1 state while the Read magnets were initialized in the +1 state.
It is assumed that VΔG equal to 1.5q|γ|Hk/β, with a TMR of 150% corresponding to ΔG/G=0.43. The time axis is normalized to |γ|Hk/(1+α2) and the currents are normalized to q|γ|Hk.
The three inputs were assumed to be +1, −1 and +1, causing both W and R magnets for 1 and 3 to change their states, while magnets 2W and 2R remain in their initial state (
Those skilled in the art will recognize that numerous modifications can be made to the specific implementations described above.
Referring now generally to
CMOS Versus Spin Switch (SS) for Neural Network:
CMOS neurons occupy hundreds to several thousands of μm2 with power consumption around 50-100 μW and operate at few MHz. The energy consumed is ˜tens of pJ. Typical spin switches (
Referring specifically to
The SS 500 operates as follows: if charge current, |Iin|>Ic (critical value), it produces enough spin current to flip the magnet {circumflex over (m)}′ hence {circumflex over (m)}. The output voltage depends on the direction of {circumflex over (m)} via: Vout=VΔG/G({circumflex over (m)}·{circumflex over (M)}) where G, ΔG are the sum and the difference of the conductance GP, GAP (parallel and anti-parallel) of the MTJ's respectively. The power P can be estimated as:
P≈V2(GAP+GP)=V2G˜10 μW, for V=Vth≈100 mV,G=(1.1 kΩ)−1.
Note that the SS 500 does not involve any crystalline materials and it should be possible to stack in 3D making it suitable for very high density neuromorphic computation [5].
SS for Synapses:
Thus,
More specifically,
where r is the resistance of the W unit. Typically Gi˜(1 kΩ)−1 and we would like to make r small enough so that we can ignore the currents going from one SS to other SS. Using t=2 nm, L=80 nm and the resistivity of Ta [4], r=ρL/Wt=80Ω/W(μm). The SS neuron 5005 has an intrinsic hysteresis activation function (
Training the Network:
Off-line training can be performed by smoothing the SS hysteresis function to make it differentiable and adapting known back-propagation (BP) methods. Alternatively, a weight perturbation (WP) method can handle non-differentiable activation functions and is suitable for hardware implementations and on-chip learning. Other possibilities include the extreme learning machine.
Once the weights have been determined using any of these methods they can be implemented through the voltages applied to the SS synapses, as we will show shortly with an example.
In particular,
SS Neural Network:
More specifically,
Specifically,
The present application claims the benefit of U.S. provisional application Ser. Nos. 61/933,290, filed Jan. 29, 2014 and 62/014,883, filed Jun. 20, 2014. The contents of both of these applications are hereby incorporated by reference in their entirety.
This invention was made with government support under CCF0939370 awarded by the National Science Foundation. The government has certain rights in the invention.
Number | Name | Date | Kind |
---|---|---|---|
20050104119 | Diorio | May 2005 | A1 |
20120176154 | Behin-Aein | Jul 2012 | A1 |
20140001524 | Manipatruni | Jan 2014 | A1 |
20140139265 | Manipatruni | May 2014 | A1 |
20140269035 | Manipatruni | Sep 2014 | A1 |
20150200003 | Buhrman | Jul 2015 | A1 |
20160042778 | Manipatruni | Feb 2016 | A1 |
20160173100 | Nikonov | Jun 2016 | A1 |
Entry |
---|
Behin—Aein et al., “Modeling circuits with spins and magnets for all-spin logic”, IEEE 2012. |
Srinivasan et al., “All-Spin Logic Device With Inbuilt Nonreciprocity”, IEEE Transactions on Magnetics, vol. 47, No. 10, Oct. 2011. |
Sharad et al., “Spin-Based Neuron Model With Domain-Wall Magnets as Synapse”, IEEE Transactions on Nanotechnology, vol. 11, No. 4, Jul. 2012. |
Diorio et al., “Adaptive CMOS: From Biological Inspiration to Systems-on-a-Chip”, Proceedings of the IEEE, vol. 90, No. 3, Mar. 2002. |
Kucic et al., “Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits”, IEEE 2001. |
Diorio, C., et al., A Single-Transistor Silicon Synapse. IEEE Transactions on Electron Devices, vol. 43, No. 11, 1972-1980, 1996. |
Low, A., et al., Basics of Floating-Gate Low-Dropout Voltage Regulators. Proceedings 43rd IEEE Midwest Symp. on Circuits and Systems, pp. 1048-1051. Lansing MI, Aug. 8-11, 2000. |
Srinivasan, V., et al., Floating-Gates Transistors for Precision Analog Circuit Design: An Overview. 48th Midwest Symposium on Circuits and Systems, IEEE, vol. 1, pp. 71-74. Covington, KY, Aug. 7-10, 2005. |
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20150269478 A1 | Sep 2015 | US |
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