Patent Application
20240429235
Integrated circuit (IC) fabrication usually includes two stages. The first stage is referred to as the front-end of line (FEOL). The second stage is referred to as the back-end of line (BEOL). In the FEOL, individual semiconductor devices components (e.g., transistor, capacitors, resistors, etc.) can be patterned in a wafer. In the BEOL, metal layers, vias, and insulating layers can be formed to get the individual components interconnected. The BEOL usually starts with forming the first metal layer on the wafer. The first metal layer is often called M0. More metal layers can be formed on top of M0, and these metal layers are often called M1, M2, and so on.
standard cell methodology is a popular method of designing IC devices, such as application-specific ICs. A standard cell usually includes a group of transistors and interconnect structures. A standard cell may provide a logic function (e.g., AND, OR, XOR, etc.), storage function (e.g., flipflop, latch, etc.), other types of functions, or some combination thereof. The height of a standard cell, which is the dimension along the vertical axis, may be defined as the number of metal tracks of the first metal layer (M0) that can fit inside the standard cell. The width of a standard cell, which is the dimension along the horizontal axis, may be defined as the number of poly (polycrystalline silicon) in the horizontal axis. The distance between two parallel poly that are immediately adjacent to each other is referred to as the contacted poly pitch (CPP). Scaling of the area of a standard cell, such as scaling the cell height and CPP, can be important to increase the number of transistors in the IC.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
The systems, methods, and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
A CFET architecture usually has NMOS (N-type metal-oxide-semiconductor) and PMOS (P-type metal-oxide-semiconductor) devices stacked on top of each other. CFET device can help with scaling the height of the standard cell. However, due to the tall structure, it can result in process complexity as well as high gate capacitance. Other types of FET architecture have been proposed, such as double-forked (E2) FET and double-forked dynamically doped (E2D2) FET. Even though these FET architectures device can support a CPP scaling with reduction of gate cap, they can result in complex standard cell routability and large cell height (e.g., in a direction along Y-axis).
Embodiments of the present disclosure may improve on at least some of the challenges and issues described above by providing CFETs with forked semiconductor structure structures. An example monolithic CFET architecture in the present disclosure may include a stack of two transistors, each of which may have two forked semiconductor structures that are misaligned along either the vertical axis or the horizontal axis of the standard cell. The CFET architecture can facilitate backside power delivery, e.g., with direct contact to the forked semiconductor structures from the backside.
In various embodiments of the present disclosure, a CFET may include a first transistor stacked over a second transistor. In an embodiment, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor. In another embodiment, the first transistor is a PMOS transistor, and the second transistor is a NMOS transistor. In yet another embodiment, both the first transistor and the second transistor are PMOS or NMOS transistors. The first transistor includes a first source region, a first drain region, a first channel region, and a first gate. The second transistor includes a second source region, a second drain region, a second channel region, and a second gate. The source or drain region in each transistor may have a forked structure, which includes a body and a branch section. The branch section includes one or more branches extending from a surface of the body. A branch may be a fin, nanoribbon, etc. The first gate may be over the second gate in a first direction, e.g., a direction along the vertical axis (e.g., Z axis) of the standard cell. The first gate or the second gate may include one or more gate electrodes, which may be separated from each other by a dielectric material. The first gate may be separated from the second gate by an insulative structure.
The first gate and second gate may be in a gate assembly that is between the branch section of a source region and the branch section of the drain region of the same transistor, e.g., in a direction along the horizontal axis (e.g., Y axis) of the standard cell. The gate assembly may be between two dielectric structures. The first gate and second gate may be between the two dielectric structures in a direction along an axis (e.g., X axis) that is perpendicular to the vertical axis and the horizontal axis of the standard cell. In some embodiments, a portion of a dielectric structure may be over a portion of the body of a source region or a drain region. The dielectric structures may prevent shortage between the gates and the source/drain contacts. For each transistor, the body of the source region and the body of the drain region may be at opposite sides of the gate assembly along both the X axis and the Y axis. For instance, the body of the source region and the body of the drain region are diagonally arranged relative to the gate assembly.
Such a CFET architecture can reduce gate cap as the source/drain and gate are on different planes. Also, the architecture can support significant or extreme CPP scaling due to lower gate spacer. With such CFET architecture, standard cell can be scaled to three M0 routing tracks. The CFET architecture can also provide easy access from the backside to both the bottom and the top device through direct contact. Low aspect ratio via from the backside can be implemented to access the top device with lower via resistance. Also, low aspect ratio via from the frontside can be implemented to access the top device with lower via resistance. Therefore, IC devices including CFETs with forked semiconductor structures in the present disclosure can have better performance than currently available IC devices.
It should be noted that, in some settings, the term “nanoribbon” has been used to describe an elongated semiconductor structure that has a substantially rectangular transverse cross-section (e.g., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe a similar structure but with a substantially circular or square transverse cross-sections. In the following, a single term “nanoribbon” is used to describe an elongated semiconductor structure independent of the shape of the transverse cross-section. Thus, as used herein, the term “nanoribbon” is used to cover elongated semiconductor structures that have substantially rectangular transverse cross-sections (possibly with rounded corners), elongated semiconductor structures that have substantially square transverse cross-sections (possibly with rounded corners), elongated semiconductor structures that have substantially circular or elliptical/oval transverse cross-sections, as well as elongated semiconductor structures that have any polygonal transverse cross-sections.
In the following, some descriptions may refer to a particular source or drain (S/D) region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor or diode is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because, as is common in the field of FETs, designations of source and drain are often interchangeable. Therefore, descriptions of some illustrative embodiments of the source and drain regions/contacts provided herein are applicable to embodiments where the designation of source and drain regions/contacts may be reversed.
As used herein, the term “metal layer” may refer to a layer above a substrate that includes electrically conductive interconnect structures for providing electrical connectivity between different IC components. Metal layers described herein may also be referred to as “interconnect layers” to clearly indicate that these layers include electrically conductive interconnect structures which may, but do not have to be, metal.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−8% of a target value, e.g., within +/−5% of a target value or within +/−2% of a target value, based on the context of a particular value as described herein or as known in the art. Also, the term “or” refers to an inclusive “or” and not to an exclusive “or.”
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).
The description may use the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of CFET with forked semiconductor structures as described herein.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation.
Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
Various IC devices with CFET with forked semiconductor structure as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.
As shown in
The drain region 120 is also a forked region. The drain region 120 includes a body section (“body”) 123 and three branch sections (“branches”) 125 (individually referred to as “branch section 125” or “branch 125”). The branches 125 are stacked along the Z axis. Even though
The channel region 107 is between the source region 110 and the drain region 120. In the embodiments of
In some embodiments, two or all of the source region 110, drain region 120, and channel region 107 may be formed using a single fabrication process, e.g., an epitaxial deposition process. In other embodiments, the source region 110, drain region 120, and channel region 107 may be formed separately, e.g., using separate epitaxial deposition processes. In some embodiments, the body and branches in the source region 110 or the drain region 120 may be formed using a single fabrication process. In other embodiments, the body and branches in the source region 110 or the drain region 120 may be formed using separate fabrication processes. In an example, the branches 115, the channel region 107, and the branches 125 may be formed using a single fabrication process, and the bodies 113 and 123 may be formed separately.
The source region 110 and drain region 120 may each include a semiconductor material with dopants. In some embodiments, the source region 110 and drain region 120 have the same semiconductor material, which may be the same as the channel material of the channel region 107. A semiconductor material of the source region 110 or drain region 120 may be a Group IV material, a compound of Group IV materials, a Group III/V material, a compound of Group III/V materials, a Group II/VI material, a compound of Group II/VI materials, or other semiconductor materials. Example Group II materials include zinc (Zn), cadmium (Cd), and so on. Example Group III materials include aluminum (Al), boron (B), indium (In), gallium (Ga), and so on. Example Group IV materials include silicon (Si), germanium (Ge), carbon (C), etc. Example Group V materials include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and so on. Example Group VI materials include sulfur(S), selenium (Se), tellurium (Te), oxygen (O), and so on. A compound of Group IV materials can be a binary compound, such as SiC, SiGe, and so on. A compound of Group III/V materials can be a binary, tertiary, or quaternary compound, such as GaN, InN, and so on. A compound of Group II/VI materials can be a binary, tertiary, or quaternary compounds, such as CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, ZnTe, CdZnTe, CZT, HgCdTe, HgZnTe, and so on.
In some embodiments, the dopants in the source region and the drain region are the same type. In other embodiments, the dopants of the source region and the drain region may be different (e.g., opposite) types. In an example, the source region has N-type dopants and the drain region has P-type dopants. In another example, the source region has P-type dopants and the drain region has N-type dopants. Example N-type dopants include Te, S, As, tin (Sn), Si, Ga, Se, S, In, Al, Cd, chlorine (CI), iodine (I), fluorine (F), and so on. Example P-type dopants include beryllium (Be), Zn, magnesium (Mg), Sn, P, Te, lithium (Li), sodium (Na), Ga, Cd, and so on.
In some embodiments, the source region 110 and drain region 120 may be highly doped, e.g., with dopant concentrations of about 1·1021 cm−3, in order to advantageously form Ohmic contacts with the respective S/D contacts (also sometimes interchangeably referred to as “S/D electrodes”), although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the source region and the drain region may be the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in the channel region 107, and, therefore, may be referred to as “highly doped” (HD) regions.
The channel region 107 may include one or more semiconductor materials with doping concentrations significantly smaller than those of the source region and the drain region. For example, in some embodiments, the channel material of the channel region 107 may be an intrinsic (e.g., undoped) semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within the channel material, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the channel material is still significantly lower than the dopant level in the source region and the drain region, for example below 1015 cm−3 or below 1013 cm−3. Depending on the context, the term “S/D terminal” may refer to a S/D region or a S/D contact or electrode of a transistor.
A channel material may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, a channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from Group II of the periodic table (e.g., Zn, Cd, Hg), and a second sub-lattice of at least one element of Group IV of the periodic table (e.g., C, Si, Ge, Sn, Pb). In some embodiments, the channel material is an epitaxial semiconductor material deposited using an epitaxial deposition process. The epitaxial semiconductor material may have a polycrystalline structure with a grain size between about 2 nm and 100 nm, including all values and ranges therein.
For some example N-type transistor embodiments (i.e., for the embodiments where the FET 100 is an NMOS transistor), the channel material may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel material may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel material, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel material may be relatively low, for example below 1015 dopant atoms per cubic centimeter (cm−3), and advantageously below 1013 cm−3. These materials may be amorphous or polycrystalline, e.g., having a crystal grain size between 0.5 nanometers and 100 nanometers.
For some example P-type transistor embodiments (i.e., for the embodiments where the FET is a PMOS transistor), the channel material may advantageously be a Group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel material may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel material, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 1015 cm−3, and advantageously below 1013 cm−3. These materials may be amorphous or polycrystalline, e.g., having a crystal grain size between 0.5 nanometers and 100 nanometers.
In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, aluminum zinc oxide, or tungsten oxide. In general, for a thin-film transistor (TFT), the channel material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, molybdenum disulfide, n- or P-type amorphous or polycrystalline silicon, monocrystalline silicon, germanium, indium arsenide, indium gallium arsenide, indium selenide, indium antimonide, zinc antimonide, antimony selenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, black phosphorus, zinc sulfide, indium sulfide, gallium sulfide, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back-end fabrication to avoid damaging other components, e.g., front-end components such as logic devices.
As noted above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. IGZO has high electron mobility compared to other semiconductors, e.g., in the range of 20-50 times than amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors are typically characterized by high band gaps, low-temperature process compatibility, and low fabrication cost relative to other semiconductors.
IGZO can be deposited as a uniform amorphous phase while retaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula InGaO3 (ZnO)5. Another example form of IGZO has an indium: gallium: zinc ratio of 1:2:1. In various other examples, IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain tertiary dopants such as aluminum or nitrogen.
Even though not shown in
Although a few examples of materials from which the support structure may be formed are described here, any material that may serve as a foundation upon which an IC may be built falls within the spirit and scope of the present disclosure. In various embodiments, the support structure may include any such substrate, possibly with some layers and/or devices already formed thereon, not specifically shown in the present figures. As used herein, the term “support” does not necessarily mean that it provides mechanical support for the IC devices/structures (e.g., transistors, capacitors, interconnects, and so on) built thereon. For example, some other structure (e.g., a carrier substrate or a package substrate) may provide such mechanical support and the support structure may provide material “support” in that, e.g., the IC devices/structures described herein are build based on the semiconductor materials of the support structure. However, in some embodiments, the support structure may provide mechanical support.
The gate assembly 130 includes three gate electrodes 133 (individually referred to as “gate electrode 133”), each of which is over a section of the channel region 107. A gate electrode is electrically conductive and may be electrically coupled to a metal layer at the frontside or backside. A gate electrode may include one or more electrical conductors, such as poly, metal, other types of electrical conductors, or some combination thereof. The gate assembly 130 also includes dielectric structures 135 (individually referred to as “dielectric structure 135”), which can separate the gate electrodes 133 from the channel region 107. A dielectric structure 135 includes one or more dielectric materials. At least a portion of a dielectric structure 135 is between a gate electrode 133 and the corresponding section of the channel region 107 along the Z axis. In other embodiments, the number of gate electrodes 133 or dielectric structures 135 may be different.
The gate assembly is between the dielectric layers 160 and 170. The dielectric layer 160 extends to the edge of the branches 115 in a direction along the Y axis, and the dielectric layer 170 extends to the edge of the branches 125 in the opposite direction along the Y axis. The dielectric layer 160 or 170 includes one or more dielectric materials. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, and so on.
As shown in
The bodies 113 and 123 are at opposite sides of the combined structure in the direction along the X axis. Also, the bodies 113 and 123 are at opposite sides of the combined structure in the direction along the Y axis. In some embodiments, the bodies 113 and 123 are diagonally arranged with respect to the gate assembly 130. As shown in
The architecture of the FET 100 shown in
As shown in
The drain region 220 is also a forked region. The drain region 220 includes a body section (“body”) 223 and three branch sections (“branches”) 225 (individually referred to as “branch section 225” or “branch 225”). The branches 225 are stacked along the Z axis. Even though
The channel region is between the source region 210 and the drain region 220. In the embodiments of
In some embodiments, the source region 210, drain region 220, and channel region may be formed using a single fabrication process, e.g., an epitaxial deposition process. In other embodiments, the source region 210, drain region 220, and channel region may be formed separately, e.g., using separate epitaxial deposition processes. In some embodiments, the body and branches in the source region 210 or the drain region 220 may be formed using a single fabrication process. In other embodiments, the body and branches in the source region 210 or the drain region 220 may be formed using separate fabrication processes. In an example, the branches 215, the channel region, and the branches 225 may be formed using a single fabrication process, and the bodies 213 and 223 may be formed separately.
The gate assembly 230 includes three gate electrodes 233 (individually referred to as “gate electrode 233”), each of which is over a section of the channel region. A gate electrode is electrically conductive and may be electrically coupled to a metal layer at the frontside or backside. A gate electrode may include one or more electrical conductors, such as poly, metal, other types of electrical conductors, or some combination thereof. The gate assembly 230 also includes dielectric structures 235 (individually referred to as “dielectric structure 235”), which can separate the gate electrodes 233 from the channel region. A dielectric structure 235 includes one or more dielectric materials. At least a portion of a dielectric structure 235 is between a gate electrode 233 and the corresponding section of the channel region along the Z axis. In other embodiments, the number of gate electrodes 233 or dielectric structures 235 may be different.
The gate assembly is between the dielectric layers 260 and 270. The dielectric layer 260 extends to the edge of the branches 215 in a direction along the Y axis, and the dielectric layer 270 extends to the edge of the branches 225 in the opposite direction along the Y axis. The dielectric layer 260 or 270 includes one or more dielectric materials. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, and so on.
As shown in
The bodies 213 and 223 are at opposite sides of the combined structure in the direction along the X axis. Also, the bodies 213 and 223 are at opposite sides of the combined structure in the direction along the Y axis. As shown in
The CFET 310 includes an FET 320 and another FET 330. The FETs 320 and 330 are stacked along the Z axis. The FET 320 is on top of the FET 330 in the embodiments of
The FET 320 includes a source region 322 and a drain region 324, each of which has a forked structure with a body and branches extending from a surface of the body. The body of the source region 322 is between two source contacts 323. The body of the drain region 324 is between two drain contacts 337. The FET 330 includes a source region 332 and a drain region 334, each of which has a forked structure. The body of the source region 332 is between two source contacts 333. The body of the drain region 334 is between two drain contacts 337. The FET 320 may be an embodiment of the FET 100 in
The FET 320 also includes a gate assembly 325 including a plurality of gate electrodes 326 and dielectric structures 328. The FET 330 also includes a gate assembly 335 including a plurality of gate electrodes 336 and dielectric structures 338. The gate electrodes 326 and the dielectric structures 328 may form an alternating pattern. Also, the gate electrodes 336 and the dielectric structures 338 may form an alternating pattern. The gate assembly 325 of the FET 320 is over the gate assembly 335 of the FET 330. In some embodiments, the gate assembly 325 may be aligned with the gate assembly 335 along the Z axis. The gate assembly 325 and gate assembly 335 may constitute a single gate assembly 305 of the CFET 310, which is between a dielectric layer 340 and another dielectric layer 350 along the X axis. In some embodiments, an electrical insulator 307 may separate the gate assembly 325 from the gate assembly 335. The electrical insulator 307 may be a dielectric material, hysteretic material, and so on. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, etc.
The frontside metal layer 360 is on top of the CFET 310. The frontside metal layer 360 includes structures 365 (individually referred to as “structure 365”). The backside metal layer 370 is under the CFET 310. The backside metal layer 370 includes structures 375 (individually referred to as “structure 375”). Each structure 365 or 375 is electrically conductive. A structure 365 or 375 may be a metal track. Even though not shown in
In
In
In
As shown in
The hybrid CFET 610 includes an FET 620 and another FET 630. The FET 620 includes a source region 622 and a drain region 624, each of which has a forked structure with a body and branches extending from a surface of the body. The body of the source region 622 is between two source contacts 623. The body of the drain region 624 is between two drain contacts 637. The FET 630 includes a source region 632 and a drain region 634, each of which has a forked structure. The body of the source region 632 is between two source contacts 633. The body of the drain region 634 is between two drain contacts 637.
The FET 620 also includes a gate assembly 625 including a plurality of gate electrodes 626 and dielectric structures 628. The FET 630 also includes a gate assembly 635 including a plurality of gate electrodes 636 and dielectric structures 638. The gate electrodes 626 and the dielectric structures 628 may form an alternating pattern. Also, the gate electrodes 636 and the dielectric structures 638 may form an alternating pattern. The gate assembly 625 of the FET 620 is over the gate assembly 635 of the FET 630. In some embodiments, the gate assembly 625 may be aligned with the gate assembly 635 along the Z axis. The gate assembly 625 and gate assembly 635 may constitute a single gate assembly 605 of the hybrid CFET 610, which is between a dielectric layer 640 and a dielectric layer 650 along the X axis. In some embodiments, an electrical insulator 607 may separate the gate assembly 625 from the gate assembly 635. The electrical insulator 607 may be a dielectric material, hysteretic material, and so on. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, etc.
The FETs 620 and 630 are stacked along the Z axis. The FET 620 is on top of the FET 630 in the embodiments of
The frontside metal layer 660 is on top of the hybrid CFET 610. The frontside metal layer 660 includes structures 665 (individually referred to as “structure 665”). The backside metal layer 670 is under the hybrid CFET 610. The backside metal layer 670 includes structures 675 (individually referred to as “structure 675”). Each structure 665 or 675 is electrically conductive. Even though not shown in
In
In
In
As shown in
The hybrid CFET 710 includes an FET 720 and another FET 730. The FET 720 includes a source region 722 and a drain region 724, each of which has a forked structure with a body and branches extending from a surface of the body. The body of the source region 722 is between two source contacts 723. The body of the drain region 724 is between two drain contacts 737. The FET 730 includes a source region 732 and a drain region 734, each of which has a forked structure. The body of the source region 732 is between two source contacts 733. The body of the drain region 734 is between two drain contacts 737.
The FET 720 also includes a gate assembly 725 including a plurality of gate electrodes 726 and dielectric structures 728. The FET 730 also includes a gate assembly 735 including a plurality of gate electrodes 736 and dielectric structures 738. The gate electrodes 726 and the dielectric structures 728 may form an alternating pattern. Also, the gate electrodes 736 and the dielectric structures 738 may form an alternating pattern. The gate assembly 725 of the FET 720 is over the gate assembly 735 of the FET 730. In some embodiments, the gate assembly 725 may be aligned with the gate assembly 735 along the Z axis. The gate assembly 725 and gate assembly 735 may constitute a single gate assembly 705 of the hybrid CFET 710, which is between a dielectric layer 740 and a dielectric layer 750 along the X axis. In some embodiments, an electrical insulator 707 may separate the gate assembly 725 from the gate assembly 735. The electrical insulator 707 may be a dielectric material, hysteretic material, and so on. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, etc.
The FETs 720 and 730 are stacked along the Z axis. The FET 720 is on top of the FET 730 in the embodiments of
The frontside metal layer 760 is on top of the hybrid CFET 710. The frontside metal layer 760 includes structures 765 (individually referred to as “structure 765”). The backside metal layer 770 is under the hybrid CFET 710. The backside metal layer 770 includes structures 775 (individually referred to as “structure 775”). Each structure 765 or 775 is electrically conductive. Even though not shown in
In
In
In
As shown in
The hybrid CFET 810 includes an FET 820 and another FET 830. The FET 820 includes a source region 822 and a drain region 824, each of which has a forked structure with a body and branches extending from a surface of the body. The body of the source region 822 is between two source contacts 823. The body of the drain region 824 is between two drain contacts 837. The FET 830 includes a source region 832 and a drain region 834, each of which has a forked structure. The body of the source region 832 is between two source contacts 833. The body of the drain region 834 is between two drain contacts 837.
The FET 820 also includes a gate assembly 825 including a plurality of gate electrodes 826 and dielectric structures 828. The FET 830 also includes a gate assembly 835 including a plurality of gate electrodes 836 and dielectric structures 838. The gate electrodes 826 and the dielectric structures 828 may form an alternating pattern. Also, the gate electrodes 836 and the dielectric structures 838 may form an alternating pattern. The gate assembly 825 of the FET 820 is over the gate assembly 835 of the FET 830. In some embodiments, the gate assembly 825 may be aligned with the gate assembly 835 along the Z axis. The gate assembly 825 and gate assembly 835 may constitute a single gate assembly 805 of the hybrid CFET 810, which is between a dielectric layer 840 and a dielectric layer 850 along the X axis. In some embodiments, an electrical insulator 807 may separate the gate assembly 825 from the gate assembly 835. The electrical insulator 807 may be a dielectric material, hysteretic material, and so on. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, etc.
The FETs 820 and 830 are stacked along the Z axis. The FET 820 is on top of the FET 830 in the embodiments of
The frontside metal layer 860 is on top of the hybrid CFET 810. The frontside metal layer 860 includes structures 865 (individually referred to as “structure 865”). The backside metal layer 870 is under the hybrid CFET 810. The backside metal layer 870 includes structures 875 (individually referred to as “structure 875”). Each structure 865 or 875 is electrically conductive. Even though not shown in
In
In
In
The IC device 900 includes a plurality of semiconductor regions 910 (individually referred to as “semiconductor region 910”), a plurality of trench contacts 915 (individually referred to as “trench contact 915”), an electrically conductive structure 917, a plurality of gates 920, a plurality of dummy gates 930, a dielectric layer 940, another dielectric layer 945, a frontside metal layer including a plurality of structures 950, a backside metal layer including a plurality of structures 960, and eight vias 901-908. For the purpose of simplicity and illustrations, the trench contacts 915, electrically conductive structure 917, and vias 901-908 are not shown in
A semiconductor region 910 may be a source region or drain region in a CFET. A trench contact 915 may be a source contact or a drain contact. A gate 920 may be a gate in a CFET. In some embodiments, a gate 920 may include one or more gate electrodes. A dummy gate 930 may include one or more dummy gate electrodes. A dummy gate electrode may be electrically conductive but not electrically coupled to other components in the IC device 900 or other devices. A gate 920 or a dummy gate 930 may include an electrical conductor, such as metal, poly, and so on. The vias 901-907 are electrically conductive.
In
In
In
In
In
As shown in
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein and may include any of the embodiments of an IC device having CFET with forked semiconductor structure. In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package. Importantly, even in such embodiments of an MCP implementation of the IC package 2200, CFET with forked semiconductor structure may be provided in a single chip, in accordance with any of the embodiments described herein. The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be ESD protection dies, including CFET with forked semiconductor structure as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, any of the dies 2256 may include CFET with forked semiconductor structure, e.g., as discussed above; in some embodiments, at least some of the dies 2256 may not include any III-N diodes with N-doped wells and capping layers.
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices such as further RF (radio frequency) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. In some embodiments, the IC devices implementing CFET with forked semiconductor structure as described herein may also be implemented in/on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include, e.g., eDRAM, and/or spin transfer torque magnetic random-access memory (STT-MRAM).
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
In various embodiments, IC devices having CFET with forked semiconductor structure as described herein may be particularly advantageous for use as part of ESD circuits protecting power amplifiers, low-noise amplifiers, filters (including arrays of filters and filter banks), switches, or other active components. In some embodiments, IC devices having CFET with forked semiconductor structure as described herein may be used in PMICs, e.g., as a rectifying diode for large currents. In some embodiments, IC devices having CFET with forked semiconductor structure as described herein may be used in audio devices and/or in various input/output devices.
The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include another output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include another input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC device, including a gate assembly including a first gate and a second gate, the second gate over the first gate in a first direction; a first source region at a first side of the gate assembly; a first drain region at a second side of the gate assembly, the second side opposing the first side in a second direction perpendicular to the first direction; a second source region at the first side of the gate assembly; and a second drain region at the second side of the gate assembly, where the first gate is between the first source region and the first drain region in the second direction, the second gate is between the second source region and the second drain region in the second direction, at least part of the first source region is over at least part of the second source region in the first direction, and at least part of the first drain region is over at least part of the second drain region in the first direction.
Example 2 provides the IC device according to example 1, where at least one of the first source region, the first drain region, the second source region, and the second drain region has a forked structure, the forked structure including a first structure and a plurality of second structures, and an individual second structure protrudes from a surface of the first structure and is over another individual second structure in the first direction.
Example 3 provides the IC device according to example 2, further including an electrically conductive structure over the first section in the first direction.
Example 4 provides the IC device according to example 3, further including a layer including an electrically conductive material, where the layer is closer to the first source region than the second source region, and the electrically conductive structure is electrically coupled to the layer.
Example 5 provides the IC device according to any one of examples 2-4, where the first gate includes a plurality of gate electrodes that are separated from each other by one or more electrical insulators.
Example 6 provides the IC device according to any of the preceding examples, where the first gate, the first source region, and the first drain region are in a P-type FET, and the second gate, the second source region, and the second drain region are in an N-type FET.
Example 7 provides the IC device according to any of the preceding examples, where the gate assembly further includes an electrical insulator between the first gate and the second gate.
Example 8 provides an IC device, including a first semiconductor region including a first portion, a second portion, and a third portion, the third portion between the first portion and the second portion in a first direction; a second semiconductor region at a first side of the first semiconductor region, the second semiconductor region connected to the first portion of the first semiconductor region; a third semiconductor region at a second side of the first semiconductor region, the third semiconductor region connected to the second portion of the first semiconductor region, the first side opposing the second side in in a second direction that is perpendicular to the first direction; and an electrically conductive structure over the third portion of the first semiconductor region a third direction that is perpendicular to the first direction or the second direction.
Example 9 provides the IC device according to example 8, further including a first dielectric layer over the first portion and the third portion of the first semiconductor region in the second direction; and a second dielectric layer over the second portion and the third portion of the first semiconductor region in the second direction, where the electrically conductive structure is between a portion of the first dielectric layer and a portion of the second dielectric layer in the second direction.
Example 10 provides the IC device according to example 8 or 9, where the electrically conductive structure is a first electrically conductive structure, and the IC device further includes a second electrically conductive structure over the second semiconductor region in the third direction; and a third electrically conductive structure over the third semiconductor region in the third direction.
Example 11 provides the IC device according to example 10, further including a fourth electrically conductive structure over the second semiconductor region in the third direction, where the second semiconductor region is between the second electrically conductive structure and the fourth electrically conductive structure in the third direction.
Example 12 provides the IC device according to any one of examples 8-11, where the electrically conductive structure is separated from the third portion of the first semiconductor region by an electrical insulator.
Example 13 provides the IC device according to any one of examples 8-12, further including a fourth semiconductor region over the first semiconductor region in the third direction; and another electrically conductive structure over a portion of the fourth semiconductor region.
Example 14 provides the IC device according to any one of examples 8-13, where the first semiconductor region includes a fin or a nanoribbon.
Example 15 provides an IC device, including a structure including a plurality of electrically conductive structures; a first semiconductor region including a first body and a plurality of first branches extending from the first body; and a second semiconductor region including a second body and a plurality of second branches extending from the second body, where: the plurality of first branches is at a first side of the structure, the plurality of second branches is at a second side of the structure, the second side opposes the first side in a direction, and an individual electrically conductive structure is between an individual first branch and an individual second branch in the direction.
Example 16 provides the IC device according to example 15, further including a third semiconductor region including a third body and a plurality of third branches extending from the third body; and a fourth semiconductor region including a fourth body and a plurality of fourth branches extending from the fourth body, where the plurality of third branches is at the first side of the structure, the plurality of fourth branches is the second side of the structure, and another individual electrically conductive structure is between an individual third branch and an individual fourth branch.
Example 17 provides the IC device according to example 16, where the plurality of first branches or the plurality of second branches is over a first portion of the structure in the direction, the plurality of third branches or the plurality of fourth branches is over a second portion of the structure in the direction, and the first portion is over the second portion in another direction that is perpendicular to the direction.
Example 18 provides the IC device according to any one of examples 15-17, where the structure further includes a first dielectric layer and a second dielectric layer, and the plurality of electrically conductive structures is between a portion of the first dielectric layer and a second dielectric layer in another direction that is perpendicular to the direction.
Example 19 provides the IC device according to example 18, where another portion of the first dielectric layer is between a portion of an individual first branch and a portion of another individual first branch, and another portion of the second dielectric layer is between a portion of an individual second branch and a portion of another individual second branch.
Example 20 provides the IC device according to any one of examples 15-19, where an individual first branch or an individual second branch includes a fin or a nanoribbon.
Example 21 provides an IC package, including the IC device according to any one of examples 1-20; and a further IC component, coupled to the device.
Example 22 provides the IC package according to example 21, where the further IC component includes one of a package substrate, an interposer, or a further IC die.
Example 23 provides the IC package according to example 21 or 22, where the IC device according to any one of examples 1-20 may include, or be a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.
Example 24 provides an electronic device, including a carrier substrate; and one or more of the IC device according to any one of examples 1-20 and the IC package according to any one of examples 21-23, coupled to the carrier substrate.
Example 25 provides the electronic device according to example 24, where the carrier substrate is a motherboard.
Example 26 provides the electronic device according to example 24, where the carrier substrate is a PCB.
Example 27 provides the electronic device according to any one of examples 24-26, where the electronic device is a wearable electronic device or handheld electronic device.
Example 28 provides the electronic device according to any one of examples 24-27, where the electronic device further includes one or more communication chips and an antenna.
Example 29 provides the electronic device according to any one of examples 24-28, where the electronic device is an RF transceiver.
Example 30 provides the electronic device according to any one of examples 24-28, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver.
Example 31 provides the electronic device according to any one of examples 24-30, where the electronic device is a computing device.
Example 32 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a base station of a wireless communication system.
Example 33 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a user equipment device of a wireless communication system.
Example 34 provides processes for forming the IC device according to any one of claims 1-20.
Example 35 provides processes for forming the IC package according to any one of the claims 21-23.
Example 36 provides processes for forming the electronic device according to any one of the claims 24-33.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
