This application claims priority to German Application No. 102016111911.3 filed Jun. 29, 2016, which is incorporated herein by reference in its entirety.
The invention relates to a component with functional layers covered by a thin-layer covering as well as to a method for its production.
MEMS components and especially micro-acoustic components require a package, in which the functional structures of the component are protected in a mechanically secure manner and preferably encapsulated in a cavity. For producing such a package, various technologies are known, which can already be carried out at the wafer level and, therefore, allow for a cost-effective parallel processing of the components on the wafer level. It is, for example, possible to apply a wafer with component chips produced thereon onto a carrier, such as a laminate or a multilayer ceramic, in a flip chip design and to seal it against the carrier using a cover layer. It is also possible to arrange the functional structures of the component in a frame and to use this frame as a housing wall and spacer for a cover wafer.
A cost-effective method, which in addition leads to components having a small construction height, are the packages called TFP (thin film package), in which the functional structures are covered by means of a mechanically stable thin-layer design. The cavity is provided for by means of a structured sacrificial layer, which is covered together with the functional structures by the thin-layer covering, defining the cavity underneath the thin-layer covering, and being dissolved away again through structure openings in the thin-layer covering in a subsequent method step. In another step, the structure openings are sealed again.
Besides the cost advantages and the small dimensions of the TFP package, however, such components also have disadvantages. The connecting faces of a component encapsulated in this way are arranged on the chip surface, that is, between the thin-layer coverings on the surface of the carrier. In order to solder such a component to a circuit environment, e.g. a circuit board, bumps must then be used, which have a sufficient stand-off, which must have at least the height of the thin-layer covering plus a tolerance value.
It is, furthermore, disadvantageous that the technically most advantageous arrangement of the connecting faces on the carrier does not necessarily coincide with a required footprint as is customary for standardized components. In addition, a bump requires a relatively large area, which is, however, limited on the surface of the carrier, especially in the case of miniaturized components. If the distribution of the connecting faces on the carrier is adapted to a required footprint, the conductor paths required for this purpose take up additional space on the surface of the carrier, which further increases the size of the component.
The task of the present invention is, therefore, to specify a component with a thin-layer covering, whereby the component avoids the aforementioned disadvantages.
This task is achieved according to the invention by a component having the features of claim 1. Advantageous embodiments of the invention and a method for producing the component are to be learned from additional claims.
A component having a thin-layer covering is specified in which a first wiring layer is applied onto or over the thin-layer covering. In this way, sacrificing valuable space on the surface of the carrier for connection purposes is avoided so that the space required for this purpose is saved on the carrier.
The first wiring layer comprises structured conductor traces, which are connected to at least one CONNECTING FACE on the surface of the carrier but preferably connect two or more connecting faces on the surface of the carrier to one another. The connection faces on the surface constitute the connectors of the functional structure on the carrier, such that the connection of the different connectors of the functional structure is realized in the wiring layer.
The invention has the additional advantage that it is compatible with known TFP packages and extends and improves these in terms of functionality.
In one embodiment of the invention, the first wiring layer comprises solderable connecting pads. This means that the outer connections of the functional structure are displaced to a layer above the thin-layer covering. Solderable connecting pads may be present that are displaced only from the surface of the carrier to the surface of the thin-layer covering. Additional solderable connection faces may constitute common nodes that are connected with a series of connection faces on the surface of the carrier. The solderable connecting pads over the thin-layer covering have the additional advantage that the stand-off for the joining of the AP with a circuit environment no longer needs to take into account the stand-off due to the component height. Solderable connecting pads, which constitute bus bars for a series of connecting faces, can thus reduce the number of external connectors.
The solderable connecting pads above the thin-layer covering have the additional advantage that they may be realized at nearly arbitrary horizontal positions, and thus an adaptation of the technically optimal distribution of the connection faces relative to the functional structures on the surface of the carrier may adapt to a desired pin layout or to a desired footprint for a circuit environment.
In one embodiment of the invention, the thin-layer covering comprises several partial layers. One of the partial layers is a mechanically stable layer, which can ensure the stability of the cavity enclosed thereunder at least for the next method steps. Another partial layer serves as a sealing layer for sealing the structure openings, which are conducted through the mechanically stable layer in order to dissolve away the sacrificial layer underneath the thin-layer covering. The first wiring level is preferably arranged between two partial layers of the thin-layer covering, i.e. integrated into the structure of a traditional thin-layer covering.
The invention is preferably used for components that require a cavity above their functional structures in order to function free of interference. The functional structure can, therefore, advantageously be selected from a MEMS structure, a micro-acoustic structure, a SAW structure, a BAW structure, or a GBAW structure.
A MEMS structure comprises a micro-structured 3D structure, which is preferably produced from a crystalline semiconductor body and which comprises at least one movable part, such as a membrane or a contact tab.
In the form of suitable transducer structures, a SAW structure can be applied directly on a carrier comprising a piezoelectric material.
For a BAW structure, a layer sequence is applied onto the carrier, whereby the layer sequence comprises, for example, an acoustic mirror, a first electrode above it, a piezoelectric layer, and a second electrode. The acoustic mirror comprises at least one pair of layers respectively having relatively high and relatively low acoustic impedance, which layers are formed on the one hand from a hard metal and on the other hand from a lightweight material such as SiO2, polymer, or aluminum.
A GBAW structure comprises an electro-acoustic transducer and an acoustic waveguide layer, which can be arranged above or underneath the transducer electrodes.
As noted, the component comprises a connection face which is arranged on the carrier and is connected with both the functional structure and, via one of the structured conductor traces, with the first wiring layer.
In one embodiment, the number of the connection faces and the number of solderable connection pads may be different. In addition or alternatively, connecting faces and connecting pads may have a different distribution or a different connection pattern.
Individual solderable connecting pads may coincide, in terms of their horizontal position, with the position of connection faces on the carrier surface, but electrically are connected with a different connection face at a different location on the surface of the carrier. In this way, a consolidation of electrical connections is achieved on one plane above the carrier surface, which is especially space-saving. Furthermore, it is therefore achieved that the solderable connecting pads are produced in a desired pin layout. In other words, a physically optimal distribution of connection faces on the carrier is adapted to a desired pin layer or a wiring standard.
The first wiring layer comprises at least structured conductor traces, but may additionally also comprise circuit components connected thereto, which circuit components may likewise be present on the surface of the thin-layer covering or be integrated into the thin-layer covering. Such circuit components may be passive circuit components, for example resistance structures, capacitances or inductances, which may be comprised of correspondingly structured conductor trace segments. Such circuit components can supplement or expand the function of the component.
In a further embodiment of the invention, a second wiring layer is arranged between two partial layers of the thin-layer structure, wherein at least one electrically insulating partial layer that is arranged between the two wiring layers provides for a sufficient insulation of the two wiring layers. Both wiring layers respectively comprise structured conductor traces that, overall, may connect the layers with one another in an electrically conductive manner. In this instance, the first wiring layer preferably has no solderable connecting pads; rather, these are then arranged in the second wiring layer, since they are more easily accessible there. In exceptional cases, it may be advantageous to alternatively or additionally provide still more connecting pads in the first metallization layer.
The thin-layer covering may be used variably and may be used for covering individual structures or entire groups of functional structures. It is crucial that the thin-layer covering still remains sufficiently mechanically stable if it spans across a relatively large area with functional structures. At least one dimension of a, for example, rectangular or approximately rectangular thin-layer covering should in this respect not exceed the limit value for sufficient mechanical stability.
A component that works with acoustic waves and that comprises transducer structures producing acoustic waves as functional structures, better electroacoustic transducers, often times comprises several functional structures that are acoustically separated from one another and only connected to one another electrically. In such cases, it can be advantageous to provide individual functional structures with a respective separate thin-layer covering.
By means of the invention, it is now possible to connect the individual functional structures to one another in a wiring layer above the thin-layer covering. The connection of the functional structures may be realized in the first or a second wiring layer.
A method for producing a component according to the invention with a thin-layer covering and a wiring level is explained below with reference to the exemplary embodiments and the associated figures. The figures are used solely for a better understanding of the invention, and are, therefore, partially only schematic and not true to scale. For a better understanding, individual parts can be illustrated in an enlarged or scaled-down manner.
A thin-layer covering DSA spans the functional structure FS, which is embedded in a cavity below this. The connection face AF remains free of the thin-layer covering DSA. Inasmuch, the arrangement coincides with known thin-layer coverings.
According to the invention, a first wiring layer VE1 is now applied on the surface of the thin-layer covering DSA or in said thin-layer covering, which first wiring layer VE1 comprises structured conductor traces that are advantageously routed to the highest point of the thin-layer covering. A connecting pad AP is then advantageously executed there, which connecting pad AP has a solderable metallization and serves for the connection of the functional structure to an external circuit environment.
Structured conductor traces that form a first wiring layer VE1 are now directed on the surface of the thin-layer covering DSA. In the shown instance, each of the connection faces AF on the surface of the carrier TR is connected with a separate connecting pad AP on the top side of the thin-layer covering DSA. However, it is also possible to connect multiple connection faces AF with a common connecting pad AP, since a wiring between different connection pads AP is enabled via the first wiring layer VE1.
While the thin-layer covering DSA is depicted as a uniform material in
In the exemplary embodiment according to
Here a hermetic layer HS that covers the entire thin-layer covering (with the exception of the connecting pads AP) is applied as a final layer which, however, is not required in all embodiments.
In this embodiment, the metallization for the first wiring layer VE1 is still to be applied and structured before the application of the sealing layer VS.
After the application and structuring of the sealing layer VS, a second wiring layer VE2 is applied and structured in the form of a metallization. This contacts the metallization of the first wiring layer VE1 in a structural gap of the sealing layer VS in which a metallization of said first metallization layer VE1 is uncovered. There, a structured conductor trace of the first wiring layer VE1 may be extended to a pad. The second wiring layer is subsequently routed to the surface of the sealing layer VS and there is provided with a solderable connecting pad AP, advantageously at the highest point. This structure is depicted in the left part of the figure.
As depicted in
An additional possibility to integrate a wiring layer VE into the design of a thin-layer covering is depicted in
After generation of a solderable connecting pad AP, an additional hermetic layer HS2 is generated, especially a passivation of the metallization of the first wiring layer VE1.
Using various schematic cross sections,
Above the functional structures FS, a sacrificial layer OS is now applied and structured such that it defines the areas for the subsequent cavities underneath the thin-layer covering DSA. The sacrificial layer OS preferably comprises an easily structurable material, especially a lacquer layer.
A mechanically stable layer MSS is now applied onto the entire surface of the structured sacrificial layer OS; for example, an SiO2 layer is applied by means of sputtering or CVD.
Subsequently, openings OE are produced in the mechanically stable layer MSS; through these openings, the sacrificial layer underneath the mechanically stable layer MSS can now be dissolved away. One or more openings OE can be provided for each provided cavity or for each thin-layer covering DSA.
In the next step, the openings OE are sealed using a sealing layer VS. The sealing layer VS is preferably applied onto the entire surface and subsequently structured, exposing the connecting faces AF as shown in
The sealing layer VS is preferably an organic lacquer or a polymer.
The hermetic layer HS is preferably a thick and electrically insulating layer, especially a silicon nitride layer.
Using schematic cross sections,
The mechanically stable layer may be a sufficiently thick SiO2 layer. However, the mechanically stable layer may also be multi-layer and comprise a silicon nitride layer in addition to the SiO2 layer or as an alternative to this. However, other multi-layer embodiments are also possible insofar as they may produce a sufficient mechanical stability.
The metallization of the first wiring layer VE1 may be executed from a suitable metal and comprise aluminum, copper, nickel or silver. The metallization may also be multi-layer.
In the next process step, openings OE are now generated in an uncovered region of the mechanically stable layer MSS, for example via dry etching. The sacrificial layer OS is subsequently extracted through these openings OE, preferably wet-chemically with solvent or, depending on the material of the sacrificial layer OS, with an etchant.
In the next step, according to
The sealing layer VS is preferably applied in a liquid state, or even better a viscous state, [so] that it cannot penetrate into the openings OE. The sealing layer VS may comprise a coating in which a polymer is dissolved in a solvent. However, a liquid polymer may also be used. The polymer may be arbitrarily selected and, for example, may consist of epoxide, acrylate, polyimide or other suitable polymers or coatings, or comprise such materials.
In the next step, the solderable connecting pads AP are generated at the points at which metallizations of the first wiring layer VE1 or of the connection faces AF are free of sealing layer VS and hermetic layer HS. A solderable connecting pad AP may comprise various metals that may make the metallization of the first wiring layer VE solderable. The solderable connecting pad AP may comprise a gold layer that is advantageously applied over a nickel layer. Copper is also suitable for the generation of a solderable connecting pad AP.
Depending on the required layer thickness, various process possibilities are suitable for the application of the solderable connecting pad AP. A base metallization or a thin metal layer may be sputtered on. A thicker layer may also be generated via sputtering, or also via vapor deposition. However, it is also possible to reinforce (for example galvanically) an applied primary thin layer or an uncovered metal layer by means of metal deposition from solution. The final layer, preferably comprising gold, may be vapor-deposited.
Using the process stages B through F (See
In the next step according to
Finally, a solderable connecting pad AP is generated in the region of the free areas FF and provided with bumps BU.
Using various process stages b through h,
In the next step, according to
A desired number of openings OE is subsequently generated in the mechanically stable layers MSS of each thin-layer covering, and the sacrificial layer is removed through these openings OE. The openings may be generated via dry etching.
If an organic coating is used as a sacrificial layer, the extraction of the sacrificial layer preferably takes place with an organic solvent.
According to
As
A hermetic layer HS is subsequently deposited over the entire arrangement and structured, wherein free areas FF for the layer connecting pads remain free.
A metallization is now applied and structured over the hermetic layer HS to produce the first wiring layer VE1. It thereby contacts the previously uncovered connection faces AF.
Since the sealing layer VS is already covered under the hermetic layer HS, now only the upper regions of the first wiring layer VE1 are still uncovered or unprotected. For their protection, a solderable connecting pad is initially generated on the first wiring layer. If the solderable connecting pad AP comprises a gold layer, for example, this may serve to mask the connecting pads AP from the remaining wiring layer or the remaining structures of the wiring layer if these receive an oxide passivation with the aid of an oxidation process. The gold layer, or that connecting pad AP provided with a gold layer, remains untouched by this.
The invention could be explained in reference to just a few exemplary embodiments and is, therefore, not limited to these. For the invention, it is essentially insignificant what type of structures may be encapsulated under the thin-layer covering DSA. MEMS components are preferably covered that, for interference-free operation, may not come into direct contact with a covering, and therefore require a cavity for encapsulation.
SAW and BAW modules are preferably encapsulated, as well as MEMS components. Any thin-layer covering may cover individual functional structures or entire groups of functional structures. The complete interconnection of the functional structures may take place within one of the wiring layers. The external contact of the component or components may be provided at the wiring layer VE1, at the wiring layer VE2, and additionally via the connection faces AF at the layer of the carrier. The connection pads AP are preferably arranged at the highest point or points of the thin-layer covering, since there the smallest stand-off is possible, thus the smallest clearance from a circuit environment into which the component is introduced via soldering.
Number | Date | Country | Kind |
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10 2016 111 911.3 | Jun 2016 | DE | national |
Filing Document | Filing Date | Country | Kind |
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PCT/US2017/039229 | 6/26/2017 | WO | 00 |