COMPUTING ARRAY BASED ON 1T1R DEVICE, OPERATION CIRCUITS AND OPERATING METHODS THEREOF

Abstract
The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.
Description
BACKGROUND OF THE INVENTION
Technical Field

The present invention belongs to the field of microelectronic devices, and more particularly relates to a computing array based on 1T1R device, operation circuits and operating methods thereof.


Description of the Related Art

In the era of big data, the Moore's Law for integrated circuits, which improve the computational performance through the size reduction of nano-transistor logic devices, has been difficult to continue. The bottleneck problem of storage and computation separation in the traditional von Neumann computing architecture is highlighted, and the existing architecture and hardware cannot meet the demand for superior computing power in explosive growth of information.


Resistive Random Access Memory (RRAM), which has the characteristics such as low power consumption, high speed, high integration as well as information storage and calculation functions, can break through the limit of Moore's Law in the development of existing electronic devices, and thus is widely used in improving the speed of computer data processing. In the existing industrial integration technology, RRAM is mainly applied in the 1T1R device structure.


Chinese Patent No. 2014203325960 proposed a non-volatile Boolean logic operation circuit and an operating method thereof, which realizes a complete set of non-volatile Boolean logic operations through a back-to-back RRAM structure, but cannot realize circuit cascading, circuit integration and more complex computing functions.


SUMMARY OF THE INVENTION

In view of the above-described defects or improvement requirements in the art, the present invention provides a computing array based on 1T1R device, operation circuits and operating methods thereof, which aim to achieve a complete set of non-volatile Boolean logic operations, and to achieve more complex computing functions, while improving the compatibility of the computing circuits and simplifying the operation methods.


In order to achieve the above objective, according to a first aspect of the present invention, there is provided a computing array based on 1T1R device, which comprises: one or more 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays.


The 1T1R array includes 1T1R devices arranged in an array, word lines WL, bit lines BL and source lines SL; resistance states of the 1T1R devices include: High Resistance H and Low Resistance L; the 1T1R devices realize storage and processing of information through different resistance states; and the 1T1R devices in the same row are connected to the same bit line, the 1T1R devices in the same column are connected to the same bit line and source line, and through applying different signals to the word lines WL, the bit lines BL and the source lines SL, different operations are achieved and operation results are stored.


The 1T1R device includes a transistor and a resistive element; the transistor includes a substrate, a source, a drain, an insulating layer and a gate, in which the source is connected to the source line SL, and the gate is connected to the word line WL; the resistive element includes two end electrodes, one of which is connected to the bit line BL and the other of which is connected to the drain of the transistor; and the resistive element has a stacked structure with a nonvolatile resistance transition characteristic.


The resistance state of the 1T1R device can be reversibly transformed under the stimulation of an applied signal, namely, with the stimulation of an applied signal, the resistance state of the 1T1R device can be transformed from High Resistance to Low Resistance, and with the stimulation of another applied signal, the resistance state of the 1T1R device can be transformed from Low Resistance to High Resistance. By using the two resistance states of the 1T1R device, storage and processing of information can be achieved.


In a first embodiment of the first aspect of the present invention, the resistive element of the 1T1R device is RRAM; RRAM includes: an upper electrode, a functional layer and a lower electrode; the upper electrode is connected to the bit line BL, and the lower electrode is connected to the drain of the transistor.


The peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit, wherein:


The state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result.


An input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to a word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array.


An input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to a bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array.


An input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to a source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array.


The word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array.


An input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem.


A first input terminal of the control signal modem is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array.


An input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit.


The data input/output terminal Data, the address input terminal Address and the clock signal input terminal CLK of the state controller respectively serve as a data input/output terminal, an address input terminal and a clock signal input terminal of the computing array.


In the computing array based on 1T1R device, applied voltage pulses are used as input signals to perform logic operation, and the result of the logic operation is characterized by the final resistance state of the 1T1R device; the result of the logic operation can be non-volatilely stored in the resistance state of the device, the resistance state can be read by a read signal of a small current (generally at the nanoampere level) or a small voltage (generally 0.2V or less), and the resistance signal can be erased by applying a voltage pulse with a certain amplitude and pulse width.


In the computing array based on 1T1R device, Boolean logic operations are achieved in the 1T1R devices by applying different voltage pulse signals to the word lines, source lines and bit lines of the 1T1R array. The initial resistance state of the 1T1R device is defined as a logic signal I, in which I=0 when the initial resistance state of the 1T1R device is High Resistance, and I=1 when the initial resistance state of the 1T1R device is Low Resistance; the word line level voltage is defined as a logic signal VWL, in which VWL=0 when a zero-level pulse is applied to the word line, and VWL=1 when a forward voltage pulse is applied to the word line; the bit line level voltage is defined as a logic signal VBL, in which VBL=0 when a zero-level pulse is applied to the bit line, and VBL=1 when a forward voltage pulse is applied to the bit line; the source line level voltage is defined as a logic signal VSL, in which VSL=0 when a zero-level pulse is applied to the source line, and VSL=1 when a forward voltage pulse is applied to the source line; the result of the logical operation in the 1T1R device is non-volatilely stored in the 1T1R device, and when information stored in the 1T1R device is read, the resistance state of the 1T1R device is defined as a logic signal R, in which R=0 when the resistance state of the 1T1R device is High Resistance, and R=1 when the resistance state of the 1T1R device is Low Resistance; and a logical relationship between the logic signal I, the logic signal VWL, the logic signal VBL, the logic signal VSL, and the logic signal R is:






R=I·VWL+I·VWL·VBL+I·VWL·VBL·VSL+Ī·VWL·VBL·VST


In the computing array based on 1T1R device, Boolean logic operation are implemented in a single 1T1R device, and specifically, the operating method includes the following steps.


(1) Initializing the 1T1R device to obtain a logic signal I.


(2) Respectively applying a voltage pulse signal to a word line, a source line and a bit line to obtain a logic signal VWL, a logic signal VSL and a logic signal VBL.


(3) Reading a result of the logical operation, that is, a logic signal R.


By controlling values of the logic signals I, VWL, VBL and VSL, the following 16 Boolean logic operations can be implemented:


implementation of logic 0: I=0, VWL=0, VBL=p and VSL=q;


implementation of logic 1: I=1, VWL=0, VBL=p and VSL=q;


implementation of p logic: I=p, VWL=0, VBL=0 and VSL=q;


implementation of p logic: I=q, VWL=0, VBL=0 and VSL=p;


implementation of p logic: I=p, VWL=0, VBL=p and VSL=q;


implementation of q logic: I=q, VWL=0, VBL=p and VSL=q;


implementation of p+q logic: I=p, VWL=1, VBL=p and VSL=0;


implementation of p+q logic: I=1, VWL=p, VBL=0 and VSL=q;


implementation of p·q logic: I=0, VWL=p, VBL=q and VSL=0;


implementation of p·q logic: I=q, VWL=p, VBL=q and VSL=1;


implementation of p+q logic: I=1, VWL=1, VBL=p and VSL=q;


implementation of p+q logic: I=1, VWL=p, VBL=q and VSL=1;


implementation of p·q logic: I=q, VWL=1, VBL=0 and VSL=p;


implementation of p·q logic: I=p, VWL=1, VBL=0 and VSL=q;


implementation of p·q+p·q logic: I=p, VWL=q, VBL=p and VSL=p; and


implementation of p·q+p·q logic: I=q, VWL=p, VBL=q and VSL=q.


Further, by inputting a logic signal VWL=1 via the word line, a logic signal VBL=Vread via the bit line and a logic signal VSL=0 via the source line, the logic signal stored in the 1T1R device can be read, in which Vread is a voltage pulse signal applied when the resistance state of the 1T1R device is read.


In the present invention, symbols similar to I, VWL, VBL and VSL are used to denote logical signals with the same concept, and signals corresponding to different 1T1R devices are distinguished only by different subscripts


According to a second aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a 1-bit full adder, in which a sum s0 and a high-order carry c1 are calculated according to a logic signal a, a logic signal b and a low-order carry c0 that are input; the operation circuit comprises: a 1T1R array A1, a 1T1R array A2 and a 1T1R array A3; the 1T1R array A1 includes a 1T1R device Rb for calculating and storing intermediate data s0*, a word line signal corresponding to Rb is VWLb, a bit line signal corresponding to Rb is VBLb and a source line signal corresponding to Rb is VSLb; the 1T1R array A2 includes a 1T1R device Rc for calculating and storing the high-order carry c1, a word line signal corresponding to Rc is YWLc, a bit line signal corresponding to Rc is VBLc and a source line signal corresponding to Rc is VSLc; the 1T1R array A3 includes a 1T1R device Rs for calculating and storing the sum s0, a word line signal corresponding to Rs is VWLs, a bit line signal corresponding to Rs is VBLs and a source line signal corresponding to Rs is VSLs; and the intermediate data s0* calculated by the 1T1R array A1 and the high-order carry c1 calculated by the 1T1R array A2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array A3 through the data transmission circuit.


In conjunction with the second aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:


(S1-1) Inputting logic signals VWLc=1, VBLc=c0 and VSLc=c0 to write the input logic signal c0 into Rc of the 1T1R array A2; inputting logic signals VWLb=1, VBLb=a0 and VSLb=a0 to write the input logic signal a0 into Rb of the 1T1R array A1; inputting logic signals VWLs=1, VBLs=a0 and VSLs=a0 to write the input logic signal a0 into Rs of the 1T1R array A3.


(S1-2) Inputting logic signals VWLc=1, VBLc=a0 and VSLc=b0 to calculate a high-order carry c1=a0·b0+a0·c0+c0·b0 and store c1 in Rc of the 1T1R array A2; inputting logic signals VWLb=b0, VBLb=a0 and VSLb=a0 to calculate an intermediate result s0*=a0⊕b0 and store s0* in Rb of the 1T1R array A1; inputting logic signals VWLs=b0, VBLs=a0 and VSLs=a0 to calculate an intermediate result s0* and store s0* in Rs of the 1T1R array A3.


(S1-3) Reading the logic signal c1 stored in Rc of the 1T1R array A2; reading the logic signal s0 stored in Rb of the 1T1R array A1; inputting logic signals VWLs=c0, VBLs=s0* and VSLs=s0* to calculate a sum s0=a0⊕b0⊕c0 and store s0 in Rs of the 1T1R array A3.


(S1-4) reading the logic signal s0 stored in Rs of the 1T1R array A3.


According to a third aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a multi-bit step-by-step carry adder, in which sums s0˜n−1 and carry information cn are calculated according to input data a0˜n−1 and b0˜n−1 and carry information c0, and n represents the number of bits of the operation data, the operation circuit comprises: a 1T1R array D1, a 1T1R array D2 and a 1T1R array D3; the 1T1R array D1 includes n 1T1R devices R0b˜R(n−1)b for calculating and storing intermediate results s0˜n−1*, word line control signals corresponding to R0b˜R(n−1)b are respectively VWL0b˜VWL(n−1)b, bit line control signals corresponding to R0b˜R(n−1)b are respectively VBL0b˜VBL(n−1)b, and source line control signals corresponding to R0b˜R(n−1)b are respectively VSL0b˜VSL(n−1)b; the 1T1R array D1 is used for data backup; the 1T1R array D2 includes a 1T1R device Rn for calculating and storing carry data ci (i is an integer from 0 to n), a word line control signal corresponding to Rn is VWLn, a bit line control signal corresponding to Rn is VBLn and a source line control signal corresponding to Rn is VSLn; the 1T1R array D3 includes n 1T1R devices R0˜Rn−1 for calculating and storing addition operation results s0˜n−1, word line control signals corresponding to R0˜Rn−1 are respectively VWL0˜VWL(n−1), bit line control signals corresponding to R0˜Rn−1 are respectively VBL0˜VBL(n−1), and source line control signals corresponding to R0˜Rn−1 are respectively VSL0˜VSL(n−1); and the intermediate data s0˜n−1* calculated by the 1T1R array D1 and the carry information ci calculated by the 1T1R array D2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array D3 through the data transmission circuit.


In conjunction with the third aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:


(S2-1) Inputting logic signals VWL0˜(n−1), VBL0˜(n−1)=a0˜n and VSL0˜(n−1)=a0˜n, to write the input data a0˜n−1 into R0˜n−1 of the 1T1R array D3; inputting logic signals VWLn=1, VBLn=c0 and VSLn=c0 to write the carry information c0 into Rn of the 1T1R array D2, a word line input signal, a bit line input signal and a source line input signal of the 1T1R array D1 being the same as that of the 1T1R array D3.


(S2-2) Inputting logic signals VWL0˜(n−1)=b0˜n−1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to calculate intermediate results s0˜n−1=a0˜n−1⊕b0˜n−1 and store s0˜n−1* in R0˜n−1 of the 1T1R array D3; inputting logic signals VWL0b˜(n−1)b=b0˜n−1, VBL0b˜(n−1)b=a0˜n−1 and VSL0b˜(n−1)b=a0˜n−1 to calculate intermediate results s0˜n−1* and store s0˜n−1* in R0b˜(n−1)b, of the 1T1R array D1; inputting logic signals VWLn=1, VBLn=a0 and VSLn=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in Rn of the 1T1R array D2.


(S2-3) Reading s0* from R0b of the 1T1R array D1, and reading s1* from R1b of the 1T1R array D1; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜n−1=0, VBL0=s0*, VBL1=s1*, VBL2˜n−1=0, VSL0=s0*, VSL1=s1* and VSL2˜n−1=0 to calculate s0=a0⊕b0⊕c0 and s1=a1⊕b1⊕c1, and store s0 in R0 of the 1T1R array D3 and s1 in R1 of the 1T1R array D3.


(S2-4) Denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2.


(S2-5) Inputting logic signals VWLn=1, VBLn=ai−1 and VSLn=bi−1 to calculate ci=ai−1·bi−1+ai−1·ci−1+ci−1·bi−1 and store ci in Rn of the 1T1R array D2.


(S2-6) Reading si* from Rib of the 1T1R array D1; inputting logic signals VWL0˜(i−1)=0, VWL2=ci, VWL(i+1)˜(n−1)=0, VBL0˜(i−1)=0, VBL2=s1*, VBL(i+1)˜(n−1)=0, VSL0˜(i−1)=0, VSL2=si* and VSL(i+1)˜(n−1)=0 to calculate si=ai⊕bi⊕ci and store si in Ri of the 1T1R array D3.


(S2-7) Incrementing the value of i by 1, and if i<n−1, proceeding to the step (S2-5); otherwise, proceeding to step (S2-8).


(S2-8) Inputting logic signals VWLn=1, VBLn=an−2 and VSLn=bn−2 to calculate cn−1=an−2·bn−2+an−2·cn−2+cn−2·bn−2 and store cn−1 in Rn of the 1T1R array D2.


(S2-9) Reading s(n−1)* from R(n−1)b of the 1T1R array D1; inputting logic signals VWL0˜(n−2)=0, VWL(n−1)=cn−1, VBL0˜(n−2)=0, VBL(n−1)=sn−1*, VSL0˜(n−2)=0 and VSL(n−1)=sn−1* to calculate sn−1=an−1⊕bn−1⊕cn−1 and store sn−1 in Rn−1 of the 1T1R array D3.


(S2-10) inputting logic signals VWLn=1, VBLn=an−1 and VSLn=bn−1 to calculate cn=an−1·bn−1+an−1·cn−1+cn−1·bn−1 and store cn in Rn of the 1T1R array D2.


According to a fourth aspect of the present invention, there is provided an operation circuit based on the computing array for implementing an optimized multi-bit step-by-step carry adder, in which sums s0˜n−1 and carry information cn are calculated according to input data a0˜n−1 and b0˜n−1 and carry information c0, and n represents the number of bits of the operation data; the operation circuit comprises: a 1T1R array E1, a 1T1R array E2 and a 1T1R array E3; the 1T1R array E1 includes n 1T1R devices R0b˜R(n−1)b for calculating and storing data s0˜n−1*, word line control signals corresponding to R0b˜R(n−1)b are respectively VWL0b˜VWL(n−1)b, bit line control signals corresponding to R0b˜R(n−1)b are respectively VBL0b˜VBL(n−1)b, and source line control signals corresponding to R0b˜R(n−1)b are respectively VSL0b˜VSL(n−1)b; the 1T1R array E1 is used for data backup; the 1T1R array E2 includes (n+1) 1T1R devices R0c˜Rnc for calculating and storing carry data ci (i is an integer from 0 to n), word line control signals corresponding to R0c˜Rnc are respectively VWL0c˜VWLnc, bit line control signals corresponding to R0c˜Rnc are respectively VBL0c˜VBLnc, and source line control signals corresponding to R0c˜Rnc are respectively VSL0c˜VSLnc; the 1T1R array E3 includes n 1T1R devices R0˜Rn−1 for calculating and storing addition operation results s0˜n−1, word line control signals corresponding to R0˜Rn−1 are respectively VWL0˜VWL(n−1), bit line control signals corresponding to R0˜Rn−1 are respectively VBL0˜VBL(n−1), and source line control signals corresponding to R0˜Rn−1 are respectively VSL0˜VSL(n−1); and the intermediate data s0˜n−1* calculated by the 1T1R array E1 and the carry information ci calculated by the 1T1R array E2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array E3 through the data transmission circuit.


In conjunction with the fourth aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:


(S3-1) Inputting logic signals VWL0˜(n−1)=1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to write the input operational data a0˜n−1 into R0˜n−1 of the 1T1R array E3; inputting logic signals VWL0b˜(n−1)b=1, VBL0b˜(n−1)b=a0˜n−1 and VSL0b˜(n−1)b=a0˜n−1 to write the input operational data a0˜n−1 into R0b˜(n−1)b of the 1T1R array E1; inputting logic signals VWL0c˜nc=1, VBL0c˜nc=c0 and VSL0c˜nc=c0 to write the carry information c0 into R0c˜nc of the 1T1R array E2.


(S3-2) Inputting logic signals VWL0˜(n−1)=b0˜n−1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to calculate intermediate results s0˜n−1*=a0˜n−1⊕b0˜n−1 and store s0˜n−1* in R0˜n−1 of the 1T1R array E3; inputting logic signals VWL0b˜(n−1)b=b0˜n−1, VBL0b˜(n−1)b=a0˜n−1 and VSL0b˜(n−1)b=an to calculate intermediate results s0˜n−1* and store sn˜n−1* in R0b˜(n−1)b of the 1T1R array E1; inputting logic signals VWL0c=0, VWL1c˜nc=1, VBL0c˜nc=a0 and VSL0c˜8c=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜nc of the 1T1R array E2.


(S3-3) Reading s0* from R0b of the 1T1R array E1, and reading s1* from R1b of the 1T1R array E1; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜(n−1)=0, VBL0=s0*, VBL1=s1*, VBL2˜(n−1)=0, VSL0=s0*, VSL1=s1* and VSL2˜(n−1)=0 to calculate s0=a0⊕b0⊕c0 and s1=a1⊕b1⊕c1, and store s0 in R0 of the 1T1R array E3 and s1 in R1 of the 1T1R array E3; inputting logic signals VWL0c˜1c=0, VWL2˜nc=1, VBL0˜nc=a1 and VSL0c˜nc=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R2c˜nc of the 1T1R array E2.


(S3-4) Denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2.


(S3-5) Reading si* from Rib of the 1T1R array E1; inputting logic signals VWL0˜(i−1)=0, VWLi=ci, VWL(i+1)˜(n−1)=0, VBL0˜(i−1)=0, VBLi=si*, VBL(i+1)˜(n−1)=0, VSL0˜(i−1)=0, VSLi=si* and VSL(i+1)˜(n−1)=0 to calculate si=ai⊕bi⊕ci, and store si in Ri of the 1T1R array E3; inputting logic signals VWL0c˜ic=0, VWL(i+1)c˜nc=1, VBL0c˜nc=ai and VSL0c˜nc=bi to calculate ci+i=ai·bi+ai·ci+ci·bi and store ci+1 in R(i+1)c˜nc of the 1T1R array E2.


(S3-6) Incrementing the value of i by 1, and if i<n−1, proceeding to the step (S3-5); otherwise, proceeding to a step (S3-7).


(3-7) Reading sn−1* from R(n−1)b the 1T1R array E1; inputting logic signals VWL0˜(n−2)=0, VWL(n−1)=cn−1, VBL0˜(n−2)=0, VBL(n−1)=sn−1*, VSL0˜(n−2)=0 and VSL(n−1)=sn−1* to calculate sn−1=an−1⊕bn−1⊕cn−1 and store sn−1 in Rn−1 of the 1T1R array E3; and inputting logic signals VWL0c˜(n−1)c=0, VWLnc=1, YBL0c˜nc=an−1 and VSL0c˜nc=bn−i to calculate cn=an−1·bn−1+an−1·cn−1+cn−1·bn−1 and store cn in Rnc of the 1T1R array E2.


According to a fifth aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a 2-bit data selector, in which a logic signal a, a logic signal b and a control signal Sel are input to output the logic signal a or the logic signal b by controlling a value of the control signal Sel; the operation circuit comprises: a 1T1R array F, wherein the 1T1R array F includes one 1T1R device R, a word line signal corresponding to R is VWL, a bit line signal corresponding to R is VBL, and a source line signal corresponding to R is VSL.


In conjunction with the fifth aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:


(S4-1) Inputting logic signals VWL=1, VBL=a and VSL=ā to initialize the 1T1R device R, and write the input logic signal an into R of the 1T1R array F.


(S4-2) Inputting logic signals VWL=Sel, VBL=b and VSL=b to input the logic signal b and the control signal Sel so as to select an output logic signal out,


wherein the logic signal a and the logic signal b represent only two independent logic signals; when the control signal Sel=0, the output signal out=a; and when the control signal Sel=1, the output signal out=b.


According to a sixth aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a multi-bit carry select adder, in which sums s0˜n−1 and carry information cn are calculated according to input data a0˜n−1 and b0˜n−1 and carry information c0, n represents the number of bits of the operation data, and in the calculation process, according to the carry information of each bit, an XNOR operation result or an XOR operation result of the corresponding bit of the operation data is selected as bit information of the sum; the operation circuit comprises: a 1T1R array G1, a 1T1R array G2 and a 1T1R array G3; the 1T1R array G1 includes n 1T1R devices R0x˜R(n−1)x for calculating and storing XNOR operation results of data a0˜n−1 and b0˜n−1 (X0˜n−1=a0˜n−1 XNOR b0˜n−1), word line control signals corresponding to R0x˜R(n−1)x are respectively VWL0x˜VWL(n−1)x, bit line control signals corresponding to R0x˜R(n−1)x are respectively VBL0x˜VBL(n−1)x, and source line control signals corresponding to R0x˜R(n−1)x are respectively VSL0x˜VSL(n−1)x; the 1T1R array G2 includes (n+1) 1T1R devices R0c˜Rnc for calculating carry data ci (i is an integer from 0 to n), word line control signals corresponding to R0c˜Rnc are respectively VWL0x˜VWLnc, bit line control signals corresponding to R0c˜Rnc are respectively VBL0c˜VBLnc, and source line control signals corresponding to R0c˜Rnc are respectively VSL0c˜VSLnc; the 1T1R array G3 includes n 1T1R devices R0˜Rn−1 for calculating and storing addition operation results s0˜n−1, word line control signals corresponding to R0˜Rn−1 are respectively VWL0˜VWL(n−1), bit line control signals corresponding to R0˜Rn−1 are respectively VBL0-VBL(n−1), and source line control signals corresponding to R0˜Rn−1 are respectively VSL0-VSL(n−1); and the XNOR operation results X0˜n−1 calculated by the 1T1R array G1 and the carry information ci calculated by the 1T1R array G2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array G3 through the data transmission circuit.


In conjunction with the sixth aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:


(S5-1) Inputting logic signals VWL0x˜(n−1)x=1, VBL0x˜(n−1)x=b0˜n−1 and VSL0x˜7x=b0˜n−1 to store the result b0˜n−1 of inverting the input operation data b0˜n−1 in R0x˜(n−1)x of the 1T1R array G1; inputting logic signals VWL0c˜nc=1, VBL0c˜nc=c0 and VSL0c˜nc=c0 to store c0 in R0c˜nc of the 1T1R array G2; inputting logic signals VWL0c˜(n−1)=1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1, to store the input operational data a0˜n−1 in R0˜n−1 of the 1T1R array G3.


(S5-2) Inputting logic signals VWL0x˜(n−1)x=a0˜n−1, VBL0x˜(n−1)x=b0˜n−1 and VSL0x˜(n−1)x=b0˜n−1 to calculate XNOR operation results of the calculated data a0˜n−1 and b0˜n−1 (X0˜n−1=a0˜n−1 XNOR b0˜n−1) and store X0˜n−1 in R0x˜(n−1)x of the 1T1R array G1; inputting logic signals VWL0c=0, VWL1c˜nc=1, VBL0c˜nc=a0 and VSL0c˜nc=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜nc of the 1T1R array G2; inputting logic signals VWL0x˜(n−1)=b0˜n−1, VBL0x˜(n−1)=a0˜n−1 and VSL0x˜(n−1)=a0˜n−1, to calculate XOR operation results s0˜n−1*=a0˜n−1⊕b0˜n−1 and store s0˜n−1* in R0˜n−1 of the 1T1R array G3.


(S5-3) Inputting logic signals VWL0c˜1c=0, VWL2c˜nc=1, VBL0c˜nc=a1 and VSL0c˜nc=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R2c˜nc of the 1T1R array G2; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜(n−1)=0, VBL0˜(n−1)=X0˜n−1 and VSL0˜(n−1)=X0˜n−1 to calculate s0 and s1, and store s0 in R0 of the 1T1R array G3 and s1 in R1 of the 1T1R array G3; when c0=0, s0=a0⊕b0, and when c1=0, s0=a0⊕b0; when c1=0, s1=a1⊕b1, and when c1=1, s1=a1⊕b1.


(S5-4) Denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2.


(S5-5) Inputting logic signals VWL0c˜ic=0, VWL(i+1)c˜nc=1, VBL0c˜nc=ai and VSL0c˜nc=bi to calculate ci+1=ai·bi+ai·ci+ci·bi and store ci+1 in R(i+1)c˜nc of the 1T1R array G2; inputting logic signals VWL0x˜(i−1)=0, VWLi=ci, VWL(i+1)˜(n−1)=0, VBL0˜(n−1)=X0˜n−1 and VSL0˜(n−1)=X0˜n−1 to calculate si and store si in Ri of the 1T1R array G3; when ci=0, si=ai⊕bi, and when ci=1, si=ai⊕bi.


(S5-6) Incrementing the value of i by 1, and if i<n−1, proceeding to the step (S5-5); otherwise, proceeding to a step (S5-7).


(S5-7) Inputting logic signals VWL0c˜(n−1)c=0, VWLnc=1, VBL0c˜nc=an−1 and VSL0c˜nc=bn−1 to calculate cn=an−1·bn−1+an−1·cn−1+cn−1·bn−1 and store cn in Rnc of the 1T1R array G2; inputting logic signals VWL0˜(n−2)=0, VWL(n−1)=cn−1, VBL0˜(n−1)=X0˜n−1 and VSL0˜(n−1)=X0˜n−1 to calculate sn−1 and store sn−1 in Rn−1 of the 1T1R array G3; when nn−1=0, sn−1=an−1⊕bn−1, and when cn−1=1, s7=an−1⊕bn−1.


According to a seventh aspect of the present invention, there is provided an operation circuit based on the computing array for implementing a multi-bit pre-calculation adder, in which sums s0˜n−1 and carry information cn are calculated according to input data a0˜n−1 and b˜n−1 and carry information c0, and n represents the number of bits of the operation data; the operation circuit comprises: a 1T1R array H1 and a 1T1R array Hz; the 1T1R array H1 includes (n+1) 1T1R devices R0c˜Rnc for calculating carry data ci (i is an integer from 0 to n), word line control signals corresponding to R0c˜Rnc are respectively VWL0c˜VWLnc, bit line control signals corresponding to R0c˜Rnc are respectively VBL0c˜VBLnc, and source line control signals corresponding to R0c˜Rnc are respectively VSL0c˜VSLnc; the 1T1R array H2 includes n 1T1R devices R0˜Rn−1 for calculating and storing addition operation results s0˜n−1, word line control signals corresponding to R0˜Rn−1 are respectively VWL0˜VWL(n−1), bit line control signals corresponding to R0˜Rn−1 are respectively VBL0˜VBL(n−1), and source line control signals corresponding to R0˜Rn−1 are respectively VSL0˜VSL(n−1); and the carry information ci calculated by the 1T1R array H1 is converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array H2 through the data transmission circuit.


In conjunction with the seventh aspect of the present invention, the present invention further provides an operating method based on the operation circuit, which comprises:


(S6-1) Inputting logic signals VWL0c˜nc=1, VBL0c˜nc=c0 and VSL0c˜nc=c0 to store c0 in R0c˜nc of the 1T1R array H1; inputting logic signals VWL0˜(n−1)=1, VBL0˜(n−1)=c0 and VSL0˜(n−1)=c0 to store the input carry information c0 in R0˜n−1 of the 1T1R array H2.


(S6-2) Inputting logic signals VWL0c=0, VWL1c˜nc=1, VBL0c˜nc=a0 and VSL0c˜nc=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜nc of the 1T1R array H1; inputting logic signals VWL0˜(n−1)=1, VBL0˜(n−1)=a0, VSL0=b0 and VSL1˜(n−1)=b0 to calculate s0′=c0·a0+c0·a0·b0+c0·a0·b0 and c1=a0·b0+a0·c0+c0·b0, and store s0′ in R0 of the 1T1R array H2 and c1 in R1˜n−1 of the 1T1R array H2.


(S6-3) Inputting logic signals VWL0c˜1c=0, VWL2c˜nc=1, VBL0c˜nc=a1 and VSL0c˜nc=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R2c˜ne of the 1T1R array H1; inputting logic signals VWL0˜(n−1)=1, VBL0=b0, VBL1˜(n−1)=a1, VSL0=c1, VSL1=b1 and VSL2˜(n−1)=b1 to calculate s0=a0⊕b0⊕c0, s1′=c1·a1+c1·a1+b1+c1·a1·b1 and c2=a1·b1+a1·c1+c1·b1, and store s0 in R0 of the 1T1R array H2, s1′ in R1 of the 1T1R array H2 and c2 in R2˜R7 of the 1T1R array H2.


(S6-4) Denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=1.


(S6-5) Inputting logic signals VWL0c˜(i+2)c=0, VWL(i+2)c˜nc=1, VBL0c˜nc=ai+1 and VSL0c˜nc=bi+1 to calculate ci+2=ai+1·bi+1+ai+1·ci+1+ci+1·bi+1 and store ci+2 in R(i+2)c˜nc of the 1T1R array H1; inputting logic signals VWL0˜(i−1)=0, VWLi˜(n−1)=1, VBL0˜(i−1)=0, VBLi=bi, VBL2˜7=ai+1, VSL0˜(i˜1)=0, VSLi=ci+1, VSL(i+1)=b(i+1) and VSL(i+2)˜(n−1)=bi+1 to calculate si=ai⊕bi⊕ci, si+1′=ci+1·ai+1+ci+1·ai+1·bi+1+ci+1·ai+1·bi+1, and ci+2=ai+1·bi+1+ai+1·ci+1+ci+1·bi+1 and store si in Ri of the 1T1R array H2, si+1′ in Ri+1 of the 1T1R array H2 and ci+2 in R(i+2)˜(n−1) of the 1T1R array H2.


(S6-6) Incrementing the value of i by 1, and if i<n−1, proceeding to the step (S6-5); otherwise, proceeding to a step (S6-7).


(S6-7) Inputting logic signals VWL0˜(n−1)c=0, VWLnc=1, VBL0c˜nc=an−1 and VSL0c˜nc=bn−1 to calculate cn=an−1·bn−1+an−1·cn−1+cn−1·bn−1 and store cn in Rnc of the 1T1R array H1; inputting logic signals VWL0˜(n−3)=0, VWL(n−2)˜(n−1)=1, VBL0˜(n−3)=0, VBL(n−2)=bn−2, VBL(n−1)=an−1, VSL0˜(n−3)=0, VSL(n−2)=cn−1 and VSL7=bn−1 to calculate sn−2=an−2⊕bn−2⊕cn−2 and sn−1′=cn−1·an−1+cn−1·an−1·bn−1+cn−1·an−1·bn−1, and store sn−2 in Rn−2 of the 1T1R array H2 and sn−1′ in Rn−1 of the 1T1R array H2.


(S6-8) Inputting logic signals VWL0˜(n−2)=0, VWL(n−1)=1, VBL0˜(n−2)=0, VBL(n−1)=bn−1, VSL0˜(n−2)=0 and VSL(n−1)=cn to calculate sn−1=an−1⊕bn−1⊕cn−1 and store sn−1 in Rn−1 of the 1T1R array H2.


In general, with the above technical solution conceived by the present invention, a computing array based on 1T1R device is provided, and based on the computing array according to the present invention, multiple operation circuits are provided, which can achieve the following beneficial effects.


(1) The operation circuits are based on the computing array based on 1T1R device, and can directly store the calculated result in the 1T1R devices of the computing array while performing the logic operation, thereby achieving the fusion of computing and storage.


(2) The operation circuits according to the present invention can complete all logical operations in two steps when implementing 16 kinds of Boolean logic operations, greatly simplifying the design of the logic circuit and reducing the complexity of the integration process.


(3) By setting a different number of 1T1R arrays in the computing array and a different number of 1T1R devices in the 1T1R array in combination with the corresponding operating methods, in addition to 16 basic Boolean logic operations, complex operations such as a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder can be realized.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a schematic diagram of a computing array based on 1T1R device according to an embodiment of the present invention.



FIG. 2 is a schematic diagram of a 1T1R array in the computing array according to the embodiment of the present invention.



FIG. 3 is a schematic diagram of a three-dimensional structure and an equivalent circuit diagram of the 1T1R device according to the embodiment of the present invention, in which (a) is a schematic diagram of a three-dimensional structure of the 1T1R device; and (b) is an equivalent circuit diagram of a 1T1R device.



FIG. 4 is a block diagram and an equivalent circuit diagram of an operation circuit of a 1-bit full adder based on the computing array according to an embodiment of the present invention, in which (a) is a block diagram of the operation circuit of the 1-bit full adder; and (b) is an equivalent circuit diagram of the operation circuit of the 1-bit full adder.



FIG. 5 is an equivalent circuit diagram of an operation circuit of an 8-bit step-by-step carry adder based on the computing array according to an embodiment of the present invention.



FIG. 6 is an equivalent circuit diagram of an operation circuit of an optimized 8-bit step-by-step carry adder based on the computing array according to an embodiment of the present invention.



FIG. 7 is a block diagram and an equivalent circuit diagram of an operation circuit of a 2-bit data selector based on the computing array according to an embodiment of the present invention, in which (a) is a block diagram of the operation circuit of the 2-bit data selector; and (b) is an equivalent circuit diagram of the operation circuit of the 2-bit data selector.



FIG. 8 is an equivalent circuit diagram of an operation circuit of an 8-bit carry select adder based on the computing array according to an embodiment of the present invention.



FIG. 9 is an equivalent circuit diagram of an operation circuit of an 8-bit pre-calculation adder based on the computing array according to an embodiment of the present invention.





In all figures, the same elements or structures are denoted by the same reference numerals, in which:



100: source line decoder, 101: word line decoder, 102: bit line decoder, 103: signal amplifier, 104: state controller, 105: control signal modem, 106: data transmission circuit, 300: bit Line, 301: upper electrode of RRAM, 302: functional layer of RRAM, 303: lower electrode of RRAM, 304: source line, 305: gate of transistor, 306: insulating layer of transistor, 307: source of transistor, 308: drain of transistor, and 309: substrate of transistor.


DETAILED DESCRIPTION OF THE EMBODIMENTS

For clear understanding of the objectives, features and advantages of the present invention, detailed description of the present invention will be given below in conjunction with accompanying drawings and specific embodiments. It should be noted that the embodiments described herein are only meant to explain the present invention, and not to limit the scope of the present invention. Furthermore, the technical features related to the embodiments of the invention described below can be mutually combined if they are not found to be mutually exclusive.


A computing array based on 1T1R device according to the present invention, as shown in FIG. 1, includes: one or more 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R array.


The 1T1R array, as shown in FIG. 2, includes 1T1R devices arranged in an array, word lines WL, bit lines BL and source lines SL; the 1T1R devices realize storage and processing of information through different resistance states; the 1T1R devices in the same row are connected to the same bit line, and the 1T1R devices in the same column are connected to the same bit line and word line; and through applying different signals to the word lines WL, bit lines BL and source lines SL, different operations are achieved and operation results are stored.


The 1T1R device, as shown in FIG. 3, includes a transistor and a resistive element. The transistor includes a substrate 309, a source 307, a drain 308, an insulating layer 306 and a gate 305. In this embodiment, the resistive element is a resistive random access memory (RRAM), which includes: an upper electrode 301, a functional layer 302 and a lower electrode 303. The source 307 of the transistor is connected to the bit line 300, the gate 305 of the transistor is connected to the word line, the upper electrode 301 of RRAM is connected to the bit line 300, and the lower electrode 303 of RRAM is connected to the drain 308 of the transistor.


The resistance states of the 1T1R devices include: High Resistance H and Low Resistance L. The resistance state of the 1T1R device can be reversibly transformed under the stimulation of an applied signal, namely, with the stimulation of an applied signal, the resistance state of the 1T1R device can be transformed from High Resistance to Low Resistance, and with the stimulation of another applied signal, the resistance state of the 1T1R device can be transformed from Low Resistance to High Resistance. By using the two resistance states of the 1T1R device, storage and processing of information can be achieved.


As shown in FIG. 1, the peripheral circuit includes a state controller 104, a word line decoder 101, a source line decoder 100, a bit line decoder 102, a signal amplifier 103, a control signal modem 105 and a data transmission circuit 106, in which:


The state controller 104 has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result.


An input terminal of the word line decoder 101 is connected to the word line output terminal of the state controller 104, an output terminal of the word line decoder 101 is connected to the word line of the 1T1R array; the word line decoder 101 decodes the control signal generated by the state controller 104 to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array.


An input terminal of the bit line decoder 102 is connected to the bit line output terminal of the state controller 104, an output terminal of the bit line decoder 102 is connected to the bit line of the 1T1R array; the bit line decoder 102 decodes the control signal generated by the state controller 104 to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array.


An input terminal of the source line decoder 100 is connected to the source line output terminal of the state controller 104, an output terminal of the source line decoder 100 is connected to the source line of the 1T1R array; the source line decoder 100 decodes the control signal generated by the state controller 104 to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array.


The word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array.


An input terminal of the signal amplifier 103 is connected to the bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier 103 converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem 105.


A first input terminal of the control signal modem 105 is connected to the secondary output terminal of the state controller 104, a second input terminal of the control signal modem 105 is connected to an output terminal of the signal amplifier 103; the control signal modem 105 decodes the control signal generated by the state controller 104 to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier 103; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array.


An input terminal of the data transmission circuit 106 is connected to an output terminal of the control signal modem 105; the data transmission circuit 106 feeds back the data voltage signal output by the control signal modem 105 to the state controller 104 through the result input terminal of the state controller 104, or transmits the control signal output from the control signal modem 105 to a word line decoder, a bit line decoder and a source line decoder of the next-stage circuit.


The data input/output terminal Data, the address input terminal Address and the clock signal input terminal CLK of the state controller 104 respectively serve as a data input/output terminal, an address input terminal and a clock signal input terminal of the computing array.


In the computing array based on 1T1R device, applied voltage pulses are used as input signals to perform logic operation, and the result of the logic operation is characterized by the final resistance state of the 1T1R device; the result of the logic operation can be non-volatilely stored in the resistance state of the device, the resistance state can be read by a read signal of a small current (generally at the nanoampere level) or a small voltage (generally 0.2V or less), and the resistance signal can be erased by applying a voltage pulse with a certain amplitude and pulse width.


In the computing array based on 1T1R device, Boolean logic operations are achieved in the 1T1R devices by applying different voltage pulse signals to the word lines, source lines and bit lines of the 1T1R array. The initial resistance state of the 1T1R device is defined as a logic signal I, in which I=0 when the initial resistance state of the 1T1R device is High Resistance, and I=1 when the initial resistance state of the 1T1R device is Low Resistance; the word line level voltage is defined as a logic signal VWL, in which VWL=0 when a zero-level pulse is applied to the word line, and VWL=1 when a forward voltage pulse is applied to the word line; the bit line level voltage is defined as a logic signal VBL, in which VBL=0 when a zero-level pulse is applied to the bit line, and VBL=1 when a forward voltage pulse is applied to the bit line; the source line level voltage is defined as a logic signal VSL, in which VSL=0 when a zero-level pulse is applied to the source line, and VSL=1 when a forward voltage pulse is applied to the source line; the result of the logical operation in the 1T1R device is non-volatilely stored in the 1T1R device, and when information stored in the 1T1R device is read, the resistance state of the 1T1R device is defined as a logic signal R, in which R=0 when the resistance state of the 1T1R device is High Resistance, and R=1 when the resistance state of the 1T1R device is Low Resistance; and a logical relationship between the logic signal I, the logic signal VWL, the logic signal VBL, the logic signal VSL, and the logic signal R is:






R=I·VWL+I·VWL·VBL+I·VWL·VBL·VSL+Ī·VWL·VBL·VST


In the computing array based on 1T1R device, Boolean logic operation are implemented in a single 1T1R device, and specifically, the operating method includes the following steps.


(1) Initializing the 1T1R device to obtain a logic signal I.


(2) Respectively applying a voltage pulse signal to a word line, a source line and a bit line to obtain a logic signal VWL, a logic signal VSL and a logic signal VBL.


(3) Reading a result of the logical operation, that is, a logic signal R.


By controlling values of the logic signals I, VWL, VBL and VSL, the following 16 Boolean logic operations can be implemented:


implementation of logic 0: I=0, VWL=0, VBL=p and VSL=q;


implementation of logic 1: I=1, VWL=0, VBL=p and VSL=q;


implementation of p logic: I=p, VWL=0, VBL=0 and VSL=q;


implementation of p logic: I=q, VWL=0, VBL=0 and VSL=p;


implementation of p logic: I=p, VWL=0, VBL=p and VSL=q;


implementation of q logic: I=q, VWL=0, VBL=p and VSL=q;


implementation of p+q logic: I=p, VWL=1, VBL=p and VSL=0;


implementation of p+q logic: I=1, VWL=p, VBL=0 and VSL=q;


implementation of p·q logic: I=0, VWL=p, VBL=q and VSL=0;


implementation of p·q logic: I=q, VWL=p, VBL=q and VSL=1;


implementation of p+q logic: I=1, VWL=1, VBL=p and VSL=q;


implementation of p+q logic: I=1, VWL=p, VBL=q and VSL=1;


implementation of p·q logic: I=q, VWL=1, VBL=0 and VSL=p;


implementation of p·q logic: I=p, VWL=1, VBL=0 and VSL=q;


implementation of p·q+p·q logic: I=p, VWL=q, VBL=p and VSL=p; and


implementation of p·q+p·q logic: I=q, VWL=p, VBL=q and VSL=q.


Further, by inputting a logic signal VWL=1 via the word line, a logic signal VBL=Vread via the bit line and a logic signal VSL=0 via the source line, the logic signal stored on the 1T1R device can be read, in which Vread is a voltage pulse signal applied when the resistance state of the 1T1R device is read.


In the present invention, symbols similar to I, VWL, VBL and VSL are used to denote logical signals with the same concept, and signals corresponding to different 1T1R devices are distinguished only by different subscripts.



FIG. 4 shows an operation circuit based on the computing array according to the present invention for implementing a 1-bit full adder, in which a sum s0 and a high-order carry c1 are calculated according to a logic signal a, a logic signal b and a low-order carry c0 that are input; the operation circuit includes: a 1T1R array A1, a 1T1R array A2 and a 1T1R array A3; the 1T1R array A1 includes a 1T1R device Rb for calculating and storing intermediate data s0*, a word line signal corresponding to Rb is VWLb, a bit line signal corresponding to Rb is VBLb and a source line signal corresponding to Rb is VSLb; the 1T1R array A2 includes a 1T1R device Rc for calculating and storing the high-order carry c1, a word line signal corresponding to Rc is VWLc, a bit line signal corresponding to Rc is VBLc and a source line signal corresponding to Rc is VSLc; the 1T1R array A3 includes a 1T1R device Rs for calculating and storing the sum s0, a word line signal corresponding to Rs is VWLs, a bit line signal corresponding to Rs is VBLs and a source line signal corresponding to Rs is VSLs; and the intermediate data s0* calculated by the 1T1R array A1 and the high-order carry c1 calculated by the 1T1R array A2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array A3 through the data transmission circuit.


In conjunction with the operation circuit based on the computing array shown in FIG. 4, an operating method according to the present invention comprises the following steps.


(S1-1) Inputting logic signals VWLc=1, VBLc=c0 and VSLc=c0 to write the input logic signal c0 into Rc of the 1T1R array A2; inputting logic signals VWLb=1, VBLb=a0 and VSLb=a0, to write the input logic signal a0 into Rb of the 1T1R array A1; inputting logic signals VWLs=1, VBLs=a0 and VSLs=a0 to write the input logic signal a0 into Rs of the 1T1R array A3.


(S1-2) Inputting logic signals VWLc=1, VBLc=a0 and VSLc=b0 to calculate a high-order carry c1=a0·b0+a0·c0+c0·b0 and store c1 in Rc of the 1T1R array A2; inputting logic signals VWLb=b0, VBLb=a0 and VSLb=a0 to calculate an intermediate result s0*=a0⊕b0 and store s0* in Rb of the 1T1R array A1; inputting logic signals VWLs=b0, VBLs=a0 and VSLs=a0 to calculate an intermediate result s0* and store s0* in Rs of the 1T1R array A3.


(S1-3) reading the logic signal c1 stored in Rc of the 1T1R array A2; reading the logic signal s0* stored in Rb of the 1T1R array A1; inputting logic signals VWLs=c0, VBLs=s0* and VSLs=s0* to calculate a sum s0=a0⊕b0⊕c0 and store s0 in Rs of the 1T1R array A3.


(S1-4) reading the logic signal s0 stored in Rs of the 1T1R array A3.



FIG. 5 shows an operation circuit based on the computing array according to the present invention for implementing an 8-bit step-by-step carry adder, in which sums s0˜7 and carry information c8 are calculated according to input data a0˜7 and b0˜7 and carry information c0; the operation circuit includes: a 1T1R array D1, a 1T1R array D2 and a 1T1R array D3; the 1T1R array D1 includes eight 1T1R devices R0b˜R7b for calculating and storing intermediate results, word line control signals corresponding to R0b˜R7b are respectively VWL0b˜VWL7b, bit line control signals corresponding to R0b˜R7b are respectively VBL0b˜VBL7b, and source line control signals corresponding to R0b˜R7b are respectively VSL0b˜VSL7b; the 1T1R array D1 is used for data backup; the 1T1R array D2 includes a 1T1R device R8 for calculating and storing carry data ci (i is an integer from 0 to 8), a word line control signal corresponding to R8 is VWL8, a bit line control signal corresponding to R8 is VBL8 and a source line control signal corresponding to R8 is VSL8; the 1T1R array D3 includes eight 1T1R devices R0˜R7 for calculating and storing addition operation results s0˜7, word line control signals corresponding to R0˜R7 are respectively VWL0˜VWL7, bit line control signals corresponding to R0˜R7 are respectively VBL0˜VBL7, and source line control signals corresponding to R0˜R7 are respectively VSL0˜VSL7; and the intermediate data s0˜7* calculated by the 1T1R array D1 and the carry information c1 calculated by the 1T1R array D2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array D3 through the data transmission circuit.


In conjunction with the operation circuit based on the computing array shown in FIG. 5, an operating method according to the present invention comprises the following steps.


(S2-1) Inputting logic signals VWL0˜7=1, VBL0˜7=a0˜7 and VSL0˜7=a0˜7 to write the input data a0˜7 into R0˜R7 of the 1T1R array D3; inputting logic signals VWL8=1, VBL8=c0 and VSL8=c0 to write the lower-order carry c0 into R8 of the 1T1R array D2.


(S2-2) inputting logic signals VWL0˜7=b0˜7, VBL0˜7=a0˜7 and VSL0˜7=a0˜7 to calculate intermediate results s0˜7*=a0˜7⊕b0˜7 and store s0˜7* in R0˜R7 of the 1T1R array D3; inputting logic signals VWL0b˜7b=b0˜7, VBL0b˜7b=a0˜7 and VSL0b˜7b=a0˜7 to calculate intermediate results s0˜7* and store s0˜7* in R0b˜R7b of the 1T1R array D1; inputting logic signals VWL8=1, VBL8=a0 and VSL8=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R8 of the 1T1R array D2.


(S2-3) Reading s0* from R0b of the 1T1R array D1, and reading s1* from Rib of the 1T1R array D1; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜7=0, VBL0=s0*, VBL1=s1*, VBL2˜7=0, VSL0=s0*, VSL1=s1* and VSL2˜7=0 to calculate s0=a0⊕b0⊕c0 and s1=a1⊕b1⊕c1, and store s0 in R0 of the 1T1R array D3 and s1 in R1 of the 1T1R array D3.


(S2-4) Inputting logic signals VWL8=1, VBL8=a1 and VSL8=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R8 of the 1T1R array D2.


(S2-5) Reading s2* from R2b of the 1T1R array D1; inputting logic signals VWL0˜1=0, VWL2=c2, VWL3˜7=0, VBL0˜1=0, VBL2=s2*, VBL3˜7=0, VSL0˜1=0, VSL2=s2* and VSL3˜7=0 to calculate s2=a2⊕b2⊕c2 and store s2 in R2 of the 1T1R array D3.


(S2-6) Inputting logic signals VWL8=1, VBL8=a2 and VSL8=b2 to calculate c3=a2·b2+a2·c2+c2·b2 and store c3 in R8 of the 1T1R array D2.


(S2-7) Reading s3* from R3b of the 1T1R array D1; inputting logic signals VWL0˜2=0, VWL3=c3, VWL4˜7=0, VBL0˜2=0, VBL3=s3*, VBL4˜7=0, VSL0˜2=0, VSL3=s3* and VSL4˜7=0 to calculate s3=a3⊕b3⊕c3 and store s3 in R3 of the 1T1R array D3.


(S2-8) inputting logic signals VWL8=1, VBL8=a3 and VSL8=b3 to calculate c4=a3·b3+a3·c3+c3·b3 and store c4 in R8 of the 1T1R array D2.


(S2-9) Reading s4* from R4b of the 1T1R array D1; inputting logic signals VWL0˜3=0, VWL4=c4, VWL5˜7=0, VBL0˜3=0, VBL4=s4*, VBL5˜7=0, VSL0˜3=0, VSL4=s4* and VSL5˜7=0 to calculate s4=a4⊕b4⊕c4 and store s4 in R4 of the 1T1R array D3.


(S2-10) Inputting logic signals VWL8=1, VBL8=a4 and VSL8=b4 to calculate c5=a4·b4+a4·c4+c4·b4 and store c5 in R8 of the 1T1R array D2.


(S2-11) Reading s5* from R5b of the 1T1R array D1; inputting logic signals VWL0˜4=0, VWL5=c5, VWL6˜7=0, VBL0˜4=0, VBL5˜s5*, VBL6˜7=0, VSL0˜4=0, VSL5=s5* and VSL6˜7=0 to calculate s5=a5⊕b5⊕c5 and store s5 in R5 of the 1T1R array D3.


(S2-12) Inputting logic signals VWL8=1, VBL8=a5 and VSL8=b5 to calculate c6=a5·b5+a5·c5+c5·b5 and store c6 in R8 of the 1T1R array D2.


(S2-13) Reading s6* from R6b of the 1T1R array D1; inputting logic signals VWL0˜5=0, VWL6=c6, VWL7=0, VBL0˜5=0, VBL6=s6*, VBL7=0, VSL0˜5=0, VSL6=s6* and VSL7=0 to calculate s6=a6⊕b6⊕c6 and store s6 in R6 of the 1T1R array D3.


(S2-14) Inputting logic signals VWL8=1, VBL8=a6 and VSL8=b6 to calculate c7=a6·b6+a6·c6+c6·b6 and store c7 in R8 of the 1T1R array D2.


(S2-15) Reading s7* from R7b of the 1T1R array D1; inputting logic signals VWL0˜6=0, VWL7=c7, VBL0˜6=0, VBL7=s7*, VSL0˜6=0 and VSL7=s7* to calculate s7=a7⊕b7⊕c7 and store s7 in R7 of the 1T1R array D3.


(S2-16) Inputting logic signals VWL8=1, VBL8=a7 and VSL8=b7 to calculate c8=a7·b7+a7·c7+c7·b7 and store c8 in R8 of the 1T1R array D2.



FIG. 6 shows an operation circuit based on the computing array according to the present invention for implementing an optimized 8-bit step-by-step carry adder, in which sums s0˜7 and carry information c8 are calculated according to input data a0˜7 and b0˜7 and carry information c0; the operation circuit includes: a 1T1R array E1, a 1T1R array E2 and a 1T1R array E3; the 1T1R array E1 includes eight 1T1R devices R0b˜R7b for calculating and storing data s0˜7*, word line control signals corresponding to R0b˜R7b are respectively VWL0b˜VWL7b, bit line control signals corresponding to R0b˜R7b are respectively VBL0b˜VBL7b, and source line control signals corresponding to R0b˜R7b are respectively VSL0b˜VSL7b; the 1T1R array E1 is used for data backup; the 1T1R array E2 includes nine 1T1R devices R0c˜R8c for calculating and storing carry data ci (i is an integer from 0 to 8), word line control signals corresponding to R0c˜R8c are respectively VWL0c˜VWL8c, bit line control signals corresponding to R0c˜R8c are respectively VBL0c˜VBL8c, and source line control signals corresponding to R0c˜R8c are respectively VSL0c˜VSL8c; the 1T1R array E3 includes eight 1T1R devices R0˜R7 for calculating and storing addition operation results s0˜7; and the intermediate data s0˜7* calculated by the 1T1R array E1 and the carry information ci calculated by the 1T1R array E2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array E3 through the data transmission circuit.


In conjunction with the operation circuit based on the computing array shown in FIG. 6, an operating method according to the present invention comprises the following steps.


(S3-1) inputting logic signals VWL0˜7=1, VBL0˜7=a0˜7 and VSL0˜7=a0˜7 to write the input operational data a0˜7 into R0˜R7 of the 1T1R array E3; inputting logic signals VWL0b˜7b=1, VBL0b˜7b=a0˜7 and VSL0b˜7b=a0˜7 to write the input operational data a0˜7 into R0b˜R7b of the 1T1R array E1; inputting logic signals VWL0c˜8c=1, VBL0c˜8=c0 and VSL0c˜8c=c0 to write the carry information c0 into R0c˜R8c of the 1T1R array E2.


(S3-2) Inputting logic signals VWL0˜7=b0˜7, VBL0˜7=a0˜7 and VSL0˜7=a0˜7 to calculate intermediate results s0˜7*=a0˜7⊕b0˜7 and store s0˜7* in R0˜R7 of the 1T1R array E3; inputting logic signals VWL0b˜7b=b0˜7, VBL0b˜7b=a0˜7 and VSL0b˜7b=a0˜7 to calculate intermediate results s0˜7* and store s0˜7* in R0b˜R7b of the 1T1R array E1; inputting logic signals VWL0c=0, VWL1c˜8c=1, VBL0c˜8c=a0 and VSL0c˜8c=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜8c of the 1T1R array E2.


(S3-3) Reading s0* from R0b of the 1T1R array E1, and reading s1* from R1b of the 1T1R array E1; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜7=0, VBL0=s0*, VBL1=s1*, VBL2˜7=0, VSL0=s0*, VSL1=s1* and VSL2˜7=0 to calculate s0=a0⊕b0⊕c0 and s1=a1⊕b1⊕c1, and store s0 in R0 of the 1T1R array E3 and s1 in R1 of the 1T1R array E3; inputting logic signals VWL0˜1c=0, VWL2c˜8c=1, VBL0c˜8c=a1 and VSL0c˜8c=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R2c˜8c of the 1T1R array E2.


(S3-4) Reading s2* from R2b of the 1T1R array E1; inputting logic signals VWL0˜1=0, VWL2=c2, VWL3˜7=0, VBL0˜1=0, VBL2=s2*, VBL3˜7=0, VSL0˜1=0, VSL2=s2* and VSL3˜7=0 to calculate s2=a2⊕b2⊕c2, and store s2 in R2 of the 1T1R array E3; inputting logic signals VWL0˜2c=0, VWL3c˜8c=1, VBL0c˜8c=a2 and VSL0c˜8c=b2 to calculate c3=a2·b2+a2·c2+c2·b2 and store c3 in R3c˜8c of the 1T1R array E2.


(3-5) Reading s3* from R3b of the 1T1R array E1; inputting logic signals VWL0˜2=0, VWL3=c3, VWL4˜7=0, VBL0˜2=0, VBL3=s3*, VBL4˜7=0, VSL0˜2=0, VSL3=s3* and VSL4˜7=0 to calculate s3=a3⊕b3⊕c3 and store s3 in R3 of the 1T1R array D3; inputting logic signals VWL0c˜3c=0, VWL4c˜8c=1, VBL0c˜8c=a3 and VSL0c˜8c=b3 to calculate c4=a3·b3+a3·c3+c3·b3 and store c4 in R4c˜8c of the 1T1R array E2.


(3-6) Reading s4* from R4b of the 1T1R array E1; inputting logic signals VWL0˜3=0, VWL4=c4, VWL5˜7=0, VBL0˜3=0, VBL4=s4*, VBL5˜7=0, VSL0˜3=0, VSL4=s4* and VSL5˜7=0 to calculate s4=a4⊕b4⊕c4 and store s4 in R4 of the 1T1R array E3; inputting logic signals VWL0c˜4c=0, VWL5c˜8c=1, VBL0c˜8c=a4 and VSL0c˜8c=b4 to calculate c5=a4·b4+a4·c4+c4·b4 and store c5 in R5c˜8c of the 1T1R array E2.


(3-7) Reading s5* from R5b of the 1T1R array E1; inputting logic signals VWL0˜4=0, VWL5=c5, VWL6˜7=0, VBL0˜4=0, VBL5˜s5*, VBL6˜7=0, VSL0˜4=0, VSL5=s5* and VSL6˜7=0 to calculate s5=a5⊕b5⊕c5 and store s5 in R5 of the 1T1R array E3; inputting logic signals VWL0˜5c=1, VWL6c˜8c=1, VBL0c˜8c=a5 and VSL0c˜8c=b5 to calculate c6=a5·b5+a5·c5+c5·b5 and store c6 in R6c˜8c of the 1T1R array E2.


(3-8) Reading s6* from R6b of the 1T1R array E1; inputting logic signals VWL0˜5=0, VWL6=c6, VWL7=0, VBL0˜5=0, VBL6=s6*, VBL7=0, VSL0˜5=0, VSL6=s6* and VSL7=0 to calculate s6=a6⊕b6⊕c6 and store s6 in R6 of the 1T1R array E3; inputting logic signals VWL7c˜8c=1, VBL0c˜8c=a6 and VSL0c˜8c=b6 to calculate c7=a6·b6+a6·c6+c6·b6 and store c7 in R7c˜8c of the 1T1R array E2.


(3-9) Reading s7* from R7b of the 1T1R array E1; inputting logic signals VWL0˜6=0, VWL7=c7, VBL0˜6=0, VBL7=s7*, VSL0˜6=0 and VSL7=s5* to calculate s7=a7⊕b7⊕c7 and store s7 in R7 of the 1T1R array E3; and inputting logic signals VWL0˜7c=0, VWL8c=1, VBL0c˜8c=a7 and VSL0c˜8c=b7 to calculate c8=a7·b7+a7·c7+c7·b7 and store c8 in R8c of the 1T1R array E2.



FIG. 7 shows an operation circuit based on the computing array according to the present invention for implementing a 2-bit data selector, in which a logic signal a, a logic signal b and a control signal Sel are input to output the logic signal a or the logic signal b by controlling a value of the control signal Sel; and the operation circuit includes a 1T1R array F, and the 1T1R array F includes one 1T1R device R.


In conjunction with the operation circuit based on the computing array shown in FIG. 7, an operating method according to the present invention comprises the following steps.


(S4-1) Inputting logic signals VWL=1, VBL=a and VSL=ā to initialize the 1T1R device R, and write the input logic signal a into R of the 1T1R array F.


(S4-2) inputting logic signals VWL=Sel, VBL=b and VSL=b to input the logic signal b and the control signal Sel so as to select an output logic signal out,


wherein the logic signal a and the logic signal b represent only two independent logic signals; when the control signal Sel=0, the output signal out=a; and when the control signal Sel=1, the output signal out=b.



FIG. 8 shows an operation circuit based on the computing array according to the present invention for implementing an 8-bit carry select adder, in which sums s0˜7 and carry information c8 are calculated according to input data a0˜7 and b0˜7 and carry information c0, and in the calculation process, according to the carry information of each bit, an XNOR operation result or an XOR operation result of the corresponding bit of the operation data is selected as bit information of the sum; the operation circuit includes a 1T1R array G1, a 1T1R array G2 and a 1T1R array G3; the 1T1R array G1 includes eight 1T1R devices R0x˜R7x for calculating and storing XNOR operation results of data a0˜7 and b0˜7 (X0˜7=a0˜7 XNOR b0˜7), word line control signals corresponding to R0x˜R7x are respectively VWL0x˜VWL7x, bit line control signals corresponding to R0x˜R7x are respectively VBL0x˜VBL7x, and source line control signals corresponding to R0x˜R7x are respectively VSL0x˜VSL7x; the 1T1R array G2 includes nine 1T1R devices R0c˜R8c for calculating carry data ci (i is an integer from 0 to 8), word line control signals corresponding to R0c˜R8c are respectively VWL0c˜VWL8c, bit line control signals corresponding to R0c˜R8c are respectively VBL0c˜VBL8c, and source line control signals corresponding to R0c˜R8c are respectively VSL0c˜VSL8c; the 1T1R array G3 includes eight 1T1R devices R0˜R7 for calculating and storing addition operation results s0˜7, word line control signals corresponding to R0˜R7 are respectively VWL0˜VWL7, bit line control signals corresponding to R0˜R7 are respectively VBL0˜VBL7, and source line control signals corresponding to R0˜R7 are respectively VSL0˜VSL7; and the XNOR operation results X0˜7 calculated by the 1T1R array G1 and the carry information ci calculated by the 1T1R array G2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array G3 through the data transmission circuit.


In conjunction with the operation circuit based on the computing array shown in FIG. 8, an operating method according to the present invention comprises the following steps.


(S5-1) Inputting logic signals VWL0x˜7x=1, VBL0x˜7x=b0˜7 and VSL0x˜7X=b0˜7 to store the result b0˜7 of inverting the input operation data b0˜n−1 in R0x˜R7x of the 1T1R array G1; inputting logic signals VWL0c˜8c=1, VBL0c˜8c=c0 and VSL0c˜8c=c0 to store c0 in R0c˜R8c, of the 1T1R array G2; inputting logic signals VWL0˜7=1, VBL0˜7=a0˜7 and VSL0˜7=a0˜7 to store the input operational data a0˜7 in R0˜R7 of the 1T1R array G3.


(S5-2) Inputting logic signals VWL0x˜7x=a0˜7; VBL0x˜7x=b0˜7 and VSL0x˜7x=b0˜7 to calculate XNOR operation results X0˜7=a0˜7 XNOR b0˜7 of the calculated data a0˜7 and a0˜7 and store X0˜7 in R0x˜R7x of the 1T1R array G1; inputting logic signals VWL1c˜8c=1, VBL1c˜8c=a0 and VSL0c˜8c=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜8c of the 1T1R array G2; inputting logic signals VWL0˜7=b0˜7, VBL0˜7=a0˜7 and VSL0˜7=a0˜7 to calculate XNOR operation results X0˜7 of the calculated data a0˜7 and b0˜7 and store X0˜7 in R0˜R7 of the 1T1R array G3.


(S5-3) Inputting logic signals VWL0c˜1c=0, VWL2c˜8c=1, VBL0c˜8c=a1 and VSL0c˜8c=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R2c˜8c of the 1T1R array G2; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜7=0, VBL0˜7=X0˜7 and VSL0˜7=X0˜7 to calculate s0 and s1 and store s0 in R0 of the 1T1R array G3 and s1 in R1 of the 1T1R array G3; when c0=0, s0=a0⊕b0, and when c1=0, s0=a0⊕b0; when c1=0, s1=a1⊕b1, and when c1=1, s1=a1⊕b1.


(S5-4) Inputting logic signals VWL0c˜2c=0, VWL3c˜8c=1, VBL0c˜8c=a2 and VSL0c˜8c=b2 to calculate c3=a2·b2+a2·c2+c2·b2 and store c3 in R3c˜8c of the 1T1R array G2; inputting logic signals VWL0˜1=0, VWL2=c2, VWL3˜7=0, VBL0˜7=X0˜7 and VSL0˜7=X0˜7 to calculate s2 and store s2 in R2 of the 1T1R array G3; when c2=0, s2=a2⊕b2, and when c2=1, s2=s2=a2⊕b2.


(S5-5) Inputting logic signals VWL0c˜3c=0, VWL4c˜8c=1, VBL0c˜8c=a3 and VSL0c˜8c=b3 to calculate c4=a3·b3+a3·c3+c3·b3 and store c4 in R4c˜8c of the 1T1R array G2; inputting logic signals VWL0˜2=0, VWL3=c3, VWL4˜7=0, VBL0˜7=X0˜7 and VSL0˜7=X0˜7 to calculate s3 and store s3 in R3 of the 1T1R array G3; when c3=0, s3=a3⊕b3, and when c3=1, s3=a3⊕b3.


(S5-6) Inputting logic signals VWL0c˜4c=0, VWL5c˜8c=1, VBL0c˜8c=a4 and VSL0c˜8c==b4 to calculate c5=a4·b4+a4·c4+c4·b4 and store c5 in R5c˜8c of the 1T1R array G2; inputting logic signals VWL0˜3=0, VWL3=c4, VWL5˜7=0, VBL0˜7=X0˜7 and VSL0˜7=X0˜7 to calculate s4 and store s4 in R4 of the 1T1R array G3; when c4=0, s4=a4⊕b4, and when c4=1, s4=a4⊕b4.


(S5-7) Inputting logic signals VWL0c˜5c=0, VWL6c˜8c=1, VBL0c˜8c=a5 and VSL0c˜8c==b5 to calculate c6=a5·b5+a5·c5+c5·b5 and store c6 in R6c˜8c of the 1T1R array G2; inputting logic signals VWL0˜4=0, VWL5=c5, VWL6˜7=0, VBL0˜7=X0˜7 and VSL0˜7=X0˜7 to calculate s5 and store s5 in R5 of the 1T1R array G3; when c5=0, s5=a5⊕b5, and when c5=1, s5=a5⊕b5.


(S5-8) Inputting logic signals VWL0c˜6c=0, VWL7c˜8c=1, VBL0c˜8c=a6 and VSL0c˜8c==b6 to calculate c7=a6·b6+a6·c6+c6·b6 and store c7 in R7c˜8c of the 1T1R array G2; inputting logic signals VWL0˜5=0, VWL6=c6, VWL7=0, VBL0˜7=X0˜7 and VSL0˜7=X0˜7 to calculate s6 and store s6 in R6 of the 1T1R array G3; when c6=0, s6=a6⊕b6, and when c5=1, s6=a6⊕b6.


(S5-9) Inputting logic signals VWL0c˜7c=0, VWL8c=1, VBL0c˜8c=a7 and VSL0c˜8c==b7 to calculate c8=a7·b7+a7·c7+c7·b7 and store c8 in R8c of the 1T1R array G2; inputting logic signals VWL0˜6=0, VWL7=c7, VBL0˜7=X0˜7 and VSL0˜7=X0˜7 to calculate s7 and store s7 in R7 of the 1T1R array G3; when c7=0, s7=a7⊕b7, and when c7=1, s7=a7⊕b7.



FIG. 9 shows an operation circuit based on the computing array according to the present invention for implementing an 8-bit pre-calculation adder, in which sums s0˜7 and carry information c8 are calculated according to input data a0˜7 and b0˜7 and carry information c0; the operation circuit includes a 1T1R array H1 and a 1T1R array Hz; the 1T1R array H1 includes nine 1T1R devices R0c˜R8c for calculating carry data ci (i is an integer from 0 to 8), word line control signals corresponding to R0c˜R8c are respectively VWL0c˜VWL8c, bit line control signals corresponding to R0c˜R8c are respectively VBL0c˜VBL8c, and source line control signals corresponding to R0c˜R8c are respectively VSL0c˜VSL8c; the 1T1R array H2 includes eight 1T1R devices R0˜R7 for calculating and storing addition operation results s0˜7, word line control signals corresponding to R0˜R7 are respectively VWL0˜VWL7, bit line control signals corresponding to R0˜R7 are respectively VBL0˜VBL7, and source line control signals corresponding to R0˜R7 are respectively VSL0˜VSL7; and the carry information c1 calculated by the 1T1R array H1 is converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array H2 through the data transmission circuit.


In conjunction with the operation circuit based on the computing array shown in FIG. 9, an operating method according to the present invention comprises the following steps.


(S6-1) Inputting logic signals VWL0c˜8c=1, VBL0c˜8c=c0 and VSL0c˜8c=c0 to store c0 in R0c˜R8c of the 1T1R array H1; inputting logic signals VWL0˜7=1, VBL0˜7=c0 and VSL0˜7=c0 to store the input carry information c0 in R0˜R7 of the 1T1R array H2.


(S6-2) Inputting logic signals VWL0c=0, VWL1c˜8c=1, VBL0c˜8c=a0 and VSL0c˜8c=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜8c of the 1T1R array H1; inputting logic signals VWL0˜7=1, VBL0˜7=a0, VSL0=b0 and VSL1˜7=b0 to calculate s0′=c0·a0+c0·a0·b0+c0·a0·b0 and c1=a0·b0+a0·c0+c0·b0 and store s0′ in R0 of the 1T1R array H2 and c1 in R1˜R7 of the 1T1R array H2.


(S6-3) Inputting logic signals VWL0c˜1c=0, VWL2c˜8c=1, VBL0c˜8c=a1 and VSL0c˜8c=b1 to calculate c2=a1˜b1+a1·c1+c1·b1 and store c2 in R2c˜8c of the 1T1R array H1; inputting logic signals VWL0˜7=1, VBL0=b0, VBL1˜7=a1, VSL0=c1, VSL1=b1 and VSL2˜7=b1 to calculate s0=a0⊕b0⊕c0, s1′=c1·a1+c1·a1·b1+c1·a1·b1 and c2 and store s0 in R0 of the 1T1R array H2, s1′ in R1 of the 1T1R array H2 and c1 in R2˜R7 of the 1T1R array H2.


(S6-4) Inputting logic signals VWL0c˜2c=0, VWL3c˜8c=1, VBL0c˜8c=a2 and VSL0c˜8c=b2 to calculate c3=a2·b2+a2·c2+c2·b2 and store c3 in R3c˜8c of the 1T1R array H1; inputting logic signals VWL0=0, VWL1˜7=1, VBL0=0, VBL1=b1, VBL2˜7=a2, VSL0=0, VSL0=c2, VSL2=b2 and VSL3˜7=b2 to calculate s1=a1⊕b1⊕c1, s2′=c2·a2+c2·a2·b2+c2·a2·b2 and c3=a2·b2+a2·c2+c2·b2 and store s1 in R1 of the 1T1R array H2, s2′ in R2 of the 1T1R array H2 and c2 in R3˜R7 of the 1T1R array H2.


(S6-5) Inputting logic signals VWL0c˜3c=0, VWL4c˜8c=1, VBL0c˜8c=a3 and VSL0c˜8c=b3 to calculate c4=a3·b3+a3·c3+c3·b3 and store c4 in R4c˜8c of the 1T1R array H1; inputting logic signals VWL0˜1=0, VWL2˜7=1, VBL0˜1=0, VBL2=b2, VBL3˜7=a3, VSL0˜1=0, VSL2=c3, VSL3=b3 and VSL4˜7=b3 to calculate s2=a2⊕b2⊕c2, s3′=c3·a3+c3·a3·b3+c3·a3·b3 and c4, and store s2 in R2 of the 1T1R array H2, s3′ in R3 of the 1T1R array H2 and c4 in R4˜R7 of the 1T1R array H2.


(S6-6) Inputting logic signals VWL0c˜4c=0, VWL5c˜8c=1, VBL0c˜8c=a4 and VSL0c˜8c=b4 to calculate c5=a4·b4+a4·c4+c4·b4 and store c5 in R5c˜8c of the 1T1R array H1; inputting logic signals VWL0˜2=0, VWL3˜7=1, VBL0˜2=0, VBL3=b3, VBL4˜7=a4, VSL0˜2=0, VSL3=c4, VSL4=b4 and VSL5˜7=b4 to calculate s3=a3⊕b3⊕c3, s4′=c4·a4+c4·a4·b4+c4·a4·b4 and c5, and store s3 in R3 of the 1T1R array H2, s4′ in R4 of the 1T1R array H2 and c5 in R5˜R7 of the 1T1R array H2.


(S6-7) Inputting logic signals VWL0c˜5c=0, VWL6c˜8c=1, VBL0c˜8c=a5 and VSL0c˜8c=b5 to calculate c6=a5·b5+a5·c5+c5·b5 and store c6 in R6c˜8c of the 1T1R array H1; inputting logic signals VWL0˜3=0, VWL4˜7=1, VBL0˜3=0, VBL4=b4, VBL5˜7=a5, VSL0˜3=0, VSL4=c5, VSL5=b5 and VSL6˜7=b5 to calculate s4=a4⊕b4⊕c4, s5′=c5·a5+c5·a5·b5+c5·a5·b5 and c6, and store s4 in R4 of the 1T1R array H2, s5′ in R5 of the 1T1R array H2 and c6 in R6˜R7 of the 1T1R array H2.


(S6-8) Inputting logic signals VWL0c˜6c=0, VWL7c˜8c=1, VBL0c˜8c=a6 and VSL0c˜8c=b6 to calculate c7=a6·b6+a6·c6+c6·b6 and store c7 in R7c˜8c of the 1T1R array H1; inputting logic signals VWL0˜4=0, VWL5˜7=1, VBL0˜4=0, VBL5=b5, VBL6˜7=a6, VSL0˜4=0, VSL5=c6, VSL6=b6 and VSL7=b6 to calculate s5=a5⊕b5⊕c5, s6′=c6·a6+c6·a6·b6+c6·a6·b6 and c7, and store s5 in R5 of the 1T1R array H2, s6′ in R6 of the 1T1R array H2 and c7 in R7 of the 1T1R array H2.


(S6-9) Inputting logic signals VWL0c˜7c=0, VWL8c=1, VBL0c˜8c=a7 and VSL0c˜8c=b7 to calculate c8=a7·b7+a7·c7+c7·b7 and store c8 in R8c of the 1T1R array H1; inputting logic signals VWL0˜5=0, VWL6˜7=1, VBL0˜5=0, VBL6=b6, VBL7=a7, VSL0˜5=0, VSL6=c7 and VSL7=b7 to calculate s6=a6⊕b6⊕c6 and s7′=c7·a7+c7·a7·b7+c7·a7·b7, and store s6 in R6 of the 1T1R array H2 and s7′ in R7 of the 1T1R array H2.


(S6-10) Inputting logic signals VWL0˜6=0, VWL7=1, VBL0˜6=0, VBL7=b7, VSL0˜6=0 and VSL7=c8, and inputting a logic signal of 0 to each of other terminals to calculate s7=a7⊕b7⊕c7 and store s7 in R7 of the 1T1R array H2.


It should be readily understood to those skilled in the art that the above description is only preferred embodiments of the present invention, and does not limit the scope of the present invention. Any change, equivalent substitution and modification made without departing from the spirit and scope of the present invention should be included within the scope of the protection of the present invention.

Claims
  • 1. A computing array based on 1T1R device, comprising: one or more 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays.
  • 2. The computing array based on 1T1R device according to claim 1, wherein the 1T1R array includes 1T1R devices arranged in an array, word lines WL, bit lines BL and source lines SL; resistance states of the 1T1R devices include: High Resistance H and Low Resistance L; the 1T1R devices realize storage and processing of information through different resistance states; and the 1T1R devices in the same row are connected to the same word line, the 1T1R devices in the same column are connected to the same bit line and source line, and through applying different signals to the word lines WL, the bit lines BL and the source lines SL, different operations are achieved and operation results are stored.
  • 3. The computing array based on 1T1R device according to claim 2, wherein the 1T1R device includes a transistor and a resistive element; the transistor includes a substrate, a source, a drain, an insulating layer and a gate, in which the source is connected to the source line SL, and the gate is connected to the word line WL; the resistive element includes two end electrodes, one of which is connected to the bit line BL and the other of which is connected to the drain of the transistor; and the resistive element has a stacked structure with a nonvolatile resistance transition characteristic.
  • 4. The computing array based on 1T1R device according to claim 1, wherein the peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit; the state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result;an input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to the word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array;an input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to the bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array;an input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to the source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array;the word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array;an input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem;a first input terminal of the control signal modem is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array;an input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit.
  • 5. The computing array based on 1T1R device according to claim 4, wherein the data input/output terminal Data, the address input terminal Address and the clock signal input terminal CLK of the state controller respectively serve as a data input/output terminal, an address input terminal and a clock signal input terminal of the computing array.
  • 6. The computing array based on 1T1R device according to claim 1, wherein 16 basic Boolean logic operations are implemented by controlling initial resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals; a logic signal stored in the 1T1R device is read by inputting a logic signal VWL=1 via a word line, a logic signal VBL=Vread via a bit line and a logic signal VSL=0 via a source line; Vread is a voltage pulse signal applied when a resistance state of the 1T1R device is read.
  • 7. An operation circuit based on the computing array according to claim 4 for implementing a 1-bit full adder, in which a sum s0 and a high-order carry c1 are calculated according to a logic signal a, a logic signal b and a low-order carry c0 that are input, comprising: a 1T1R array A1, a 1T1R array A2 and a 1T1R array A3; the 1T1R array A1 includes a 1T1R device Rb for calculating and storing intermediate data s0*, a word line signal corresponding to Rb is VWLb, a bit line signal corresponding to Rb is VBLb and a source line signal corresponding to Rb is VSLb; the 1T1R array A2 includes a 1T1R device Rc for calculating and storing the high-order carry c1, a word line signal corresponding to Rc is VWLc, a bit line signal corresponding to Rc is VBLc and a source line signal corresponding to Rc is VSLc; the 1T1R array A3 includes a 1T1R device Rs for calculating and storing the sum s0, a word line signal corresponding to Rs is VWLs, a bit line signal corresponding to Rs is VBLs and a source line signal corresponding to Rs is VSLs; and the intermediate data s0* calculated by the 1T1R array A1 and the high-order carry c1 calculated by the 1T1R array A2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array A3 through the data transmission circuit.
  • 8. An operating method based on the operation circuit according to claim 7, comprising: (S1-1) inputting logic signals VWLc=1, VBLc=c0 and VSLc=c0 to write the input logic signal c0 into Rc of the 1T1R array A2; inputting logic signals VWLb=1, VBLb=a0 and VSLb=a0 to write the input logic signal a0 into Rb of the 1T1R array A1; inputting logic signals VWLs=1, VBLs=a0 and VSLs=a0 to write the input logic signal a0 into Rs of the 1T1R array A3;(S1-2) inputting logic signals VWLc=1, VBLc=a0 and VSLc=b0 to calculate a high-order carry c1=a0·b0+a0·c0+c0·b0 and store c1 in Rc of the 1T1R array A2; inputting logic signals VWLb=b0, VBLb=a0 and VSLb=a0 to calculate an intermediate result s0*=a0⊕b0 and store s0* in Rb of the 1T1R array A1; inputting logic signals VWLs=b0, VBLs=a0 and VSLs=a0 to calculate an intermediate result s0* and store s0* in Rs of the 1T1R array A3;(S1-3) reading the logic signal c1 stored in Rc of the 1T1R array A2; reading the logic signal s0* stored in Rb of the 1T1R array A1; inputting logic signals VWLs=c0, VBLs=s0* and VSLs=s0*, to calculate a sum s0=a0⊕b0⊕c0 and store s0 in Rs of the 1T1R array A3; and(S1-4) reading the logic signal s0 stored in Rs of the 1T1R array A3.
  • 9. An operation circuit based on the computing array according to claim 4 for implementing a multi-bit step-by-step carry adder, in which sums s0˜n−1 and carry information cn are calculated according to input data a0˜n−1 and b0˜n−1 and carry information c0, and n represents the number of bits of the operation data, comprising: a 1T1R array D1, a 1T1R array D2 and a 1T1R array D3; the 1T1R array D1 includes n 1T1R devices R0b˜R(n−1)b for calculating and storing intermediate results s0˜n−1*, word line control signals corresponding to R0b˜R(n−1)b, are respectively VWL0b˜VWL(n−1)b, bit line control signals corresponding to R0b˜R(n−1)b are respectively VBL0b˜VBL(n−1)b, and source line control signals corresponding to R0b˜R(n−1)b are respectively VSL0b˜VSL(n−1)b; the 1T1R array D1 is used for data backup; the 1T1R array D2 includes a 1T1R device Rn for calculating and storing carry data ci, i is an integer from 0 to 8, a word line control signal corresponding to Rn is VWLn, a bit line control signal corresponding to Rn is VBLn and a source line control signal corresponding to Rn is VSLn; the 1T1R array D3 includes n 1T1R devices R0˜Rn−1 for calculating and storing addition operation results s0˜n−1, word line control signals corresponding to R0˜Rn−1 are respectively VWL0˜VWL(n−1), bit line control signals corresponding to R0˜Rn−1 are respectively VBL0˜VBL(n−1), and source line control signals corresponding to R0˜Rn−1 are respectively VSL0˜VSL(n−1); and the intermediate data s0˜n−1* calculated by the 1T1R array D1 and the carry information ci calculated by the 1T1R array D2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array D3 through the data transmission circuit.
  • 10. An operating method based on the operation circuit according to claim 9, comprising: (S2-1) inputting logic signals VWL0˜(n−1)=1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to write the input data a0˜n−1 into R0˜n−1 of the 1T1R array D3; inputting logic signals VWLn=1, VBLn=c0 and VSLn=c0 to write the carry information c0 into Rn of the 1T1R array D2, a word line input signal, a bit line input signal and a source line input signal of the 1T1R array D1 being the same as that of the 1T1R array D3;(S2-2) inputting logic signals VWL0˜(n−1)=b0˜n−1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to calculate intermediate results s0˜n−1*=a0˜n−1⊕b0˜n−1 and store s0˜n−1* in R0˜n−1 of the 1T1R array D3; inputting logic signals VWL0b˜(n−1)b=b0˜n−1, VBL0b˜(n−1)=a0˜n−1 and VSL0b˜(n−1)b=a0˜n−1 to calculate intermediate results s0*n−1* and store s0˜n−1 in R0b˜(n−1)b of the 1T1R array D1; inputting logic signals VWLn=1, VBLn=a0 and VSLn=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in Rn of the 1T1R array D2;(S2-3) reading s0* from R0b of the 1T1R array D1, and reading s1* from R1b of the 1T1R array D1; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜n−1=0, VBL0=s0*, VBL1=s1*, VBL2˜n−1=0, VSL0=s0*, VSL1=s1* and VSL2˜n−1=0 to calculate s0=a0⊕b0⊕c0 and s1=a1⊕b1⊕c1, and store s0 in R0 of the 1T1R array D3 and s1 in R1 of the 1T1R array D3;(S2-4) denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2;(S2-5) inputting logic signals VWLn=1, VBLn=ai−1 and VSLn=bi−1 to calculate ci=ai−1·bi−1+ai−1·ci−1+ci−1·bi−1 and store ci in Rn of the 1T1R array D2;(S2-6) reading si* from Rib of the 1T1R array D1; inputting logic signals VWL0˜(i−1)=0, VWLi=ci, VWL(i+1)˜(n−1)=0, VBL0˜(i−1)=0, VBLi=si*, VBL(i+1)˜(n−1)=0, VSL0˜(i−1)=0, VSLi=si* and VSL(i+1)˜(n−1)=0 to calculate si=ai⊕bi⊕ci and store si in Ri of the 1T1R array D3;(S2-7) incrementing the value of i by 1, and if i<n−1, proceeding to the step (S2-5); otherwise, proceeding to step (S2-8);(S2-8) inputting logic signals VWLn=1, VBLn=an−2 and VSLn=bn−2 to calculate cn−1=an−2·bn−2+an−2·cn−2+cn−2·bn−2 and store cn−1 in Rn of the 1T1R array D2;(S2-9) reading sn−1* from R(n−1)b of the 1T1R array D1; inputting logic signals VWL0˜(n−2)=0, VWL(n−1)=cn−1, VBL0˜(n−2)=0, VBL(n−1)=sn−1*, VSL0˜(n−2)=0 and VSL(n−1)=sn−1* to calculate sn−1=an−1⊕bn−1⊕cn−1 and store sn−1 in Rn−1 of the 1T1R array D3; and(S2-10) inputting logic signals VWLn=1, VBLn=an−1 and VSLn=bn−1 to calculate cn=an−1·bn−1+an−1·cn−1+cn−1·bn−1 and store cn in Rn of the 1T1R array D2.
  • 11. An operation circuit based on the computing array according to claim 4 for implementing an optimized multi-bit step-by-step carry adder, in which sums s0˜n−1 and carry information cn are calculated according to input data a0˜n−1 and b0˜n−1 and carry information c0, and n represents the number of bits of the operation data, comprising: a 1T1R array E1, a 1T1R array E2 and a 1T1R array E3; the 1T1R array E1 includes n 1T1R devices R0b˜R(n−1)b for calculating and storing data s0˜n−1*, word line control signals corresponding to R0b˜R(n−1)b are respectively VWL0b˜VWL(n−1)b, bit line control signals corresponding to R0b˜R(n−1)b are respectively VBL0b˜VBL(n−1)b, and source line control signals corresponding to R0b˜R(n−1)b are respectively VSL0b˜VSL(n−1)b; the 1T1R array E1 is used for data backup; the 1T1R array E2 includes (n+1) 1T1R devices R0c˜Rnc for calculating and storing carry data ci, i is an integer from 0 to n, word line control signals corresponding to R0c˜Rnc are respectively VWL0c˜VWLnc, bit line control signals corresponding to R0c˜Rnc are respectively VBL0c˜VBLnc, and source line control signals corresponding to R0c˜Rnc are respectively VSL0c˜VSLnc; the 1T1R array E3 includes n 1T1R devices R0˜Rn−1 for calculating and storing addition operation results s0˜n−1, word line control signals corresponding to R0˜Rn−1 are respectively VWL0˜VWL(n−1), bit line control signals corresponding to R0˜Rn−1 are respectively VBL0˜VBL(n−1), and source line control signals corresponding to R0˜Rn−1 are respectively VSL0˜VSL(n−1); and the intermediate data s0˜n−1* calculated by the 1T1R array E1 and the carry information ci calculated by the 1T1R array E2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array E3 through the data transmission circuit.
  • 12. An operating method based on the operation circuit according to claim 11, comprising: (S3-1) inputting logic signals VWL0˜(n−1)=1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to write the input operational data a0˜n−1 into R0˜n−1 of the 1T1R array E3; inputting logic signals VWL0b˜(n−1)b=1, VBL0b˜(n−1)b=a0˜n−1 and VSL0b˜(n−1)b=a0˜n−1 to write the input operational data a0˜n−1 into R0b˜(n−1)b of the 1T1R array E1; inputting logic signals VWL0c˜nc=1, VSL0c˜nc=c0 and VSL0c˜nc=c0 to write the carry information c0 into R0c˜nc of the 1T1R array E2;(S3-2) inputting logic signals VWL0˜(n−1)=b0˜n−1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to calculate intermediate results and store s0˜n−1* in R0˜n−1 of the 1T1R array E3; inputting logic signals VWL0b˜(n−1)b=b0˜n−1, VBL0b˜(n−1)b=a0˜n−1 and VSL0b˜(n−1)b=a0˜n−1 to calculate intermediate results s0˜n−1* and store s0˜n−1* in R0b˜(n−1)b of the 1T1R array E1; inputting logic signals VWL0=0, VWL1c˜nc=1, VBL0c˜nc=a0 and VSL0c˜nc=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜nc of the 1T1R array E2;(S3-3) reading s0* from R0b of the 1T1R array E1, and reading s1* from R1b of the 1T1R array E1; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜(n−1)=0, VBL0=s0*, VBL1=s1*, VBL2˜(n−1)=0, VSL0=s0* , VSL1=s1* and VSL2˜(n−1)=0 to calculate s0=a0⊕b0⊕c0 and s1=a1⊕b1⊕c1, and store s0 in R0 of the 1T1R array E3 and s1 in R1 of the 1T1R array E3; inputting logic signals VWL0c˜1c=0, VWL2c˜nc=1, VBL0c˜nc=a1 and VSL0c˜nc=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R2c˜nc of the 1T1R array E2;(S3-4) denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2;(S3-5) reading si* from Rib of the 1T1R array E1; inputting logic signals VWL0˜(i−1)=0, VWLi=ci, VWL(i+1)˜(n−1)=0, VBL0˜(i−1)=0, VBLi=s1*, VBL(i+1)˜(n−1)=0, VSL0˜(i−1)=0, VSLi=si* and VSL(i+1)˜(n−1)=0 to calculate si=ai⊕bi⊕ci, and store si in Ri of the 1T1R array E3; inputting logic signals VWL0c˜ic=0, VWL(i+1)c˜nc=1, VBL0c˜nc=ai and VSL0c˜nc=bi to calculate ci+1=ai⊕bi+ai·ci+ci·bi and store ci+1 in R(i+1)c˜nc of the 1T1R array E2;(S3-6) incrementing the value of i by 1, and if i<n−1, proceeding to the step (S3-5); otherwise, proceeding to a step (S3-7); and(3-7) reading sn−1* from R(n−1)b of the 1T1R array E1; inputting logic signals VWL0˜(n−2)=0, VWL(n−1)=cn−1, VBL0˜(n−2)=0, VBL(n−1)=sn−1*, VSL0˜(n−2)=0 and VSL(n−1)=sn−1* to calculate sn−1=an−1⊕bn−1⊕cn−1 and store sn−1 in Rn−1 of the 1T1R array E3; and inputting logic signals VWL0c˜(n−1)c=0, VWLnc=1, VBL0c˜nc=an−1 and VSL0c˜nc=bn−1 to calculate cn=an−1·bn−1+an−1·cn−1+cn−1·bn−1 and store cn in Rnc of the 1T1R array E2.
  • 13. An operation circuit based on the computing array according to claim 4 for implementing a 2-bit data selector, in which a logic signal a, a logic signal b and a control signal Sel are input to output the logic signal a or the logic signal b by controlling a value of the control signal Sel, comprising: a 1T1R array F, wherein the 1T1R array F includes one 1T1R device R, a word line signal corresponding to R is VWL, a bit line signal corresponding to R is VBL, and a source line signal corresponding to R is VSL.
  • 14. An operating method based on the operation circuit according to claim 13, comprising: (S4-1) inputting logic signals VWL=1, VBL=a and VSL=ā to initialize the 1T1R device R, and write the input logic signal a into R of the 1T1R array F; and(S4-2) inputting logic signals VWL=Sel, VBL=b and VSL=b to input the logic signal b and the control signal Sel so as to select an output logic signal out,wherein the logic signal a and the logic signal b represent only two independent logic signals; when the control signal Sel=0, the output signal out=a; and when the control signal Sel=1, the output signal out=b.
  • 15. An operation circuit based on the computing array according to claim 4 for implementing a multi-bit carry select adder, in which sums s0˜n−1 and carry information cn are calculated according to input data a0˜n−1 and b0˜n−1 and carry information c0, n represents the number of bits of the operation data, and in the calculation process, according to the carry information of each bit, an XNOR operation result or an XOR operation result of the corresponding bit of the operation data is selected as bit information of the sum, comprising: a 1T1R array G1, a 1T1R array G2 and a 1T1R array G3; the 1T1R array G1 includes n 1T1R devices R0x˜R(n−1)x for calculating and storing XNOR operation results of data a0˜n−1 and b0˜n−1 (X0˜n−1=a0˜n−1 XNOR b0˜n−1), word line control signals corresponding to R0x˜R(n−1)x are respectively VWL0x˜VWL(n−1)x, bit line control signals corresponding to R0x˜R(n−1)x are respectively VBL0x˜VBL(n−1)x, and source line control signals corresponding to R0x˜R(n−1)x are respectively VSL0x˜VSL(n−1)x; the 1T1R array G2 includes (n+1) 1T1R devices R0c˜Rnc for calculating carry data ci, i is an integer from 0 to n, word line control signals corresponding to R0c˜Rn, are respectively VWL0c˜VWLnc, bit line control signals corresponding to R0c˜Rnc are respectively VBL0C˜VBLnc, and source line control signals corresponding to R0c˜Rnc are respectively VSL0c˜VSLnc; the 1T1R array G3 includes n 1T1R devices R0˜Rn−1 for calculating and storing addition operation results s0˜n−1, word line control signals corresponding to R0˜Rn−1 are respectively VWL0˜VWL(n−1), bit line control signals corresponding to R0˜Rn−1 are respectively VBL0˜VBL(n−1), and source line control signals corresponding to R0˜Rn−1 are respectively VSL0˜VSL(n−1); and the XNOR operation results X0˜n−1 calculated by the 1T1R array G1 and the carry information ci calculated by the 1T1R array G2 are converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array G3 through the data transmission circuit.
  • 16. An operating method based on the operation circuit according to claim 15, comprising: (S5-1) inputting logic signals VWL0x˜(n−1)x=1, VBL0x˜(n−1)x=b0˜n−1 and VSL0x˜(n−1)x=b0˜n−1 to store the result b0˜n−1 of inverting the input operation data b0˜n−1 in R0x˜(n−1)x of the 1T1R array G1; inputting logic signals VWL0c˜nc=1, VSL0c˜nc=c0 and VSL0c˜nc=c0 to store c0 in R0c˜nc of the 1T1R array G2; inputting logic signals VWL0˜(n−1)=1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to store the input operational data a0˜n−1 in R0˜n−1 of the 1T1R array G3;(S5-2) inputting logic signals VWL0x˜(n−1)x=a0˜n−1, VBL0x˜(n−1)x=b0˜n−1 and VSL0x˜(n−1)x=b0˜n−1 to calculate XNOR operation results X0˜n−1=a0˜n−1 XNOR b0˜n−1 of the calculated data a0˜n−1 and b0˜n−1 and store X0˜n−1 in R0x˜(n−1)x of the 1T1R array G1; inputting logic signals VWL0c=0, VWL1c-nc=1, VBL0c˜nc=a0 and VSL0c˜nc=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜nc of the 1T1R array G2; inputting logic signals VWL0˜(n−1)=b0˜n−1, VBL0˜(n−1)=a0˜n−1 and VSL0˜(n−1)=a0˜n−1 to calculate XOR operation results s0˜n−1*=a0˜n−1⊕b0˜n−1 and store s0˜n−1* in R0˜n−1 of the 1T1R array G3;(S5-3) inputting logic signals VWL0c˜1c=0, VWL2c˜nc=1, VBL0c˜nc=a1 and VSL0c˜nc=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R2c˜ne of the 1T1R array G2; inputting logic signals VWL0=c0, VWL1=c1, VWL2˜(n−1)=0, VBL0˜(n−1)=X0˜n−1 and VSL0˜(n−1)=X0˜n−1 to calculate s0 and s1, and store s0 in R0 of the 1T1R array G3 and s1 in R1 of the 1T1R array G3; when c0=0, s0=a0⊕b0, and when c1=0, s0=a0⊕b0; when c1=0, s1=a1⊕b1, and when c1=1, s1=a1⊕b1;(S5-4) denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=2;(S5-5) inputting logic signals VWL0c˜ic=0, VWL(i+1)c˜nc=1, VBL0c˜nc=ai and VSL0c˜nc=bi to calculate ci+i=ai·bi+ai·ci+ci·bi and store ci+1 in R(i+1)c˜nc of the 1T1R array G2; inputting logic signals VWL0˜(i−1)=0, VWLi=ci, VWL(i+1)˜(n−1)=0, VBL0˜(n−1)=X0˜n−1 and VSL0˜(n−1)=X0˜n−1 to calculate si and store si in Ri of the 1T1R array G3; when ci=0, si=ai⊕bi, and when ci=1, si=ai bi;(S5-6) incrementing the value of i by 1, and if i<n−1, proceeding to the step (S5-5); otherwise, proceeding to a step (S5-7); and(S5-7) inputting logic signals VWL0c˜(n−1)c=0, VWLnc=1, VSL0c˜nc=an−1 and VSL0c˜nc=bn−1 to calculate cn=an−1·bn−1+an−1·cn−1+cn−1·bn−1 and store cn in Rnc of the 1T1R array G2; inputting logic signals VWL0˜(n−2)=0, VWL(n−1)=cn−1, VBL0˜(n−1)=X0˜n−1 and VSL0˜(n−1)=X0˜n−1 to calculate sn−1 and store sn−1 in Rn−1 of the 1T1R array G3; when cn−1=0, sn−1=an−1⊕bn−1, and when cn−1=1, s7=an−1⊕bn−1.
  • 17. An operation circuit based on the computing array according to claim 4 for implementing a multi-bit pre-calculation adder, in which sums s0˜n−1 and carry information cn are calculated according to input data a0˜n−1 and b0˜n−1 and carry information c0, and n represents the number of bits of the operation data, comprising: a 1T1R array H1 and a 1T1R array H2; the 1T1R array H1 includes (n+1) 1T1R devices R0c˜Rnc for calculating carry data ci, i is an integer from 0 to n, word line control signals corresponding to R0c˜Rnc are respectively VWL0c˜VWLnc, bit line control signals corresponding to R0c˜Rnc are respectively VBL0c˜VBLnc, and source line control signals corresponding to R0c˜Rnc are respectively VSL0c˜VSLnc; the 1T1R array H2 includes n 1T1R devices R0˜Rn−1 for calculating and storing addition operation results s0˜n−1, word line control signals corresponding to R0˜Rn−1 are respectively VWL0˜VWL(n−1), bit line control signals corresponding to R0˜Rn−1 are respectively VBL0˜VBL(n−1), and source line control signals corresponding to R0˜Rn−1 are respectively VSL0˜VSL(n−1); and the carry information ci calculated by the 1T1R array H1 is converted by the signal amplifier and the control signal modem, and then transmitted to the 1T1R array H2 through the data transmission circuit.
  • 18. An operating method based on the operation circuit according to claim 17, comprising: (S6-1) inputting logic signals VWL0c˜nc=1, VBL0c˜nc=c0 and VSL0c˜nc=c0 to store c0 in R0c˜nc of the 1T1R array H1; inputting logic signals VWL0˜(n−1)=1, VBL0˜(n−1)=c0 and VSL0˜(n−1)=c0 to store the input carry information c0 in R0˜n−1 of the 1T1R array H2;(S6-2) inputting logic signals VWL0c=0, VWL1c˜nc=1, VBL0c˜nc=a0 and VSL0c˜nc=b0 to calculate c1=a0·b0+a0·c0+c0·b0 and store c1 in R1c˜nc of the 1T1R array H1; inputting logic signals VWL0˜(n−1)=1, VBL0˜(n−1)=a0, VSL0=b0 and VSL1˜(n−1)=b0 to calculate s0′=c0·a0+c0·a0·b0+c0·a0·b0 and c1=a0·b0+a0·c0+c0·b0, and store s0′ in R0 of the 1T1R array H2 and c1 in R1˜n−1 of the 1T1R array Hz;(S6-3) inputting logic signals VWL0c˜1c=0, VWL2e˜nc=1, VBL0c˜nc=a1 and VSL0c˜nc=b1 to calculate c2=a1·b1+a1·c1+c1·b1 and store c2 in R2c˜nc of the 1T1R array H1; inputting logic signals VWL0˜(n−1)=1, VBL0=b0, VBL1˜(n−1)=a1, VSL0=c1, VSL1=b1 and VSL2˜(n−1)=b1 to calculate s0=a0⊕b0⊕c0, s1′=c1·a1+c1·a1·b1+c1·a1·b1 and c2=a1·b1+a1·c1+c1·b1, and store s0 in R0 of the 1T1R array H2, s1′ in R1 of the 1T1R array H2 and c2 in R2˜(n−1) of the 1T1R array H2;(S6-4) denoting the i-th bit in the operation data or operation result by i, and giving i an initial value of i=1;(S6-5) inputting logic signals VWL0c˜(i+1)0, VWL(i+2)c˜nc=1, VBL0c˜nc=a1+1 and VSL0c˜nc=bi+1 to calculate ci+2=ai+1·bi+1+ai+1·ci+1+ci+1·bi+1 and store ci+2 in R(i+2)c−nc of the 1T1R array H1; inputting logic signals VWL0˜(i−1)=0, VWLi˜(n−1)=1, VBL0˜(i−1)=0, VBLi=bi, VBL(i+1)˜(n−1)=ai+1, VSL0˜(i−1)=0, VSLi=ci+1, VSL(i+1)=b(i+1) and VSL(i+2)˜(n−1)=bi+1 to calculate si=ai⊕bi⊕ci, si+1′=ci+1·ai+1+ci+1·ai+1+bi+1+ci+1·ai+1·bi+1 and ci+2=ai+1·bi+1+ai+1·ci+1+ci+1·bi+1 and store si in Ri of the 1T1R array H2, si+1* in Ri+1 of the 1T1R array H2 and ci+2 in R(i+2)˜(n−1) of the 1T1R array H2;(S6-6) incrementing the value of i by 1, and if i<n−1, proceeding to the step (S6-5); otherwise, proceeding to a step (S6-7);(S6-7) inputting logic signals VWL0c˜(n−1)c=0, VWLnc=1, VBL0c˜nc=an−1 and VSL0c˜nc=bn−1 to calculate cn=an−1·bn−1+an−1·cn−1+cn−1·bn−1 and store cn in Rnc of the 1T1R array H1; inputting logic signals VWL0˜(n−3)=0, VWL(n−2)˜(n−1)=1, VBL0˜(n−3)=0, VBL(n−2)=bn−2, VBL(n−1)=an−1, VSL0˜(n−3)=0, VSL(n−2)=cn−1 and VSL(n−1)=bn−1 to calculate sn−2=an−2⊕bn−2⊕cn−2 and sn−1*=cn−1·an−1+cn−1·an−1·bn−1+cn−1·an−1·bn−1, and store sn−2 in Rn−2 of the 1T1R array H2 and sn−1* in Rn−1 of the 1T1R array H2; and(S6-8) inputting logic signals VWL0˜(n−2)=0, VWL(n−1)=1, VBL0˜(n−2)=0, VBLn(n−1)=bn−1, VSL0˜(n−2)=0 and VSL(n−1)=cn to calculate sn−1=an−1⊕bn−1⊕cn−1 and store sn−1 in Rn−1 of the 1T1R array H2.
  • 19. The computing array based on 1T1R device according to claim 2, wherein the peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit; the state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result;an input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to the word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array;an input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to the bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array;an input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to the source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array;the word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array;an input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem;a first input terminal of the control signal modem is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1T1R array in the compute array;an input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit.
  • 20. The computing array based on 1T1R device according to claim 3, wherein the peripheral circuit includes: a state controller, a word line decoder, a source line decoder, a bit line decoder, a signal amplifier, a control signal modem and a data transmission circuit; the state controller has a data input/output terminal Data, an address input terminal Address, a clock signal input terminal CLK, a result input terminal, a word line output terminal, a bit line output terminal, a source line output terminal and a secondary output terminal; the data input/output terminal Data of the state controller is configured to input calculated data on the one hand and output a calculated result on the other hand, the address input terminal Address of the state controller is configured to input address information of a selected device, the clock signal input terminal CLK of the state controller is configured to input a clock signal for controlling a calculation timing, and the result input terminal of the state controller is configured to input a calculated result generated by a pre-stage circuit; the state controller generates a control signal according to the input data, address information, clock signal and calculated result, or outputs a final calculated result;an input terminal of the word line decoder is connected to the word line output terminal of the state controller, an output terminal of the word line decoder is connected to the word line of the 1T1R array; the word line decoder decodes the control signal generated by the state controller to obtain a word line control signal, and inputs the word line control signal to the 1T1R devices through the word line of the 1T1R array;an input terminal of the bit line decoder is connected to the bit line output terminal of the state controller, an output terminal of the bit line decoder is connected to the bit line of the 1T1R array; the bit line decoder decodes the control signal generated by the state controller to obtain a bit line control signal, and inputs the bit line control signal to the 1T1R devices through the bit line of the 1T1R array;an input terminal of the source line decoder is connected to the source line output terminal of the state controller, an output terminal of the source line decoder is connected to the source line of the 1T1R array; the source line decoder decodes the control signal generated by the state controller to obtain a source line control signal, and inputs the source line control signal to the 1T1R devices through the source line of the 1T1R array;the word line control signal, the bit line control signal and the source line control signal are commonly applied to the 1T1R array to control states of the 1T1R devices in the 1T1R array;an input terminal of the signal amplifier is connected to a bit line of the 1T1R array; when data information stored in the 1T1R array is read, the signal amplifier converts an acquired resistance signal stored by the 1T1R device into a voltage signal and then outputs it to the control signal modem;a first input terminal of the control signal modem is connected to the secondary output terminal of the state controller, a second input terminal of the control signal modem is connected to an output terminal of the signal amplifier; the control signal modem decodes the control signal generated by the state controller to obtain a control signal of a next-stage circuit, or directly transmits the data voltage signal output by the signal amplifier; the next-stage circuit is the next 1T1R device in the same 1T1R array, or a next 1 T1R array in the compute array;an input terminal of the data transmission circuit is connected to an output terminal of the control signal modem; the data transmission circuit feeds back the data voltage signal output by the control signal modem to the state controller through the result input terminal of the state controller, or transmits the control signal output from the control signal modem to the word line decoder, the bit line decoder and the source line decoder of the next-stage circuit.
Priority Claims (1)
Number Date Country Kind
201711358553.4 Dec 2017 CN national
PCT Information
Filing Document Filing Date Country Kind
PCT/CN2018/090247 6/7/2018 WO 00