Claims
- 1. A semiconductor device comprising:
- a semiconductor substrate;
- a conductivity-modulation field effect transistor formed on said substrate, said transistor having a base region of a first conductivity type, a source region of a second conductivity type formed in one portion of said base region, a source electrode for electrically connecting said base region and said source region with each other, a drain region of the first conductivity type formed in another portion of said base region, a drain electrode formed on said drain region, and a gate electrode insulatively provided above said substrate on a channel region formed between source and drain regions; and
- means for, when said transistor is turned off, facilitating carriers in said device to flow into said drain electrode, thereby accelerating dispersion of the carriers in said transistor, said means comprising a first heavily-doped semiconductive layer of the second conductivity type which is formed in said drain region to have a conductivity type opposite to that of said drain region, said semiconductive layer being in contact with said drain electrode.
- 2. The device according to claim 1, wherein said substrate has a surface in which said base region an said drain region are formed.
- 3. The device according to claim 2, further comprising:
- a second heavily-doped semiconductive layer which is formed in said drain region to overlap the first heavily-doped semiconductive layer, said second semiconductive layer having a conductivity type opposite to that of said first semiconductive layer.
- 4. The device according to claim 2, further comprising:
- a second heavily-doped semiconductive layer which is formed in said drain region to be contact with said drain electrode, said second semiconductive layer having a conductivity type opposite to that of said first semiconductive layer.
- 5. The device according to claim 4, further comprising:
- a third heavily-doped semiconductive layer having the conductivity type opposite to that of said source region and which is formed in said substrate so as to overlap said base region and said source region and to be in contact with said source electrode.
- 6. A single-gate type conductivity-modulation field effect transistor comprising:
- a first base layer having a surface;
- a second base layer of a first conductivity type provided in the surface of said first base layer;
- a source layer provided in said second base layer;
- a source electrode provided on the layer surface, for electrically shorting said second base layer with said source layer;
- a drain layer having said first conductivity type provided in said layer surface;
- a drain electrode formed on said layer surface to be in contact with said drain layer;
- a gate electrode insulatively provided above said layer surface, for covering a certain surface portion of said second base layer which is positioned between said first base layer and said source layer to define a channel region below said gate electrode; and
- a heavily-doped semiconductor layer of a second conductivity type which is provided in a selected surface portion of said drain layer and which is included in said drain layer to be in contact with said drain electrode, said heavily-doped semiconductor layer facilitating, when said transistor is turned off, carriers accumulated in said first base layer to flow into said drain electrode through said drain layer, thereby accelerating dispersion of the carriers in said transistor; and
- wherein said first base layer and said source layer have said second conductivity type.
- 7. The transistor according to claim 6, wherein said drain layer comprises heavily-doped drain layer portions each pair of two adjacent layer portions of which are separated from each other.
- 8. The transistor according to claim 7, wherein said source layer has one side portion along which a plurality of projected layer portions are aligned to define a comb-shaped planar pattern.
- 9. The transistor according to claim 6, further comprising:
- a high-resistive layer insulating provided above said layer surface and connected with said source electrode and said drain electrode.
- 10. The transistor according to claim 6, wherein said drain layer comprises:
- a first diffusion layer; and
- a second diffusion layer which at least partially surrounds said heavily doped semiconductor layer and which has its depth smaller than that of said first diffusion layer, said second diffusion layer formed adjacent said first diffusion layer.
- 11. The transistor according to claim 10, further comprising:
- a second heavily doped semiconductor layer of a conductivity type which is the same of that of said drain layer and which is formed in said first diffusion layer.
- 12. The transistor according to claim 11, wherein said second heavily doped semiconductor layer is in contact with said drain electrode.
Priority Claims (6)
Number |
Date |
Country |
Kind |
62-41309 |
Feb 1987 |
JPX |
|
62-110743 |
May 1987 |
JPX |
|
62-304634 |
Dec 1987 |
JPX |
|
63-199538 |
Aug 1988 |
JPX |
|
1-18309 |
Jan 1989 |
JPX |
|
1-187393 |
Jul 1989 |
JPX |
|
Parent Case Info
This application is a continuation-in-part application of the co-pending U.S. patent application Ser. No. 233,425 filed on Aug. 18, 1988 (now abandoned) which is a continuation-in-part of co-pending U.S. patent application Ser. No. 160,277 filed on Feb. 25, 1988, now U.S. Pat. No. 4,980,743.
US Referenced Citations (17)
Foreign Referenced Citations (8)
Number |
Date |
Country |
0280535 |
Aug 1988 |
EPX |
0224269 |
Jun 1987 |
DEX |
0023277 |
Feb 1977 |
JPX |
58-97866 |
Jun 1983 |
JPX |
60-196974 |
Oct 1985 |
JPX |
60-254658 |
Dec 1985 |
JPX |
61-82477 |
Apr 1986 |
JPX |
61-123184 |
Jun 1986 |
JPX |
Non-Patent Literature Citations (2)
Entry |
"Improved COMFETs with Fast Switching Speed and High-Current Capability" A. M. Goodman et al., RCA Laboratories, Princeton, NJ 08540 and RCA Solid State Division, Mountainton, PA 18707, CH1973-7/83/0000-0079, 1983 IEEE. |
IEEE Transactions on Electron Devices, vol. ED-33, No. 12, Dec. 1986 "n-Channel Lateral Insulated Gate Transistors: Part I-Steady-State Characteristics", Deva N. Pattanayak et al., 0018-9383/86/1200-1956. |
Continuation in Parts (2)
|
Number |
Date |
Country |
Parent |
233425 |
Aug 1988 |
|
Parent |
160277 |
Feb 1988 |
|