Patent Application
20090174018
The present invention relates to construction methods for backside illuminated image sensors and, more particularly, to construction methods for backside illuminated image sensors using improved methods for providing mechanical integrity for the semiconductor wafer during processing and performing high temperature processing out of the presence of color filters.
Solid state image sensors, including complimentary metal oxide semiconductor (CMOS) imagers and charge-coupled devices (CCD), may be used in many different digital imaging applications to capture scenes. A solid state image sensor may include an array of pixels arranged on a semiconductor wafer. Pixel arrays may be formed on semiconductor wafers using semiconductor processing techniques such as, for example, photolithography, ion implantation, oxidation, thin film deposition and etching. When exposed to incident light to capture a scene, a photosensitive element of each pixel in the array may output a signal having a magnitude corresponding to an intensity of light at one point in the scene. The signals output from each photosensitive element may be processed to form an image representing the captured scene.
Conventional solid state image sensors may include interconnect structures, which may electrically connect the photosensitive elements with control and read-out circuitry. The interconnect structures may include layers of dielectrics and patterned metal lines and vias.
Each pixel in a solid state image sensor may have an assigned color, such as, for example, red, green or blue. Red, green and blue filters on the pixels may function to pass only light having wavelengths corresponding to the assigned color and to reflect or absorb all other wavelengths. The passed light may enter the photosensitive element whereas the reflected or absorbed light may not. Accordingly, the signal produced by each photosensitive element may have a magnitude representing an intensity of a particular color of incident light at a point in the scene.
The color filters may be formed of photoresist-type materials, which may have relatively low melting points. Specifically, the color filters may have melting points lower than the processing temperatures required during some stages of semiconductor chip processing such as, for example, formation of the interconnect layers described above. Therefore, it may be desirable that color filters are deposited after high temperature processing takes place. Alternatively, other techniques may be devised to reduce temperatures used in processing the semiconductor chips so that processing may occur after the color filters are already in place.
In one arrangement, the interconnect structures may be formed over the photosensitive elements and the color filters may be formed over the interconnect structures. This arrangement may be desirable because the color filters may be formed after high temperature processing takes place. Using this arrangement, the incident light may propagate through the interconnect structures before reaching the surface of the photodiode. Some amount of incident light may be lost due to absorption and reflection of incident light in the interconnect structures. Additionally, some amount of light intended for a given pixel may end up in neighboring pixels due to diffraction and reflection, creating undesirable optical crosstalk between the pixels.
Additional structures, such as microlens elements, may be used to direct incident light toward the surfaces of the respective photosensitive elements and away from the interconnect structures to reduce at least some of the light loss and optical crosstalk. Microlenses, however, may not sufficiently reduce the light loss and optical crosstalk and may be complex to design and manufacture.
Alternatively, the above structure may be flipped so that light may be incident on the back side of the substrate. This construction may remove the interconnect structures from the optical path to allow the incident light to enter the sensor from the substrate side. These types of imagers are typically referred to as backside illuminated. This arrangement allows for direct illumination of the photosensitive elements while still allowing the interconnect structures to be placed and processed before color filters are placed. Because the substrate may be thick enough to absorb most, if not all, of the incident light before it is able to reach the photosensitive elements, however, it may be desirable for the semiconductor substrate to be substantially thinned in order to let the incident light through.
These and other features, aspects, and advantages of the embodiments of the present invention described below will become more fully apparent from the following description, appended claims, and accompanying drawings in which the same reference numerals are used for designating the same elements throughout the several figures, and in which:
As described above, it may be necessary to thin the substrate of a backside illuminated imager to allow light to propagate through the substrate and to reach the photosensitive elements. For a silicon substrate, it may be desirable to thin the silicon to no more than a few microns, which is far below the minimum thickness required to provide mechanical integrity for wafer handling during processing. Accordingly, the embodiments of the present invention address construction methods for image sensors that provide mechanical integrity for wafer handling during processing and for high temperature processing to take place before color filters are placed.
While the examples of the present invention are in terms of backside illuminated imagers, it is contemplated that it may be practiced with other semiconductor devices in which a thin substrate of a semiconductor material is formed on a substrate of another material.
At step 100 of
At step 104, optional “smart cut” fault line 214 may be formed in a handle wafer 212. At step 106, handle wafer 212 may be attached to semiconductor wafer 1 via, for example, adhesive bonding layer 216, as shown in
Handle wafer 212 may provide mechanical support for semiconductor wafer 1 during processing. In one example embodiment, handle wafer 212 may be used to provide mechanical support for semiconductor wafer 1 during initial processing steps and may be removed after these initial processing steps have been completed.
If a temporary wafer bonding adhesive is used, the handle wafer may be separated from the semiconductor wafer by sliding the semiconductor wafer relative to the handle wafer. The temporary adhesive may then be removed using acetone IPA (isopropyl alcohol.)
If included, optional smart cut fault line 214 may ease removal of handle wafer 212. Smart cut fault line 214 may provide for a separation of handle wafer 212 into a bulk portion 211 and a thin film portion 213 so that bulk portion 211 may be easily removed, leaving only thin film portion 213 remaining after removal.
Optional smart cut fault line 214 may be formed according to steps shown in
Alternatively, internal stress may be created in the wafer using lasers and a technique similar to the Stealth Dicing technology available from Hamamatsu Photonics. This technology focuses a laser beneath the surface of the wafer. While the Stealth dicing technique forms these stress points along the edges of the dies, the technique may also be used to form stress points over an area by, for example, raster scanning the laser across the surface of the handle wafer.
At step 402, handle wafer 212 may be heat treated at a second temperature. The second temperature may be greater than the first temperature and may be sufficient to create, through a crystal rearrangement effect in handle wafer 212 and through the pressure of the microcavities, a separation between thin film portion 213 and bulk portion 211. This second temperature may be, for example, 500 degrees Celsius for silicon. This separation may simplify mechanical removal of handle wafer 212 from wafer 1. That is, the separation may permit thin film portion 213 and bulk portion 211 to be pried apart, eliminating any need to grind the handle wafer down to remove it. Also, because bulk portion 211 of handle wafer 212 may be removed almost entirely intact, it may be re-used.
Even after the heat treatment, the handle wafer 211 provides sufficient support to semiconductor wafer 1 to allow conventional semiconductor processing steps to be performed, as described below.
It may be desirable to conduct heat treating step 402 before the color filters are placed on the wafer 1. Handle wafer 212 separated into thin film portion 213 and bulk portion 211 may provide sufficient mechanical support for processing semiconductor wafer 1. Accordingly, this step may take place before color filters are laid. Specifically, this step may take place after handle wafer 212 is attached to semiconductor wafer 1 and before original substrate 202 is removed, as described below. Alternatively, this step may take place after original substrate 202 is removed and before color filters 218 are attached, as described below. Further, because handle wafer 212 may be formed separately from semiconductor wafer 1, heat treating step 402 may also be conducted before semiconductor wafer 1 is attached to handle wafer 212.
After handle wafer 212 is attached to semiconductor wafer 1, handle wafer 212 may be used to provide mechanical support for semiconductor wafer 1 during further processing. Using handle wafer 212 to provide mechanical support, at step 108, original substrate 200 may be removed from semiconductor wafer 1, as shown in
One example method of forming etchstop 202 and removing substrate 200 down to etchstop 202 may be a bond-and-etch back technique. Bond-and-etch back includes bonding wafer 1 to handle wafer 212, grinding wafer 1 from the back surface to thin substrate 200 from wafer 1 and then chemically etching the remaining portion of substrate 200 down to etchstop 202. If desirable, etchstop 202 may also be removed at this point by chemical etching. One example suitable etchstop for use with such bond-and-etch back technique may include a heavily boron-doped etch stop layer. Any suitable etchstop may, however, be used as etchstop 202. Also, any other suitable methods of forming etchstop 202, such as silicon on insulator (SOI) and Silicon Nitride epitaxial layer methods, may be used.
After substrate 200 is removed, optional passivation and annealing of semiconductor wafer 1 may be performed (not shown). Then, at step 110, color filter array 218 may be formed on semiconductor wafer 1, as shown in
At step 112, optional microlens array 220 may be formed over color filter array 218, as shown in
IR alignment may be used to align the filters with the buried photodiodes. It may also be possible to create visible alignment marks on the semiconductor wafer during manufacture of the semiconductor wafer itself, which may be used to align the filters with the buried photodiodes.
At step 114, cover glass 224 may be formed over color filter array 218 or over microlens array 220, if provided. Cover glass 224 may be attached using at least two different methods. First, cover glass 224 may be attached directly to semiconductor wafer 1. Here, a passivation layer (not shown) may be formed on color filter array 218 and the outer edges of each imager. Cover glass 224 may then be attached directly to the passivation layer.
Second, as shown in
Permanently attached cover glass 224 may serve at least two functions. First, cover glass 224 may protect the color filters, microlenses and photosensitive elements disposed under it from particles in the ambient air during the remaining processing steps. Second, cover glass 224 may be used to provide mechanical support for semiconductor wafer 1 when the handle wafer 212 is removed.
The adhesive used to permanently bond cover glass 224 to semiconductor wafer 1 may be any suitable adhesive. However, the adhesive used should have different material characteristics than the adhesive used in adhesive bonding layer 216, which was used to bond handle wafer 212 to semiconductor wafer 1. This is because adhesive bonding layer 216 may be etched or otherwise processed to expose electrical contacts 210 when handle wafer 212 is subsequently removed and, if an adhesive having the same material characteristics were used for both applications, any processing technique used to remove adhesive bonding layer 216 may also affect the adhesive bonding cover glass 224 to semiconductor wafer 1. In one embodiment, an ultraviolet cured and set adhesive may used as the adhesive to permanently bond cover glass 224 to semiconductor wafer 1. Because ultraviolet radiation is used to cure and set the adhesive instead of, for example, heat, it may be used in the presence of the filters. Additionally, by using ultraviolet radiation to cure and set the adhesive as opposed to, for example, using a solvent, contamination of the glass due to outgas may be prevented.
To prevent warpage of the permanent cover glass, the gap between the color filter array and the microlens array (if included) may be pressurized during step 114 so that the pressure in the wafer is ambient at ambient temperature.
Because the cover glass may be used later to provide mechanical support for the wafer during processing, it may be desirable to protect the cover glass. For this purpose, a high modulus polyimide film such as, for example, the Kapton® film provided by Dupont, may be used. The film may cover the surface of the glass and may protect the glass from damage due to contact with a surface, chemicals contacting the glass and high temperature processing.
Using cover glass 224 for support, at step 116, handle wafer 212 may be removed, as shown in
After handle wafer 212 is removed, adhesive bonding layer 216 may be removed to expose electrical contacts 210 using wet etch or other suitable methods. If wet etch is used, an etchant is desirably chosen to remove adhesive bonding layer 216 without removing the adhesive used to bond cover glass 224 to semiconductor wafer 1. If a temporary wafer bonding coating was used to bond handle wafer 212 to semiconductor wafer 1, the material may be removed using, for example, acetone isopropyl alcohol (Acetone-IPA).
It may be desirable, at this point, to provide additional support for the remaining structure, which may be between 1.5 and 15 microns thick. This may be done, for example, by providing a thick polymer coating (e.g., thick polymer coating provided by HD Microsystems) on the surface of wafer 1 exposed when handle wafer 212 and adhesive bonding layer 216 are removed. A thick polymer film may be deposited on the exposed surface of the wafer. Tension may be applied to the film to align rods in the polymer coating creating a material having a coefficient of thermal expansion (CTE) that matches the CTE of the support layer on the previously exposed surface of the wafer at least in the x, y plane.
At step 118, optional flip-chip processing may be performed by forming a redistribution layer (not shown) and solder bumps 226, so as to electrically connect solder bumps 226 with exposed electrical contacts 210, as shown in
If no thick polymer coating is provided on the surface of wafer 1 that is exposed when handle wafer 212 and adhesive bonding layer 216 are removed, an electrolytic plating process may be used to form the bumps. If a thick polymer coating is provided, via holes may be formed in the thick polymer coating and filled with a conductive material. An electrolytic plating process may be used to form the conductive traces. If a thick polymer coating is provided, an ultraviolet exposed and cured polymer may be used to form the traces using printing, plating or sputtering. Because the wafer is supported by the thick polymer coating, the wafer may maintain its integrity under the vacuum provided in a sputter chamber and, therefore, sputtering may be used to deposit the traces.
At step 120, the wafer may be diced into individual dies or imagers. Before dicing, for example, wide gaps may be formed between individual imagers using a dry etch. A blade (e.g., a nickel diamond standard cutting blade) may then be used to scribe the wafer, cutting only partially through the wafer. A wet etch may then be used (e.g., Tetra-Methyl Ammonium Hydroxide (TMAH) or Potassium Hydroxide (KOH) to remove inclusions created by the blade. Die singulation may then be performed using dicing tape along with a narrower blade or a smaller collimated laser. The silicon edge of each individual die may be coated to provide a light seal. Alternatively, such light seal may be created for each singulated die by using a partial saw and opaque polymer fill followed by a re-saw or laser reduced cut width. The stealth dicing technique, described above, may also be used for die singulation.
In the final construction, each sensor package may be configured to receive incident light through a top surface of cover glass 224, as shown in
At step 300 of
At step 306, partial thickness via holes 22 may be formed in handle wafer 24, which is separate from semiconductor wafer 2. Steps 304 and 306 result in a handle wafer 24 with pre-formed partial thickness via holes. Each of the via holes may be formed so as to extend from a top surface of the handle wafer partially through the handle wafer toward a bottom surface of the handle wafer. Further, each of the via holes may be formed in a position on the handle wafer corresponding to a respective one of the electrical contacts on the semiconductor wafer. At this stage, the openings of the via holes may not be exposed from the handle wafer. They may be exposed later when the handle wafer is thinned, as described below. Alternatively, the via holes may be pre-formed in the handle wafer and may extend through the entire thickness of the handle wafer. They may be filled before the handle wafer is attached to the semiconductor wafer. The conductive traces and plating may also be in place before the handle wafer is attached to the semiconductor wafer.
At step 308, handle wafer 24 with pre-formed partial thickness via holes 22 already formed in it may be disposed over the semiconductor wafer. Here, via holes may be aligned with respective electrical contacts 20 using, for example, an IR alignment technique. At step 310, after the appropriate alignments have been made, handle wafer 24 may be attached to the semiconductor wafer using, for example, Benzocylobutene (BCB), a curable polymer or polimide or any suitable adhesive. If the via holes have been pre-formed and the trace work and plating are in place, an interconnect may be formed between the vias and the respective electrical contacts when the handle wafer is attached to the semiconductor wafer while both the handle wafer and semiconductor wafer are at their thickest.
The via holes may be formed in the handle wafer by, for example, dry plasma etching or other suitable processes. For this reason, forming the via holes in the handle wafer before attaching the handle wafer and before color filters are attached to the semiconductor wafer may be advantageous because high temperature dry plasma etching or other high temperature processes may take place away from the color filters. Using a handle wafer with pre-formed partial thickness via holes to provide mechanical integrity for the semiconductor wafer during processing may provide several additional advantages. First, the handle wafer may remain attached to the semiconductor wafer throughout the entire manufacturing process. Second, the handle wafer may allow for use of via holes to provide electrical connectivity between interconnect structures formed in the semiconductor wafer and external electrical components in a solid state image sensor that includes relatively low melting temperature color filters.
After handle wafer 24 with pre-formed via holes 22 is attached to the semiconductor wafer 2, it may be used to provide mechanical support for the semiconductor wafer during further processing. Using handle wafer 24 to provide mechanical support, at step 312, original substrate 10 may be removed from the semiconductor wafer, as shown in
After substrate 10 is removed, optional passivation and annealing of the semiconductor wafer may be performed (not shown). Then, at step 314, color filter array 28 may be formed on the semiconductor wafer, as shown in
IR alignment may be used to align the filters with the buried photodiodes. It may also be possible to create visible alignment marks on the semiconductor wafer during manufacture of the semiconductor wafer itself, which may be used to align the filters with the buried photodiodes.
At step 316, optional microlens array 30 may be formed over color filter array 28, as shown in
At step 318, optional protective covering 34 may be formed over color filter array 28 or over microlens array 30, if used. Optional covering 34 may be a cover glass, such as cover glass 224 described above with respect to the first embodiment. If such cover glass is used, it may be permanently attached using any of the methods described above with respect to the first embodiment or may be temporarily attached using any suitable method. Alternatively, because a permanent cover glass is not needed to provide mechanical integrity during processing, any temporary protection, such as protective tape, may be used as optional covering 34, as shown in
If a permanent cover glass is used, any suitable adhesive may be used. The restrictions described with respect to the first embodiment may not be applicable here because handle wafer 24 is not removed from the semiconductor wafer.
At step 320, if the via holes have not been pre-filled, the semiconductor wafer may be flipped so that the color filters and optional microlenses may be placed on a work surface. Then, handle wafer 24 may be thinned at least until openings of pre-formed via holes 22 are exposed from handle wafer 24, as shown in
At step 322, exposed via holes 22 may be filled with a conductive material, as shown in
At step 324, optional flip-chip processing may be performed by, for example, applying solder material to the exposed ends of exposed via holes 22 to form, for example, solder bumps 36, as shown in
An ultraviolet exposed and cured polymer may be used to form the conductive traces using printing, plating or sputtering. Because the wafer is supported by the handle wafer, the wafer may maintain its integrity under the vacuum provided in a sputter chamber and, therefore, sputtering may be used to deposit the traces.
In
After the exposed via holes are filled and/or after solder bumps are formed, any temporary protection for color filters and optional microlenses attached in step 318 may be removed. If no protection was attached or if a cover glass was attached, this step may be skipped.
The wafer may then be diced into individual dies or imagers. Before dicing, for example, wide gaps may be formed between individual imagers using a dry etch. A blade (e.g., a nickel diamond standard cutting blade) may then be used to scribe the wafer, cutting only partially through the wafer. A wet etch may then be used (e.g., Tetra-Methyl Ammonium Hydroxide (TMAH) or Potassium Hydroxide (KOH) to remove inclusions created by blade. Die singulation may then be performed using a narrower blade, a smaller collimated laser or dicing tape. The silicon edge of each individual die may be coated to provide a light seal at the perimeter of each singulated die. Alternatively, such light seal may be created for each singulated die by using a partial saw and opaque polymer fill followed by a re-saw or laser with a reduced cut width.
In the final construction, each sensor package may be configured to receive incident light through the bottom surface of the semiconductor wafer (i.e., the surface on which color filters and optional microlenses have been attached). Oriented this way, interconnect structures 18 may not be disposed between photodiodes in transistor and photodiode layer 16 and the incident light impinging on the photodiodes through the top surface of the semiconductor wafer. Accordingly, a backside illuminated sensor may be formed while preserving mechanical integrity of the semiconductor wafer and preserving the optical properties of the color filters.
While example embodiments of the invention have been shown and described herein, it will be understood that such embodiments are provided by way of example only. Numerous variations, changes and substitutions will occur to those skilled in the art without departing from the invention. Accordingly, it is intended that the appended claims cover all such variations as fall within the scope of the invention.
