CONTACT EXTENDED OVER AN ADJACENT SOURCE OR DRAIN REGION

FIELD OF THE DISCLOSURE

The present disclosure relates to integrated circuits, and more particularly, to contacts for source or drain regions.

BACKGROUND

As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, reducing the size of memory and logic cells is becoming increasingly more difficult, as is reducing device spacing at the device layer. As transistors are packed more densely, the formation of certain interconnect structures can be challenging given the limited spacing and number of tracks used for a given interconnect layer. Accordingly, there remain a number of non-trivial challenges with respect to forming semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are cross-sectional views of some semiconductor devices that illustrate a contact extended over an adjacent source or drain region, in accordance with an embodiment of the present disclosure.

FIG. 1C is a plan view of the integrated circuit of FIGS. 1A and 1B, in accordance with an embodiment of the present disclosure.

FIGS. 2A and 2B are cross-sectional views that illustrate a stage in an example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 3A and 3B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 4A and 4B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 5A and 5B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 6A and 6B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 7A and 7B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 8A and 8B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 9A and 9B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 10A and 10B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIGS. 11A and 11B are cross-sectional views that illustrate another stage in the example process for forming semiconductor devices that have a contact extended over an adjacent source or drain region, in accordance with some embodiments of the present disclosure.

FIG. 12 illustrates a cross-sectional view of a chip package containing one or more semiconductor dies, in accordance with some embodiments of the present disclosure.

FIG. 13 is a flowchart of a fabrication process for semiconductor devices having a contact extended over an adjacent source or drain region, in accordance with an embodiment of the present disclosure.

FIG. 14 illustrates a computing system including one or more integrated circuits, as variously described herein, in accordance with an embodiment of the present disclosure.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used.

DETAILED DESCRIPTION

Techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to device layer transistors, such as finFETs or gate-all-around transistors (e.g., ribbonFETs and nanowire FETs). In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The semiconductor region can be, for example, a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region (more generally, a diffusion region). A conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without making contact with the adjacent source or drain region. The contact may extend along the source/drain trench through a gate cut that extends orthogonally through the source/drain trench. A conductive via may contact the portion of the conductive contact that passes over the adjacent source or drain region. The conductive contact may have a first thickness above the source or drain region with which it contacts, and a second thickness above the adjacent source or drain region that it passes over, with the first thickness being greater than the second thickness (such as the example case where the first thickness is 5 nm or more greater than the second thickness). Numerous variations and embodiments will be apparent in light of this disclosure.

General Overview

As previously noted above, there remain a number of non-trivial challenges with respect to integrated circuit fabrication. In more detail, as devices become smaller and more densely packed, many structures become more challenging to fabricate as critical dimensions (CD) of the structures push the limits of current fabrication technology. Interconnects can be particularly challenging with the number of connections to be made and a limited footprint. For many advanced libraries and certain cell designs, a limited number of parallel signal tracks may be used in a given interconnect layer (e.g., a first metal layer). In such architectures, it can be challenging to make connections between each of the various transistor elements to a limited number of signal tracks. For example, some connections cannot be made directly above a given element (such as a source or drain region) as it would cause a short with another element on the same signal track.

Thus, and in accordance with an embodiment of the present disclosure, a conductive contact on a given source or drain region is extended laterally over an adjacent source or drain region without contacting the adjacent source or drain region. In some embodiments, a via may be located over the adjacent source or drain region to touch the conductive contact. According to some embodiments, the conductive contact may have a first height over the source or drain region that it contacts and a second height where it extends over an adjacent source or drain region, where the first height is greater than the second height. In some examples, the second height may be around half the height of the first height. In some embodiments, the first height may be between around 30 nm and around 40 nm and the second height may be between around 10 nm and around 20 nm. In some embodiments, the conductive contact partially wraps around one or more sides of the source or drain region. In some embodiments, a dielectric wall extends between the source or drain region and the adjacent source or drain region and also between corresponding gate structures of the adjacent devices. The conductive contact extends through a portion of the dielectric wall to be arranged over the adjacent source or drain region, according to some embodiments. In some examples, portions of other dielectric walls can be removed such that the contact also extends between adjacent source or drain regions while making contact with the adjacent source or drain regions.

According to an embodiment, an integrated circuit includes a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region. The integrated circuit further includes a dielectric wall extending in the first direction through an entire thickness of the gate structure and extending in the first direction adjacent to the source or drain region, and a conductive contact on at least a top surface of the source or drain region. The conductive contact includes a first section directly above the source or drain region and a second section extending away from the source or drain region along the second direction and through a portion of the dielectric wall such that the source or drain region is not below the second section.

According to another embodiment, an integrated circuit includes a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region located in a source/drain trench, and a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region located in the source/drain trench. The second source or drain region is adjacent to the first source or drain region within the source/drain trench along a second direction orthogonal to the first direction. The integrated circuit further includes a dielectric wall extending in the first direction between the first source or drain region and the second source or drain region and extending beyond the source/drain trench in the first direction, and a conductive contact on at least a top surface of the first source or drain region. The conductive contact has a first section directly above the first source or drain region and a second section extending away from the first section along the second direction and through a portion of the dielectric wall such that the second section extends over, but does not contact, the second source or drain region.

According to another embodiment, a method of forming an integrated circuit includes forming a fin comprising semiconductor material, the fin extending above a substrate and extending in a first direction; forming a source or drain region at one end of the fin; forming a gate electrode extending in a second direction over the semiconductor material; forming a dielectric fill extending in the second direction over the source or drain region; forming a first recess through an entire thickness of the gate electrode, the recess extending in the first direction such that the first recess is also formed adjacent to the source or drain region; forming a dielectric material within the first recess; forming a second recess through the dielectric fill and over the source or drain region; forming a first conductive material in the second recess; forming a third recess through a portion of the first conductive material, through a portion of the dielectric material, and through a portion of the dielectric fill adjacent to the dielectric material; and forming a second conductive material in the third recess.

The techniques can be used with any type of non-planar transistors, including finFETs (sometimes called tri-gate transistors), nanowire and nanoribbon transistors (sometimes called gate-all-around transistors), or forksheet transistors, to name a few examples. The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions that are deposited during an etch-and-replace source/drain forming process. The dopant-type in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate-first process or a gate-last process (sometimes called a replacement metal gate, or RMG, process). Any number of semiconductor materials can be used in forming the transistors, such as group IV materials (e.g., silicon, germanium, silicon germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. For instance, in some example embodiments, such tools may indicate the presence of a conductive contact on a source or drain region that includes a portion extending away from the rest of the conductive contact, such that the extended portion flies over an adjacent source or drain region. In some embodiments, a conductive via is connected to the portion of the conductive contact over the adjacent source or drain region.

It should be readily understood that the meaning of “above” and “over” in the present disclosure should be interpreted in the broadest manner such that “above” and “over” not only mean “directly on” something but also include the meaning of over something with an intermediate feature or a layer therebetween. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A monolayer is a layer that consists of a single layer of atoms of a given material. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure, with the layer having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A layer can be conformal to a given surface (whether flat or curvilinear) with a relatively uniform thickness across the entire layer.

Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer. If two materials are elementally different, then one of the materials has an element that is not in the other material.

Architecture

FIG. 1A is a cross-sectional view taken across the gate trench of three example semiconductor devices, a first semiconductor device 101, a second semiconductor device 103, and a third semiconductor device 105 according to an embodiment of the present disclosure. FIG. 1B is another cross-sectional view taken across the source/drain trench or diffusion region and contact trench adjacent to the gate trench either into or out of the page of FIG. 1A. FIG. 1C is a top-down cross-section view of the adjacent semiconductor devices 101/103/105 taken across the dashed line 1C-1C depicted in both FIG. 1A and FIG. 1B. FIG. 1A illustrates the cross-section taken across the dashed line 1A-1A depicted in FIG. 1C, and FIG. 1B illustrates the cross-section taken across the dashed line 1B-1B depicted in FIG. 1C. It should be noted that some of the material layers (such as dielectric layer 130) are not visible in the top-down view of FIG. 1C, given the location of the depicted cross-section.

Each of semiconductor devices 101/103/105 may be, for example, non-planar metal oxide semiconductor (MOS) transistors, such as tri-gate (e.g., finFET) or gate-all-around (GAA) transistors, although other transistor topologies and types could also benefit from the techniques provided herein. The illustrated example embodiments use the GAA structure. The various illustrated semiconductor devices represent a portion of an integrated circuit that may contain any number of similar semiconductor devices.

As can be seen, semiconductor devices 101/103/105 are formed on a substrate 102. Any number of semiconductor devices can be formed on substrate 102, but three are illustrated here as an example. Substrate 102 can be, for example, a bulk substrate including group IV semiconductor material (such as silicon, germanium, or silicon germanium), group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and/or any other suitable material upon which transistors can be formed. Alternatively, substrate 102 can be a semiconductor-on-insulator substrate having a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, substrate 102 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some embodiments, a lower portion of (or all of) substrate 102 is removed and replaced with one or more backside interconnect layers to form backside signal and power routing, during a backside process.

Each of semiconductor devices 101/103/105 includes one or more corresponding nanoribbons 104a/104b/104c, respectively, that extend parallel to one another along a direction between corresponding source or drain regions, as seen more clearly in FIG. 1C (e.g., a first direction into and out of the page in the cross-section view of FIG. 1A). Accordingly, nanoribbons 104a extend between source or drain regions 110a, nanoribbons 104b extend between source or drain regions 110b, and nanoribbons 104c extend between source or drain regions 110c. Nanoribbons 104a/104b/104c are one example of semiconductor regions or semiconductor bodies that extend between source or drain regions. The term nanoribbon may also encompass other similar shapes such as nanowires or nanosheets. The semiconductor material of nanoribbons 104a/104b/104c may be formed from substrate 102. In some embodiments, semiconductor devices 101/103/105 may each include semiconductor regions in the shape of fins that can be, for example, native to substrate 102 (formed from the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins can be formed of material deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In another such example, non-native fins can be formed in a so-called aspect ratio trapping based process, where native fins are etched away so as to leave fin-shaped trenches which can then be filled with an alternative semiconductor material (e.g., group IV or III-V material). In still other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate forming of the illustrated nanoribbons 104a/104b/104c during a gate forming process where one type of the alternating layers is selectively etched away so as to liberate the other type of alternating layers within the channel region, so that a gate-all-around (GAA) process can then be carried out. Again, the alternating layers can be blanket deposited and then etched into fins or deposited into fin-shaped trenches.

As can further be seen, adjacent semiconductor devices are separated by a dielectric fill 106. Dielectric fill 106 provides shallow trench isolation (STI) between any adjacent semiconductor devices. Dielectric fill 106 can be any suitable dielectric material, such as silicon dioxide, aluminum oxide, or silicon oxycarbonitride.

Semiconductor devices 101/103/105 each include a subfin region 108. According to some embodiments, subfin region 108 comprises the same semiconductor material as substrate 102 and is adjacent to dielectric fill 106. According to some embodiments, nanoribbons 104a/104b/104c (or other semiconductor bodies) extend between source or drain regions 110a/110b/110c in the first direction to provide an active region (sometimes called channel region) for a transistor (e.g., the semiconductor region beneath the gate). It should be understood that the source or drain regions 110a/110b/110c illustrated in the cross-section of FIG. 1B are only along one side of nanoribbons 104a/104b/104c (e.g., out of the page of FIG. 1A) and that similar source or drain regions may be present along the opposite side of nanoribbons 104a/104b/104c, as shown in FIG. 1C.

According to some embodiments, the source or drain regions are epitaxial regions that are provided using an etch-and-replace process. In other embodiments the source or drain regions could be, for example, implantation-doped native portions of the semiconductor fins or substrate. Any semiconductor materials suitable for source and drain regions can be used (e.g., group IV and group III-V semiconductor materials). The composition and doping of the source or drain regions may be the same or different, depending on the polarity of the transistors. In an example, for instance, one transistor is a p-type MOS (PMOS) transistor, and the other transistor is an n-type MOS (NMOS) transistor. As such, source or drain region 110a may have a different dopant type (n or p) compared to source or drain region 110b. Any number of source or drain configurations and materials can be used.

According to some embodiments, a lower dielectric layer 112 exists beneath source or drain regions 110a/110b/110c. Lower dielectric layer 112 can include any suitable dielectric material, such as silicon dioxide or silicon nitride or silicon oxynitride and may be provided to isolate source or drain regions 110a/110b/110c from subfin regions 108. According to some embodiments, another dielectric fill 114 is provided around and over portions of source or drain regions 110a/110b/110c along the source/drain trench after epitaxial formation of the source/drain regions is complete. Accordingly, each source or drain region may be isolated from any adjacent source or drain regions by dielectric fill 114. Dielectric fill 114 may be any suitable dielectric material, although in some embodiments, dielectric fill 114 includes the same dielectric material as dielectric fill 106 or lower dielectric layer 112. In one example, each of dielectric fill 114, lower dielectric layer 112, and dielectric fill 106 includes silicon dioxide.

According to some embodiments, a gate structure extends over nanoribbons 104a/104b/104c of semiconductor devices 101/103/105 along a second direction across the page of FIG. 1A. The gate structure includes a gate dielectric 116 and a gate electrode 118. Gate dielectric 116 represents any number of dielectric layers present between nanoribbons 104a/104b/104c and gate electrode 118. Gate dielectric 116 may also be present on the surfaces of other structures within the gate trench, such as on subfin regions 108. Gate dielectric 116 may include any suitable gate dielectric material(s). In some embodiments, gate dielectric 116 includes a layer of native oxide material (e.g., silicon dioxide) on the nanoribbons or other semiconductor regions making up the channel region of the devices, and a layer of high-k dielectric material (e.g., hafnium oxide) on the native oxide.

Gate electrode 118 may represent any number of conductive layers, such as any metal, metal alloy, or doped polysilicon layers. In some embodiments, gate electrode 118 includes one or more workfunction metals around nanoribbons 104a/104b/104c. In some embodiments, one of semiconductor devices 101/103/105 is a p-channel device that includes a workfunction metal having titanium around its nanoribbons and another semiconductor device is an n-channel device that includes a workfunction metal having tungsten around its nanoribbons. Gate electrode 118 may also include a fill metal or other conductive material around the workfunction metals to provide the whole gate electrode structure.

According to some embodiments, dielectric walls 120 are present between adjacent semiconductor devices such that a first gate structure is present over nanoribbons 104a, a second gate structure is present over nanoribbons 104b, and a third gate structure is present over nanoribbons 104c. Dielectric walls 120 extend along the first direction (e.g., into and out of the page) across the gate trench and further along the source/drain trench to isolate adjacent source or drain regions from each other. Accordingly, dielectric wall 120 extends between source or drain region 110a and source or drain region 110b and also between source or drain region 110b and source or drain region 110c. Dielectric walls 120 may continue to extend in the first direction to separate any number of other devices from one another within the integrated circuit. Dielectric walls 120 extend through at least an entire thickness of the gate structures. In some examples, dielectric walls 120 also extend through an entire thickness of dielectric fill 106. Dielectric walls 120 may be formed from a sufficiently insulating material, such as a dielectric material. Example materials for dielectric walls 120 include silicon nitride, silicon oxide, or silicon oxynitride. According to some embodiments, dielectric walls 120 each has a width between about 10 nm and about 15 nm.

According to some embodiments, a first conductive contact 122a and a second conductive contact 122b may be formed on corresponding source or drain regions 110a and 110b, respectively. According to some embodiments, each of first conductive contact 122a and second conductive contact 122b includes a conductive fill and a conductive liner along outside edges of the conductive fill. The conductive fill may be any suitably conductive material such as tungsten (W). Other conductive materials may include copper (Cu), ruthenium (Ru), cobalt (Co), titanium (Ti), molybdenum (Mo), or any alloys thereof. The conductive liner may be, for instance, a barrier layer and/or resistance-reducing layer that includes titanium or tantalum (e.g., titanium nitride or tantalum nitride) or some other suitable liner layer.

According to some embodiments, a conductive arm 124 extends laterally (e.g., along the second direction) from second conductive contact 122b over source or drain region 110c without contacting source or drain region 110c. Conductive arm 124 may extend through a portion of dielectric wall 120 and over another dielectric fill 126 on a top surface of source or drain region 110c. Accordingly, dielectric fill 126 may be between source or drain region 110c and conductive arm 124. Dielectric fill 126 may be any suitable dielectric material, and may be the same dielectric material as dielectric fill 114.

According to some embodiments, second conductive contact 122b above source or drain region 110b has a first thickness t₁and conductive arm 124 extending away from second conductive contact 122b has a second thickness t₂. In some examples, the first thickness t₁is between about 30 nm and about 40 nm and the second thickness t₂is between about 10 nm and about 20 nm. More generally, the first thickness t₁may be at least 5 nm greater, or two times greater, than the second thickness t₂, according to some embodiments. Due to its smaller thickness, conductive arm 124 may extend above the adjacent source or drain region 110c without contacting it. Conductive arm 124 may extend over any other semiconductor structure or may not extend over any semiconductor structures, according to some embodiments. According to some embodiments, both second conductive contact 122b and conductive arm 124 have a planar top surface that is substantially coplanar with a top surface of dielectric walls 120 within the gate trench.

According to some embodiments, a portion of another dielectric wall 120 between first conductive contact 122a and second conductive contact 122b may be removed and replaced with a conductive plug 128. Conductive plug 128 may extend in the second direction to contact the sides of both first conductive contact 122a and second conductive contact 122b. Conductive plug 128 may have the same thickness t₂as conductive arm 124.

Each of conductive arm 124 and conductive plug 128 may include any suitable conductive material, such as tungsten, molybdenum, or other metals. According to some embodiments, conductive arm 124 and conductive plug 128 are formed together such that they include the same conductive material. The conductive material of conductive arm 124 and conductive plug 128 may be different from the conductive material of first conductive contact 122a and second conductive contact 122b.

First conductive contact 122a, second conductive contact 122b, conductive arm 124, and conductive plug 128 may collectively form a single conductive contact within the device layer that contacts multiple source or drain regions (e.g., source or drain regions 110a and 110b) and flies over another source or drain region 110c. In some embodiments, there may not be any noticeable seams or boundaries between any of first conductive contact 122a, second conductive contact 122b, conductive arm 124, or conductive plug 128 depending on the materials used. When different materials or deposition processes are used, seams or boundaries may be noticeable between different conductive elements.

According to some embodiments, a dielectric cap layer 130 runs along a top surface of the gate structures in the gate trench. Accordingly, dielectric cap layer 130 may run along the second direction on the top surface of gate electrode 118 and be interrupted by dielectric walls 120. Dielectric cap layer 130 may include the same dielectric material as dielectric walls 120, in some examples.

FIG. 1C illustrates the plan view of the integrated circuit showing how nanoribbons 104a/104b/104c extend between corresponding source or drain regions 110a/110b/110c. According to some embodiments, spacer structures 132 extend along the sides of the gate trench and isolate the gate trench from the source/drain trench (including epi regions and their respective contacts). Spacer structures 132 may include any suitable dielectric material, such as silicon nitride. The nanoribbons 104a/104b/104c (or other channel body) extend through spacer structures 132 to contact respective source or drain regions.

Fabrication Methodology

FIGS. 2A-11A and 2B-11B are cross-sectional views that collectively illustrate a first example process for forming an integrated circuit configured with a contact extended over an adjacent source or drain region, in accordance with an embodiment of the present disclosure. FIGS. 2A-11A represent cross-sectional views taken across a gate trench of the integrated circuit, while FIGS. 2B-11B represent cross-sectional views taken across the source/drain trench adjacent to the gate trench along the same direction. Each figure shows an example structure that results from the process flow up to that point in time, so the depicted structure evolves as the process flow continues, culminating in the structure shown in FIGS. 11A and 11B, which is similar to the structure shown in FIGS. 1A and 1B, respectively. Such a structure may be part of an overall integrated circuit (e.g., such as a processor or memory chip) that includes, for example, digital logic cells and/or memory cells and analog mixed signal circuitry. Thus, the illustrated integrated circuit structure may be part of a larger integrated circuit that includes other integrated circuitry not depicted. Example materials and process parameters are given, but the present disclosure is not intended to be limited to any specific such materials or parameters, as will be appreciated. Figures sharing the same number (e.g., FIGS. 2A and 2B) illustrate different views of the structure at the same point in time during the process flow. Although the fabrication of a single conductive contact is illustrated in the aforementioned figures, it should be understood that any number of similar conductive contacts can be fabricated across the integrated circuit using the same processes discussed herein.

FIGS. 2A and 2B illustrate parallel cross-sectional views taken through a stack of alternating semiconductor layers on a semiconductor substrate 102. FIG. 2A is taken across a portion of the stack that will eventually become a gate trench while FIG. 2B is taken across a portion of the stack that will eventually become a source/drain trench adjacent and parallel to the gate trench. Alternating material layers may be deposited over substrate 102 including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form GAA transistor structures. Any number of alternating semiconductor layers 204 and sacrificial layers 202 may be deposited over substrate 102.

According to some embodiments, sacrificial layers 202 have a different material composition than semiconductor layers 204. In some embodiments, sacrificial layers 202 are silicon germanium (SiGe) while semiconductor layers 204 include a semiconductor material suitable for use as a nanoribbon such as silicon (Si), SiGe, germanium, or III-V materials like indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layers 202 and in semiconductor layers 204, the germanium concentration is different between sacrificial layers 202 and semiconductor layers 204. For example, sacrificial layers 202 may include a higher germanium content compared to semiconductor layers 204. In some examples, semiconductor layers 204 may be doped with either n-type dopants (to produce a p-channel transistor) or p-type dopants (to produce an n-channel transistor).

While dimensions can vary from one example embodiment to the next, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm), and the thickness of each of semiconductor layers 204 may be about the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of sacrificial layers 202 and semiconductor layers 204 may be deposited using any known or proprietary material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

FIGS. 3A and 3B depict the cross-section views of the structure shown in FIGS. 2A and 2B, respectively, following the formation of a cap layer 302 and the subsequent formation of fins beneath cap layer 302, according to an embodiment. Cap layer 302 may be any suitable hard mask material such as a carbon hard mask (CHM) or silicon nitride. Cap layer 302 is patterned into rows to form corresponding rows of fins from the alternating layer stack of sacrificial layers 202 and semiconductor layers 204. The rows of fins extend lengthwise in a first direction (e.g., into and out of the page of each cross-section view).

According to some embodiments, an anisotropic etching process through the layer stack continues into at least a portion of substrate 102, where the unetched portions of substrate 102 beneath the fins form subfin regions 304. The etched portions of substrate 102 may be filled with a dielectric fill 306 that acts as shallow trench isolation (STI) between adjacent fins. Dielectric fill 306 may be any suitable dielectric material such as silicon dioxide, and may be recessed to a desired depth as shown (in this example case, down to around the upper surface of subfin regions 304), so as to define the active portion of the fins that will be covered by a gate structure. In some embodiments, dielectric fill 306 is recessed below the top surface of subfin regions 304.

FIGS. 4A and 4B depict the cross-section views of the structure shown in FIGS. 3A and 3B, respectively, following the formation of a sacrificial gate 402 extending across the fins in a second direction different from the first direction, according to some embodiments. Sacrificial gate 402 may extend across the fins in a second direction that is orthogonal to the first direction. According to some embodiments, the sacrificial gate material is formed in parallel strips across the integrated circuit and removed in all areas not protected by a gate masking layer. Sacrificial gate 402 may be any suitable material that can be selectively removed without damaging the semiconductor material of the fins. In some examples, sacrificial gate 402 includes polysilicon.

As seen in the cross-section views, sacrificial gate 402 extends across the fins along the gate trench cross-section of FIG. 4A but is not present along the source/drain trench cross-section of FIG. 4B. Accordingly, sacrificial gate 402 (along with any gate spacers formed on the sidewalls of sacrificial gate 402) protect the underlying portions of the fins while the exposed portions of the fins are etched away as seen in FIG. 4B. According to some embodiments, both semiconductor layers 204 and sacrificial layers 202 are etched at substantially the same rate using an anisotropic RIE process. As observed in FIG. 4B, the fins are completely removed above subfin regions 304. In some embodiments, the RIE process may also etch into subfin regions 304 thus recessing subfin regions 304 beneath a top surface of dielectric fill 306. In some embodiments, inner gate spacers can be formed after the source/drain trenches are etched and before any formation of source or drain regions. For instance, a selective etch can be used to laterally recess sacrificial layers 202, and that recess can then be filled with inner gate spacer material (e.g., silicon nitride or silicon oxynitride). Any excess gate spacer material can be removed with directional etching.

FIGS. 5A and 5B depict the cross-section views of the structure shown in FIGS. 4A and 4B, respectively, following the formation of source or drain regions 502a/502b/502c at the ends of each of the fins (extending into and out of the page in FIG. 5A), according to some embodiments. Source or drain regions 502a/502b/502c may be epitaxially grown from the exposed ends of semiconductor layers 204, such that the material grows together or otherwise merges towards the middle of the trenches between fins, according to some embodiments. Note that epitaxial growth on one semiconductor layer 204 can fully or partially merge with epitaxial growth on one or more other semiconductor layers 204 in the same vertical stack. The degree of any such merging can vary from one embodiment to the next. In the example of a PMOS device, a given source or drain region may be a semiconductor material (e.g., group IV or group III-V semiconductor materials) having a higher dopant concentration of p-type dopants compared to n-type dopants. In the example of an NMOS device, a given source or drain region may be a semiconductor material (e.g., group IV or group III-V semiconductor materials) having a higher dopant concentration of n-type dopants compared to p-type dopants. According to some embodiments, source or drain regions 502a/502b/502c grown from different semiconductor devices may be aligned along the source/drain trench in the second direction as shown in FIG. 5B.

According to some embodiments, a bottom dielectric layer 504 may be deposited prior to the formation of source or drain regions 502a/502b/502c. Bottom dielectric layer 504 may be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. Bottom dielectric layer 504 may be included to provide isolation between source or drain regions 502a/502b/502c and subfin regions 304.

According to some embodiments, another dielectric fill 506 is provided along the source/drain trench. Dielectric fill 506 may extend between adjacent ones of the source or drain regions 502a/502b/502c along the second direction and also may extend up and over each of the source or drain regions 502a/502b/502c, according to some embodiments. Accordingly, each source or drain region may be isolated from any adjacent source or drain regions by dielectric fill 506. Dielectric fill 506 may be any suitable dielectric material, although in some embodiments, dielectric fill 506 includes the same dielectric material as dielectric fill 306 or bottom dielectric layer 504. In one example, each of dielectric fill 506, bottom dielectric layer 504, and dielectric fill 306 includes silicon dioxide. Dielectric fill 506 may not be present between certain adjacent source or drain regions in situations where the adjacent source or drain regions are desired to be electrically coupled together. According to some embodiments, a top surface of dielectric fill 506 may be polished using, for example, chemical mechanical polishing (CMP). The top surface of dielectric fill 506 may be polished until it is substantially coplanar with a top surface of sacrificial gate 402.

FIGS. 6A and 6B depict the cross-section views of the structure shown in FIGS. 5A and 5B, respectively, following the formation of nanoribbons 602a/602b/602c from semiconductor layers 204, according to some embodiments. Depending on the dimensions of the structures, nanoribbons 602a/602b/602c may also be considered nanowires or nanosheets. Sacrificial gate 402 may be removed using any wet or dry isotropic process thus exposing the alternating layer stack of the fins within the trenches left behind after the removal of sacrificial gate 402. Once sacrificial gate 402 is removed, sacrificial layers 202 may also be removed using a selective isotropic etching process that removes the material of sacrificial layers 202 but does not remove (or removes very little of) semiconductor layers 204 or any other exposed layers (e.g., inner gate spacers). At this point, the suspended (sometimes called released) semiconductor layers 204 form nanoribbons 602a/602b/602c that extend in the first direction (into and out of the page) between corresponding source or drain regions 502a/502b/502c.

FIGS. 7A and 7B depict the cross-section views of the structure shown in FIGS. 6A and 6B, respectively, following the formation of a gate structure around nanoribbons 602a/602b/602c within the gate trench, according to some embodiments. As noted above, the gate structure includes a gate dielectric 702 and a gate electrode 704. Gate dielectric 702 may be conformally deposited around nanoribbons 602a/602b/602c using any suitable deposition process, such as atomic layer deposition (ALD). Gate dielectric 702 may include any suitable dielectric (such as silicon dioxide, and/or a high-k dielectric material). Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, gate dielectric 702 is hafnium oxide with a thickness between about 1 nm and about 5 nm. In some embodiments, gate dielectric 702 may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). Gate dielectric 702 may be a multilayer structure, in some examples. For instance, gate dielectric 702 may include a first layer on nanoribbons 602a/602b/602c, and a second layer on the first layer. The first layer can be, for instance, an oxide of the semiconductor layers (e.g., silicon dioxide) and the second layer can be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, an annealing process may be carried out on gate dielectric 702 to improve its quality when a high-k dielectric material is used. In some embodiments, the high-k material can be nitridized to improve its aging resistance.

Gate electrode 704 may be deposited over gate dielectric 702 and can be any conductive structure. In some embodiments, gate electrode 704 includes doped polysilicon, a metal, or a metal alloy. Example suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. Gate electrode 704 may include, for instance, one or more workfunction layers, resistance-reducing layers, and/or barrier layers. The workfunction layers can include, for example, p-type workfunction materials (e.g., titanium nitride) for PMOS gates, or n-type workfunction materials (e.g., titanium aluminum carbide) for NMOS gates.

According to some embodiments, a gate cap 706 may be formed by first recessing gate electrode 704 and filling the recess with a dielectric material. The dielectric material may then be polished such that its top surface is substantially coplanar with any adjacent spacer structures or material within the source/drain trench. Gate cap 706 may be any suitable dielectric material, such as silicon nitride.

According to some embodiments, a portion of dielectric fill 506 may be recessed within the source/drain trench to expose at least a top surface of source or drain regions 502a/502b/502c. A conductive contact 708 may be formed within the recess to contact at least the top surfaces of source or drain regions 502a/502b/502c. In some embodiments, dielectric fill 506 is recessed far enough to expose one or more side surfaces of source or drain regions 502a/502b/502c, in which case conductive contact 708 also contacts the exposed side surfaces of source or drain regions 502a/502b/502c. Conductive contact 708 may include any suitable conductive material, such as tungsten, molybdenum, or ruthenium, for making electrical contact with the underlying source or drain regions 502a/502b/502c. A top surface of conductive contact 708 may be polished to be substantially coplanar with a top surface of gate cap 706.

FIGS. 8A and 8B depict cross-section views of the structure shown in FIGS. 7A and 7B, respectively, following the formation of dielectric walls 802 extending in the first direction between adjacent devices, according to some embodiments. Dielectric walls 802 extend to a depth at least through an entire thickness of the gate structures to isolate separate gate structures along the second direction. In some embodiments, dielectric walls 802 extend into at least a portion of dielectric fill 306 or through an entire thickness of dielectric fill 306. In some embodiments, dielectric walls 802 extend entirely through dielectric fill 306 and into a portion of substrate 102.

According to some embodiments, dielectric walls 802 may be formed by first forming corresponding gate cut recesses through gate cap 706, contact 708 and gate electrode 704 using any suitable metal gate etch process that iteratively etches through portions of gate electrode 704 while simultaneously protecting the sidewalls of the recess from lateral etching to provide a high height-to-width aspect ratio recess (e.g., aspect ratio of 5:1 or higher, or 10:1 or higher). The gate cut recesses may extend in the first direction through multiple gate trenches and source/drain trenches to isolate adjacent gate structures and source or drain regions. The gate cut recesses may be filled with one or more dielectric materials to form dielectric walls 802. For example, dielectric walls 802 may include only silicon oxide or silicon nitride or silicon carbide. In some examples, dielectric walls 802 include a first dielectric layer deposited first and a second dielectric layer or dielectric fill formed on the first dielectric layer. The first dielectric layer may include a high-k dielectric material (e.g., materials with a dielectric constant higher than that of silicon oxide or higher than 3.9) while the second dielectric layer may include a low-k dielectric material (e.g. materials with a dielectric constant equal to or lower than that of silicon oxide, such as porous silicon oxide, or equal to or lower than 3.9). In the illustrated example, dielectric wall 802 separates conductive contact 708 into a first contact 708a and a second contact 708b. In some examples where devices are closely packed, dielectric walls 802 may contact one or more sidewalls of source or drain regions 502a/502b/502c.

According to some embodiments, portions of conductive contact 708 above and around source or drain region 502c may be removed and replaced with another dielectric fill 804. The removed portion of conductive contact 708 may be constrained within the adjacent dielectric walls 802 on either side of source or drain region 502c. Dielectric fill 804 may be any suitable dielectric material. In some examples, dielectric fill 804 is the same dielectric material as dielectric fill 506. A top surface of dielectric fill 804 may be polished to be substantially coplanar with a top surface of first contact 708a and a second contact 708b.

FIGS. 9A and 9B depict the cross-section views of the structure shown in FIGS. 8A and 8B, respectively, following the formation of a first recess 902 and a second recess 904, according to some embodiments. An anisotropic dielectric etching process may be performed to recess a portion of dielectric fill 804 and a portion of dielectric wall 802 between dielectric fill 804 and second contact 708b. A hard mask or other suitable masking material may be used to protect other regions of the device. Depending on the alignment of the mask, portions of both dielectric walls 802 on either side of source or drain region 502c may be recessed during the etching process. First recess 902 exposes at least a portion of the sidewall of second contact 708b. According to some embodiments, first recess 902 does not expose any portion of source or drain region 502c, such that dielectric fill 804 remains over a top surface of source or drain region 502c.

According to some embodiments, second recess 904 may also be formed between adjacent contacts. In the illustrated example, second recess 904 is formed by removing a portion of dielectric wall 802 between first contact 708a and second contact 708b. The same masking layer or masking material may be used to expose the dielectric materials along the source/drain trench, such that first recess 902 and second recess 904 are formed at the same time using the same etching process. Second recess 904 may have a similar depth as first recess 902. According to some embodiments, any number of dielectric walls 802 can have their top portion removed to form recesses between any number of contacts along a given source/drain trench.

According to some embodiments, the etching process used to form first and second recesses 902 and 904 may not be selective to the conductive material of first and second contacts 708a and 708b. In such examples, portions of first contact 708a and/or second contact 708b may also be removed when forming the recesses. In some embodiments, each of dielectric wall 802, dielectric fill 804 and second contact 708b are recessed together at substantially the same rate using a non-selective anisotropic etching process.

FIGS. 10A and 10B depict the cross-section views of the structure shown in FIGS. 9A and 9B, respectively, following the formation of a conductive arm 1002 within first recess 902 and a conductive plug 1004 within second recess 904, according to some embodiments. Conductive arm 1002 extends away from second contact 708b along the second direction and over source or drain region 502c without contacting source or drain region 502c. Conductive arm 1002 extends through dielectric wall 802 that runs between source or drain region 502b and source or drain region 502c. According to some embodiments, conductive plug 1004 extends from first contact 708a to second contact 708b along the second direction. Each of conductive arm 1002 and conductive plug 1004 may include any suitable conductive material, such as tungsten, molybdenum, or other metals. In some examples, conductive arm 1002 and conductive plug 1004 includes the same conductive material as first contact 708a and second contact 708b. According to some embodiments, conductive arm 1002 and conductive plug 1004 are formed together such that they include the same conductive material. The conductive material of conductive arm 1002 and conductive plug 1004 may be different from the conductive material of first contact 708a and second contact 708b.

First contact 708a, second contact 708b, conductive arm 1002, and conductive plug 1004 may collectively form a single conductive contact within the device layer that contacts multiple source or drain regions (e.g., 502a and 502b) and flies over at least one other source or drain region (e.g., 502c). Additional adjacent source or drain regions along the same source/drain trench may also be contacted by forming additional conductive plugs across adjacent dielectric walls 802. In some embodiments, there may not be any noticeable seams or boundaries between any of first contact 708a, second contact 708b, conductive arm 1002, or conductive plug 1004 depending on the materials used. When different materials or deposition processes are used, seams or boundaries may be noticeable between different conductive elements.

FIGS. 11A and 11B depict the cross-section views of the structure shown in FIGS. 10A and 10B, respectively, following the formation of an interconnect layer over the structure, according to some embodiments. The interconnect layer may be a first interconnect layer of an interconnect structure that includes any number of stacked interconnect layers, with each interconnect layer including any number and arrangement of conductive vias and conductive traces. According to an embodiment, the illustrated interconnect layer includes a dielectric layer 1102 and a conductive via 1104 through dielectric layer 1102.

Dielectric layer 1102 may be any suitable dielectric material, such as silicon dioxide. Conductive via 1104 may include the same conductive material as conductive arm 1002 and/or any of conductive contacts 708a/708b. In one example, conductive via 1104 includes tungsten. According to some embodiments, conductive via 1104 contacts conductive arm 1002, such that conductive via 1104 is not located directly over source or drain region 502a or over source or drain region 502b. Accordingly, the combined conductive contact may be used to route signal or power between source or drain region 502a and/or source or drain region 502b and conductive via 1104 where conductive via 1104 is not located directly above source or drain region 502a or source or drain region 502b. In some examples, conductive via 1104 is located directly above source or drain region 502c or directly above another semiconductor structure, or above no semiconductor structures.

FIG. 12 illustrates an example embodiment of a chip package 1200, in accordance with an embodiment of the present disclosure. As can be seen, chip package 1200 includes one or more dies 1202. One or more dies 1202 may include at least one integrated circuit having semiconductor devices, such as any of the semiconductor devices disclosed herein. One or more dies 1202 may include any other circuitry used to interface with other devices formed on the dies, or other devices connected to chip package 1200, in some example configurations.

As can be further seen, chip package 1200 includes a housing 1204 that is bonded to a package substrate 1206. The housing 1204 may be any housing, and may provide, for example, electromagnetic shielding and environmental protection for the components of chip package 1200. The one or more dies 1202 may be conductively coupled to a package substrate 1206 using connections 1208, which may be implemented with any number of connection mechanisms, such as solder bumps, ball grid array (BGA), pins, or wire bonds, to name a few examples. Package substrate 1206 may be any package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between the faces of package substrate 1206, or between different locations on each face. In some embodiments, package substrate 1206 may have a thickness less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of package geometries can be used. Additional conductive contacts 1212 may be disposed at an opposite face of package substrate 1206 for conductively contacting, for instance, a printed circuit board (PCB). One or more vias 1210 extend through a thickness of package substrate 1206 to provide conductive pathways between one or more of connections 1208 to one or more of contacts 1212. Vias 1210 are illustrated as single straight columns through package substrate 1206 for ease of illustration, although other configurations can be used (e.g., damascene, dual damascene, through-silicon via, or an interconnect structure that meanders through the thickness of substrate 1206 to contact one or more intermediate locations therein). In still other embodiments, vias 1210 are fabricated by multiple smaller stacked vias, or are staggered at different locations across package substrate 1206. In the illustrated embodiment, contacts 1212 are solder balls (e.g., for bump-based connections or a ball grid array arrangement), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). In some embodiments, a solder resist is disposed between contacts 1212, to inhibit shorting.

In some embodiments, a mold material 1214 may be disposed around the one or more dies 1202 included within housing 1204 (e.g., between dies 1202 and package substrate 1206 as an underfill material, as well as between dies 1202 and housing 1204 as an overfill material). Although the dimensions and qualities of the mold material 1214 can vary from one embodiment to the next, in some embodiments, a thickness of mold material 1214 is less than 1 millimeter. Example materials that may be used for mold material 1214 include epoxy mold materials, as suitable. In some cases, the mold material 1214 is thermally conductive, in addition to being electrically insulating.

Methodology

FIG. 13 is a flow chart of a method 1300 for forming at least a portion of an integrated circuit, according to an embodiment. Various operations of method 1300 may be illustrated in FIGS. 2A-11A and FIGS. 2B-11B. However, the correlation of the various operations of method 1300 to the specific components illustrated in the aforementioned figures is not intended to imply any structural and/or use limitations. Rather, the aforementioned figures provide one example embodiment of method 1300. Other operations may be performed before, during, or after any of the operations of method 1300. For example, method 1300 does not explicitly describe all processes that are performed to form common transistor structures. Some of the operations of method 1300 may be performed in a different order than the illustrated order.

Method 1300 begins with operation 1302 where any number of parallel semiconductor fins are formed, according to some embodiments. The semiconductor material in the fins may be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed of material deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In another such example, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitates forming of nanowires and nanoribbons during a gate forming process where one type of the alternating layers are selectively etched away so as to liberate the other type of alternating layers within the channel region, so that a gate-all-around (GAA) process can then be carried out. The alternating layers can be blanket deposited and then etched into fins, or deposited into fin-shaped trenches. The fins may also include a cap structure over each fin that is used to define the locations of the fins during, for example, an RIE process. The cap structure may be a dielectric material, such as silicon nitride.

According to some embodiments, a dielectric layer is formed around subfin portions of the one or more fins. In some embodiments, the dielectric layer extends between each pair of adjacent parallel fins and runs lengthwise in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate and the dielectric layer may be formed within the recessed portions of the substrate. Accordingly, the dielectric layer acts as shallow trench isolation (STI) between adjacent fins. The dielectric layer may be any suitable dielectric material, such as silicon dioxide.

Method 1300 continues with operation 1304 where a sacrificial gate and spacer structures are formed over the fins. The sacrificial gate may be patterned using a gate masking layer in a strip that runs orthogonally over the fins (many gate masking layers and corresponding sacrificial gates may be formed parallel to one another (e.g., forming a cross-hatch pattern with the fins). The gate masking layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate may be formed from any suitable material that can be selectively removed at a later time without damaging the semiconductor material of the fins. In one example, the sacrificial gate includes polysilicon. The spacer structures may be deposited and then etched back such that the spacer structures remain mostly only on sidewalls of any exposed structures. According to some embodiments, the spacer structures may be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

Method 1300 continues with operation 1306 where source or drain regions are formed at the ends of the semiconductor regions of each of the fins. Any portions of the fins not protected by the sacrificial gate and spacer structures may be removed using, for example, an anisotropic etching process followed by the epitaxial growth of the source or drain regions from the exposed ends of the semiconductor layers in the fins. In some example embodiments, the source or drain regions are NMOS source or drain regions (e.g., epitaxial silicon) or PMOS source or drain regions (e.g., epitaxial SiGe).

Method 1300 continues with operation 1308 where a first dielectric fill is formed over the source or drain regions. The first dielectric fill may be formed adjacent to the various source or drain regions for additional electrical isolation between adjacent regions. The first dielectric fill may also extend over a top surface of the source or drain regions. The first dielectric fill can take up any remaining space along the source/drain trench, according to some embodiments. The first dielectric fill may include any suitable dielectric material, such as silicon dioxide or silicon oxynitride.

Method 1300 continues with operation 1310 where the sacrificial gate is replaced with a gate structure. According to some embodiments, the sacrificial gate may be removed along with any sacrificial layers within the exposed fins between the spacer structures (in the case of GAA structures). A gate structure may then be formed in place of the sacrificial gate. The gate structure may include both a gate dielectric and a gate electrode. The gate dielectric is first formed over the exposed semiconductor regions between the spacer structures followed by forming the gate electrode within the remainder of the trench between the spacer structures, according to some embodiments. The gate dielectric may include any number of dielectric layers deposited using a CVD process, such as ALD. The gate electrode can include any conductive material, such as a metal, metal alloy, or polysilicon. The gate electrode may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name a few examples.

Method 1300 continues with operation 1312 where a first contact is formed over a first source or drain region and a second contact is formed over an adjacent source or drain region. In some embodiments, a conductive layer forms both the first and second contacts within the source/drain trench, such that they are coupled together. The conductive layer may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, or cobalt. The conductive layer represents any number of different conductive materials that may be deposited to form the contacts.

Method 1300 continues with operation 1314 where a dielectric wall is formed through the gate structure between adjacent pairs of fins and through the source/drain trench between the first source or drain region and the second source or drain region. According to some embodiments, the dielectric wall also cuts through the conductive layer to isolate separate contacts on each of the first source or drain region and the second source or drain region. A trench may be etched through both the gate structure and through the dielectric fill around the source or drain regions. The trench may extend substantially parallel and lengthwise to the fins or nanowires. A single etching process may be used to form multiple trenches between adjacent devices using a mask with a grating pattern. A reactive ion etching (RIE) process may be used to cut through the various material layers and form the trenches. The trench may be filled with a dielectric material to form the dielectric wall between the first source or drain region and the second source or drain region. The trench may be filled with any suitable low-K dielectric material, such as silicon nitride. In some embodiments, each pair of semiconductor devices in the integrated circuit includes a dielectric wall between them.

Method 1300 continues with operation 1316 where the second contact is removed and replaced with a second dielectric fill on the second source or drain region. The second contact may be constrained within adjacent dielectric walls on either side of the second source or drain region. The second dielectric fill may be any suitable dielectric material. In some examples, the second dielectric fill is the same dielectric material as the first dielectric fill. A top surface of the second dielectric fill may be polished to be substantially coplanar with a top surface of the first contact on the first source or drain region.

Method 1300 continues with operation 1318 where a recess is formed adjacent to the first contact and through a portion of the dielectric wall and second dielectric fill. An anisotropic etching process may be used to form the recess through the dielectric materials of the dielectric wall and second dielectric fill. According to some embodiments, the recess has a depth that does not expose any portion of the second source or drain region beneath the second dielectric fill. According to some embodiments, the recess exposes a portion of a sidewall of the first conductive contact.

Method 1300 continues with operation 1320 wherein a conductive material is formed within the recess. The conductive material may be tungsten or any other suitable metal, such as ruthenium, cobalt, titanium, molybdenum, or any alloys thereof. According to some embodiments, a top surface of the conductive material is polished using, for example, CMP until it is substantially coplanar with a top surface of the first contact in the source/drain trench. According to some embodiments, the conductive material extends from the first contact along the source/drain trench and over the second source or drain region without contacting any portion of the second source or drain region. A conductive via within an interconnect layer may be formed on the conductive material, according to some embodiments.

Example System

FIG. 14 is an example computing system implemented with one or more of the integrated circuit structures as disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 1400 houses a motherboard 1402. The motherboard 1402 may include a number of components, including, but not limited to, a processor 1404 and at least one communication chip 1406, each of which can be physically and electrically coupled to the motherboard 1402, or otherwise integrated therein. As will be appreciated, the motherboard 1402 may be, for example, any printed circuit board (PCB), whether a main board, a daughterboard mounted on a main board, or the only board of system 1400, etc.

Depending on its applications, computing system 1400 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1402. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1400 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment (e.g., a module including an integrated circuit on a substrate, the substrate having semiconductor devices that include a contact extended over an adjacent source or drain region). In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1406 can be part of or otherwise integrated into the processor 1404).

The communication chip 1406 enables wireless communications for the transfer of data to and from the computing system 1400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1406 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1400 may include a plurality of communication chips 1406. For instance, a first communication chip 1406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1404 of the computing system 1400 includes an integrated circuit die packaged within the processor 1404. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more semiconductor devices as variously described herein. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1406 also may include an integrated circuit die packaged within the communication chip 1406. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 1404 (e.g., where functionality of any chips 1406 is integrated into processor 1404, rather than having separate communication chips). Further note that processor 1404 may be a chip set having such wireless capability. In short, any number of processor 1404 and/or communication chips 1406 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1400 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

It will be appreciated that in some embodiments, the various components of the computing system 1400 may be combined or integrated in a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components or any suitable combination of hardware, firmware or software.

FURTHER EXAMPLE EMBODIMENTS

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit that includes a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region, a dielectric wall extending in the first direction through an entire thickness of the gate structure and extending in the first direction adjacent to the source or drain region, and a conductive contact on at least a top surface of the source or drain region. The conductive contact has a first section directly above the source or drain region and a second section extending away from the source or drain region along the second direction and through a portion of the dielectric wall.

Example 2 includes the integrated circuit of Example 1, wherein the first section has a first thickness and the second section has a second thickness, the first thickness being greater than the second thickness.

Example 3 includes the integrated circuit of Example 1 or 2, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons.

Example 4 includes the integrated circuit of Example 3, wherein the plurality of semiconductor nanoribbons comprise germanium, silicon, or a combination thereof.

Example 5 includes the integrated circuit of any one of Examples 1-4, wherein a top surface of the first section of the conductive contact is substantially coplanar with a top surface of the second section of the conductive contact.

Example 6 includes the integrated circuit of any one of Examples 1-5, wherein the source or drain region is a first source or drain region and the second section of the conductive contact extends over a second source or drain region from an adjacent semiconductor device, the second section of the conductive contact not contacting the second source or drain region.

Example 7 includes the integrated circuit of Example 6, wherein the dielectric wall extends between the first source or drain region and the second source or drain region.

Example 8 includes the integrated circuit of Example 6 or 7, further comprising a dielectric layer between a top surface of the second source or drain region and the second section of the conductive contact.

Example 9 includes the integrated circuit of any one of Examples 1-8, further comprising a conductive via that contacts a top surface of the second section of the conductive contact.

Example 10 includes the integrated circuit of any one of Examples 1-9, wherein both the first and second sections of the conductive contact comprise a conductive liner and a conductive fill.

Example 11 is a printed circuit board comprising the integrated circuit of any one of Examples 1-10.

Example 12 is an electronic device that includes a chip package having one or more dies. At least one of the one or more dies includes a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction over the semiconductor region, a dielectric wall extending in the first direction through an entire thickness of the gate structure and extending in the first direction adjacent to the source or drain region, and a conductive contact on at least a top surface of the source or drain region. The conductive contact has a first section directly above the source or drain region and a second section extending away from the source or drain region along the second direction and through a portion of the dielectric wall such that the source or drain region is not below the second section.

Example 13 includes the electronic device of Example 12, wherein the first section has a first thickness and the second section has a second thickness, the first thickness being greater than the second thickness.

Example 14 includes the electronic device of Example 12 or 13, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons.

Example 15 includes the electronic device of Example 14, wherein the plurality of semiconductor nanoribbons comprise germanium, silicon, or a combination thereof.

Example 16 includes the electronic device of any one of Examples 12-15, wherein a top surface of the first section of the conductive contact is substantially coplanar with a top surface of the second section of the conductive contact.

Example 17 includes the electronic device of any one of Examples 12-16, wherein the source or drain region is a first source or drain region and the second section of the conductive contact extends over a second source or drain region from an adjacent semiconductor device.

Example 18 includes the electronic device of Example 17, wherein the dielectric wall extends between the first source or drain region and the second source or drain region.

Example 19 includes the electronic device of Example 17 or 18, wherein the at least one of the one or more dies further comprises a dielectric layer between a top surface of the second source or drain region and the second section of the conductive contact.

Example 20 includes the electronic device of any one of Examples 12-19, wherein the at least one of the one or more dies further comprises a conductive via that contacts a top surface of the second section of the conductive contact.

Example 21 includes the electronic device of any one of Examples 12-20, wherein both the first and second sections of the conductive contact comprise a conductive liner and a conductive fill.

Example 22 includes the electronic device of any one of Examples 12-21, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.

Example 23 is a method of forming an integrated circuit. The method includes forming a fin comprising semiconductor material, the fin extending above a substrate and extending in a first direction; forming a source or drain region at one end of the fin; forming a gate electrode extending in a second direction over the semiconductor material; forming a dielectric fill extending in the second direction over the source or drain region; forming a first recess through an entire thickness of the gate electrode, the recess extending in the first direction such that the first recess is also formed adjacent to the source or drain region; forming a dielectric material within the first recess; forming a second recess through the dielectric fill and over the source or drain region; forming a first conductive material in the second recess; forming a third recess through a portion of the first conductive material, through a portion of the dielectric material, and through a portion of the dielectric fill adjacent to the dielectric material; and forming a second conductive material in the third recess.

Example 24 includes the method of Example 23, wherein the second conductive material extends away from the first conductive material along the second direction such that the source or drain region is not below a portion of the second conductive material.

Example 25 includes the method of Example 24, further comprising forming a conductive via on the portion of the second conductive material.

Example 26 includes the method of any one of Examples 23-25, wherein forming the first conductive material comprises forming a conductive liner within the second recess and forming a conductive fill on the conductive liner.

Example 27 includes the method of any one of Examples 23-26, further comprising polishing a top surface of the second conductive material using chemical mechanical polishing (CMP).

Example 28 is an integrated circuit that includes a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region located in a source/drain trench, and a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region located in the source/drain trench. The second source or drain region is adjacent to the first source or drain region within the source/drain trench along a second direction orthogonal to the first direction. The integrated circuit further includes a dielectric wall extending in the first direction between the first source or drain region and the second source or drain region and extending beyond the source/drain trench in the first direction, and a conductive contact on at least a top surface of the first source or drain region. The conductive contact has a first section directly above the first source or drain region and a second section extending away from the first section along the second direction and through a portion of the dielectric wall such that the second section extends over, but does not contact, the second source or drain region.

Example 29 includes the integrated circuit of Example 28, wherein the first section has a first thickness and the second section has a second thickness, the first thickness being greater than the second thickness.

Example 30 includes the integrated circuit of Example 28 or 29, wherein the first semiconductor region and the second semiconductor region comprise a plurality of semiconductor nanoribbons.

Example 31 includes the integrated circuit of Example 30, wherein the plurality of semiconductor nanoribbons comprise germanium, silicon, or a combination thereof.

Example 32 includes the integrated circuit of any one of Examples 28-31, wherein a top surface of the first section of the conductive contact is substantially coplanar with a top surface of the second section of the conductive contact.

Example 33 includes the integrated circuit of any one of Examples 28-32, wherein the first semiconductor device comprises a first gate structure extending in the second direction over the first semiconductor region, and the second semiconductor device comprises a second gate structure extending in the second direction over the second semiconductor region.

Example 34 includes the integrated circuit of Example 33, wherein the dielectric wall extends in the first direction between the first gate structure and the second gate structure.

Example 35 includes the integrated circuit of any one of Examples 28-34, further comprising a dielectric layer between a top surface of the second source or drain region and the second section of the conductive contact.

Example 36 includes the integrated circuit of any one of Examples 28-35, further comprising a conductive via that contacts a top surface of the second section of the conductive contact.

Example 37 includes the integrated circuit of any one of Examples 28-36, wherein both the first and second sections of the conductive contact comprise a conductive liner and a conductive fill.

Example 38 is a printed circuit board comprising the integrated circuit of any one of Examples 28-37.

The foregoing description of the embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto.

CONTACT EXTENDED OVER AN ADJACENT SOURCE OR DRAIN REGION

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