This application relates generally to non-volatile semiconductor memories of the flash memory type, their formation, structure and use.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, USB drives, embedded memory, and Solid State Drives (SSDs) which use an array of flash EEPROM cells. An example of a flash memory system is shown in
One popular flash EEPROM architecture utilizes a NAND array, wherein a large number of strings of memory cells are connected through one or more select transistors between individual bit lines and a reference potential. A portion of such an array is shown in plan view in
The top and bottom of the string connect to the bit line and a common source line respectively through select transistors (source select transistor and drain select transistor). Select transistors do not contain floating gates and are used to connect NAND strings to control circuits when they are to be accessed, and to isolate them when they are not being accessed.
NAND strings are generally connected by conductive lines in order to form arrays that may contain many NAND strings. At either end of a NAND string a contact area may be formed by appropriately doping a portion of the substrate. This allows connection of the NAND string as part of the array. Metal contacts may be formed over contact areas to connect the contact areas (and thereby connect NAND strings) to conductive metal lines that extend over the memory array (e.g. bit lines).
Thus, there is a need for a memory chip manufacturing process that forms contact holes for contacting NAND strings with very small dimensions, and that allows good control of contact hole formation.
In some integrated circuits, such as NAND flash memories, misalignment of contact plugs with active areas in a substrate may have negative consequences including current leakage and open connections. Contact hole bending may also result in such problems. Portions of dielectric material located over STI structures may block contact holes that extend towards neighboring active areas and may constrain them to an intended active area. Such portions of dielectric material may be formed of different material to the surrounding material so that they are not significantly affected by contact holes formed using selective etching. For example, silicon nitride portions in silicon oxide allow selective etching of silicon oxide that is constrained by the silicon nitride portions. Portions of silicon nitride may be self-aligned with a pattern of STI structures and active areas by recessing STI structures, depositing a liner layer (e.g. silicon oxide), and subsequently forming silicon nitride portions in the lined recesses. Alternatively, portions of silicon nitride may be formed in holes in a relatively thin lower silicon oxide layer, with holes aligned with active areas and subsequently covered by a thicker upper silicon oxide layer.
An example of a NAND flash memory includes: a plurality of active areas in a semiconductor substrate; a plurality of shallow trench isolation structures in the semiconductor substrate between the plurality of active areas; a first dielectric layer formed of a first material extending over the substrate; a plurality of portions of a second material extending over the plurality of shallow trench isolation structures; a second dielectric layer formed of the first material extending over the first dielectric layer and over the plurality of portions; and a plurality of contact holes extending through the first and second dielectric layers at locations over the plurality of active areas in the semiconductor substrate.
An individual contact hole may be constrained by a portion of the second material where the contact hole extends in a direction that is not perpendicular to a primary surface of the semiconductor substrate, or where the contact hole is misaligned with a corresponding active area. A plurality of metal contacts may be formed in the plurality of contact holes. The plurality of metal contacts may form electrical connections with bit lines that extend over the semiconductor substrate. The plurality of shallow trench isolation structures may have upper surfaces that are lower than upper surfaces of the plurality of active areas with trenches over shallow trench isolation structures lined by the first dielectric layer and the plurality of portions of the second material may fill central portions of the trenches. The plurality of portions of the second material may have upper surfaces that are higher than the upper surfaces of the plurality of active areas and may have lower surfaces that are lower than the upper surfaces of the plurality of active areas. The plurality of shallow trench isolation structures may have upper surfaces that are approximately level with upper surfaces of the plurality of active areas and the plurality of portions of the second material may have lower surfaces that are substantially level with the upper surfaces of the plurality of shallow trench isolation structures and the plurality of active areas. The plurality of portions of the second material may be located over peripheral areas of shallow trench isolation structures. The plurality of portions of the second material may extend partially over boundaries between shallow trench isolation structures and active areas to overlie peripheral areas of active areas. The plurality of portions of the second material may extend in a vertical direction and may be connected to a layer of the second material. The first material may be silicon oxide, and the second material may be silicon nitride. An individual active area may have a lateral dimension of less than thirty nanometers (30 nm) and the contact holes may have a vertical dimension of greater than four hundred nanometers (400 nm).
An example of a method of forming contact holes through a dielectric layer includes: forming alternating active areas and shallow trench isolation structures in a substrate, the shallow trench isolation structures having upper surfaces that are lower than upper surfaces of the active areas; depositing a first dielectric layer over the substrate, the first dielectric layer formed of a first dielectric material; subsequently depositing a second dielectric material over the first dielectric layer, subsequently removing excess second dielectric material to leave portions of the second dielectric material over the shallow trench isolation structures; subsequently depositing a second dielectric layer, the second dielectric layer formed of the first dielectric material; subsequently forming an etch mask to define contact hole openings in the first dielectric material at locations over active areas; and subsequently etching a plurality of contact holes in the first and second dielectric layers, the plurality of contact holes etched by a process that etches the first dielectric material at a first etch rate and etches the second dielectric material at a second etch rate, the first etch rate being significantly higher than the second etch rate.
Forming the alternating active areas and shallow trench isolation structures may include lowering the upper surfaces of the shallow trench isolation structures by etching. The first material may be silicon oxide, the second material may be silicon nitride, and the etching may be anisotropic etching with a high silicon oxide etch rate. Removing excess second dielectric material may include planarizing to remove all of the second dielectric material that is not within trenches formed between active areas lined by the first dielectric layer. The method may also include: forming one or more additional dielectric layers over the second dielectric layer, the etch mask subsequently formed over the one or more additional dielectric layers, and the plurality of contact holes etched through the one or more additional dielectric layers.
An example of a method of forming contact holes through a dielectric layer includes: forming alternating active areas and shallow trench isolation structures in a substrate; depositing a first dielectric layer over the substrate, the first dielectric layer formed of a first dielectric material; subsequently forming a plurality of openings through the first dielectric layer over the active areas thereby exposing the active areas; subsequently depositing a second dielectric material over the first dielectric layer and within the openings; subsequently depositing a second dielectric layer, the second dielectric layer formed of the first dielectric material; subsequently forming an etch mask to define contact hole openings in the second dielectric layer at locations over active areas; and subsequently etching a plurality of contact holes in the first and second dielectric layers, the plurality of contact holes etched by a process that etches the first dielectric material at a first etch rate and etches the second dielectric material at a second etch rate, the first etch rate being significantly higher than the second etch rate.
Upper surfaces of active areas and shallow trench isolation structures may be coplanar, the first dielectric layer may be substantially planar, and the second dielectric may be deposited along inner walls of the openings and along an upper surface of the first dielectric layer. The method may also include: removing the second dielectric along the upper surface of the first dielectric layer and along the active area prior to deposition of the second dielectric layer. The second dielectric material may form an etch-stop layer, and the etching may include a first etch stage that etches through the first material and a second etch stage that etches through the second dielectric material to expose the active area.
Various aspects, advantages, features and embodiments are included in the following description of examples, which description should be taken in conjunction with the accompanying drawings.
Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
In other embodiments, types of memory other than the two dimensional and three dimensional exemplary structures described here may be used.
An example of a prior art memory system, which may be modified to include various structures described here, is illustrated by the block diagram of
The data stored in the memory cells are read out by the column control circuit 2 and are output to external I/O lines via an I/O line and a data input/output buffer 6. Program data to be stored in the memory cells are input to the data input/output buffer 6 via the external I/O lines, and transferred to the column control circuit 2. The external I/O lines are connected to a controller 9. The controller 9 includes various types of registers and other memory including a volatile random-access-memory (RAM) 10.
The memory system of
As memory dimensions get smaller, some problems may be encountered when forming contact holes for electrical connection to NAND strings. In general, as such contact holes become narrower, and their cross sectional area (in plan view) becomes smaller, they become harder to control. For example, alignment of very small features may be difficult because tolerance for alignment is generally reduced as feature sizes shrink.
In addition to alignment error, narrow high-aspect ratio contact holes on at least some areas of a substrate such as a silicon wafer may not extend perpendicularly to the substrate surface. Instead, such contact holes may bend to one side, deviating from perpendicular, as they go down through a dielectric layer. This may be related to their location on a substrate or other factors. For example, memory holes in dies near the edge of a substrate may tend to bend significantly because of nonuniform etching conditions. This may become more severe over time as a process kit becomes worn (e.g. contact hole bending may only become significant after a number of substrates have been processed in a given etch chamber and only in certain areas of a substrate surface). Magnetic fields, electric fields, gas flows, temperature profiles, and other process parameters may vary across a wafer and over time. Such variation may provide at least some contact hole bending on at least some dies for at least some period of time. In general, the effects of contact hole bending are worse as contact hole aspect ratios increase (where aspect ratio is the ratio of contact hole height to width). In order to maintain adequate electrical isolation, dielectric layer thicknesses may not be reduced proportionally as lateral dimensions are reduced so that aspect ratios may tend to increase as technology moves to smaller dimensions.
The structure of
Dielectric portion 629b can be seen to have a width, W1, that is determined by the width of the STI structure, W2, and the thickness of the first dielectric layer, D1 (W1=W2−2*D1). By choosing a suitable value for D1, width W1 can be chosen to maintain a minimum distance between contact plugs and neighboring active areas that ensures little or no leakage current. The vertical dimensions of dielectric portions such as portion 629b may also be selected according to requirements. Dielectric portions have upper surfaces at level L1, which is higher than upper surfaces of active areas at level L2. Lower surfaces of dielectric portions are lower than L2 at level L3. Level L3 may be established by etching recesses to an appropriate depth. Level L1 may be established by planarizing down to level L1. Contact hole 641 is subsequently filled with metal (and barrier layer(s) as appropriate) so that the resulting contact plug has the dimensions of contact hole.
While the example of
Another example of a process for forming a NAND flash memory is shown in
Variations on the above described steps may be carried out in a number of ways.
Dielectric portions are not limited to overlying STI structures. In some cases, dielectric portions may partially or completely overlie active areas.
Although the various aspects have been described with respect to examples, it will be understood that protection within the full scope of the appended claims is appropriate.