Patent Application
20200373410
The disclosed subject matter relates generally to methods of forming semiconductor devices and, more particularly, to methods of forming contact structures over an active region of a semiconductor device and the resulting semiconductor devices therefrom.
Technological advances in the semiconductor integrated circuit (IC) industry have brought tremendous device miniaturization, along with performance improvements. Scaling is critical to obtain higher performance speed in IC devices, resulting in higher device density and smaller sized IC devices. Conventional IC processing requires forming contacts to the various features of an IC device. There are several challenges in fabricating contacts for use with increasingly smaller features.
One of the challenges of fabricating IC contacts is ensuring that gate contacts are not electrically short-circuited to neighboring source/drain regions within an active region. As a result of technology scaling, gate structures are formed increasingly closer to each other, and the gate-to-gate spacing becomes so narrow that a minor misalignment for the gate contact may electrically short the gate contact to the neighboring source/drain region. As a result, conventional IC designs require the gate contacts to be placed over isolation regions, away from the active regions. Placing gate contacts over the isolation regions creates a longer gate transporting length and a higher gate resistance that may be undesirable for some IC devices whose performances are sensitive to gate resistance.
For the reasons described above, there is a need to devise methods of forming contact structures over an active region of a semiconductor device and the resulting semiconductor devices having such contact structures.
To achieve the foregoing and other aspects of the present disclosure, methods of forming contact structures over an active region of a semiconductor device and the resulting semiconductor devices are presented.
According to an aspect of the disclosure, a method of fabricating a semiconductor device is provided that includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch. The plurality of first gate structures traverse across a first set of fins. A plurality of second gate structures are formed having a second gate pitch traversing across a second set of fins. The second gate pitch is wider than the first gate pitch. A plurality of epitaxial regions are formed in spaces between adjacent second gate structures in each of the traversed second set of fins. A dielectric layer is deposited over the plurality of second gate structures and the plurality of epitaxial regions. A plurality of contact openings are formed in the dielectric layer and at least one of the contact openings is formed over the second gate structure at a location where the second gate structure traverses across the second set of fins. The plurality of contact openings are filled with a conductive material to form a plurality of contact structures electrically coupled to the second gate structures.
According to another aspect of the disclosure, a method of fabricating a semiconductor device is provided that includes providing a plurality of fins over a substrate and forming a plurality of first gate structures having a first gate pitch. The plurality of first gate structures traverse across a first set of fins. A plurality of second gate structures are formed having a second gate pitch traversing across a second set of fins. The second gate pitch is wider than the first gate pitch. A plurality of epitaxial regions are formed in spaces between adjacent second gate structures on each of the traversed second set of fins. A dielectric layer is deposited over the plurality of second gate structures and the plurality of epitaxial regions. A plurality of discrete contact openings are etched in the dielectric layer to form a plurality of first contact openings. Each of the first contact openings is formed over each of the second gate structures at a location where the second gate structure traverses across one of the second set of fins. The plurality of first contact openings are filled with a conductive material to form a plurality of first contact structures electrically connected to the second gate structures.
According to yet another aspect of the disclosure, a semiconductor device is provided that includes a substrate, a plurality of fins, a plurality of first gate structures, a plurality of second gate structures, a plurality of epitaxial regions, and a first contact structure. The plurality of first gate structures and the plurality of second gate structures traverse across the plurality of fins. The plurality of first gate structures have a first gate pitch and the plurality of second gate structures have a second gate pitch, with the second gate pitch being wider than the first gate pitch. A plurality of epitaxial regions are formed in each of the fins, wherein the epitaxial regions are interposed between adjacent second gate structures. A first contact structure is positioned over each of the second gate structures traversing across at least one of the plurality of fins. The first contact structure is electrically coupled to at least one of the plurality of second gate structure.
The embodiments of the present disclosure will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawings:
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the disclosure. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the disclosure. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.
Various embodiments of the disclosure are described below. The embodiments disclosed herein are exemplary and not intended to be exhaustive or limiting to the disclosure.
The present disclosure relates to methods of forming contact structures over an active region of a semiconductor device and the resulting semiconductor devices. It is understood that the following disclosure is not limited to any particular type of semiconductor devices. The method disclosed herein may be applied to any type of semiconductor devices, such as tri-gate field effect transistor (FET) devices, fin-type FET (FinFET) devices or planar-type metal-oxide-semiconductor FET (MOSFET) devices.
The semiconductor device may be fabricated with a gate-first, a gate-last or a hybrid fabrication process. In a gate-first process, conductive layers are formed over active regions and patterned to form gate structures. This is followed by conventional complementary metal-oxide-semiconductor (CMOS) processing, including formation of source and drain regions, formation of spacers and deposition of inter-level dielectric (ILD) material. In a gate-last process, dummy gate structures are formed followed by conventional CMOS processing including formation of the source and drain regions, formation of spacers and deposition of ILD material. Thereafter, the dummy gate structures are removed followed by conventional formation of replacement gate structures. In the hybrid fabrication process, a gate structure of one type of device may be formed first and a gate structure of another type of device may be formed last.
Aspects of the disclosure are now described in detail with accompanying drawings. It is noted that like and corresponding elements are referred to by the use of the same reference numerals. However, it is noted that specific elements may be denoted by a reference numeral and a subscript, for example 108a, 108b, etc. When those elements are referred to generically, merely the reference numerals are used, for example 108, 206, etc.
The contact structures 108a are formed over the gate structures 104 and the contact structures 108b are formed over the interconnect structures 106. The contact structures 108a provide electrical contact to the gate structures 104. The contact structures 108a may be in a form of a discrete contact structure, i.e., individual contact structures having a generally square-like or cylindrical shape that typically couple to one active region 102. The contact structures 108b are electrically coupled to the epitaxial regions through the interconnect structures 106. The contact structures 108b may be in a form of line-type contact structures that typically traverse across at least two active regions 102 of the semiconductor device 100.
The interconnect structures 206a are formed over the gates structures 204 and the interconnect structures 206b are formed over the epitaxial regions traversing across the array active regions 102. The contact structures 208 are formed over the interconnect structures 206. The interconnect structures 206a provide electrical contact between the gate structures 204 and the contact structures 208a, and the interconnect structures 206b provide electrical contact between the epitaxial regions and the contact structures 208b, respectively. The contact structures 208 may be all line-type contact structures that typically traverse across at least two active regions 202 of the semiconductor device 200, without the use of any discrete contact structures.
While the active regions (102 and 202, respectively) are represented as fins in the accompanying drawings, it is understood that the fin is used only as a non-limiting example of the active regions (102 and 202, respectively), and other active regions (e.g., a doped layer on a top surface of a bulk semiconductor substrate or a semiconductor-on-insulator layer) may be used as well. It should also be understood that the present disclosure can be applied to any type of transistor device architecture, such as a three-dimensional device architecture (e.g., FinFETs), or a planar device architecture (e.g., complementary metal oxide semiconductor (CMOS) devices), semiconductor-on-insulator (SOI) devices). In this embodiment of the present disclosure, the active regions 102 and 202 are preferably fins of FinFET semiconductor devices. Furthermore, those skilled in the art would recognize, after a complete reading of the disclosure, the number and placement locations of the active regions (102 and 202, respectively), the gate structures (104 and 204, respectively), the interconnect structures (106 and 206, respectively) and the contact structures (108 and 208, respectively) may vary according to the specific designs of the semiconductor devices.
As illustrated in
The term “gate pitch” as used herein defines a distance from a left edge of a gate structure to a left edge of an adjacent identical gate structure. The minimum gate pitch in a semiconductor device is termed “contacted poly pitch” (CPP), with a corresponding minimum gate-to-gate spacing. The term “spacing” as used herein defines a distance between two adjacent structures.
In this embodiment of the disclosure, the gate pitch d1 of
With continuing reference from
The gate structure 304 typically includes a layer of gate insulating material (e.g., a layer of high-k dielectric material having a dielectric constant of typically 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon), that serve as gate electrode for the gate structure 304. The gate insulating material and the conductive material layers are not separately shown in the accompanying drawings.
A dielectric layer 310 is deposited over the gate structures 304 and the epitaxial regions 308 using a suitable deposition process. The dielectric layer 310 may be deposited in a one or a multi-step process, and a suitable planarization process may be performed to form a substantially planar top dielectric surface 312. The dielectric layer 310 is preferably a dielectric material, e.g., silicon dioxide, suitable to electrically isolate conductive features ultimately formed therein while maintaining a robust structure during the subsequent processing steps.
The interconnect structures 322 are electrically connected to the epitaxial regions 308. The interconnect structures 322 may be in a form of line-type structures that traverse across at least two active regions 302 of the semiconductor device 300. The conductive material may include tungsten, copper, aluminum, alloys of these metals and/or combinations thereof. In one embodiment of the disclosure, the interconnect structures 322 are preferably formed of tungsten.
Although not shown in
The material removing process may include one or more dry etching processes, wet etching processes, other suitable etching processes (e.g., reactive ion etching), and/or combinations thereof. The contact openings 334a preferably have the same width as the interconnect structures 314, even though wider or narrower widths have been contemplated.
As illustrated by the semiconductor device 100 shown in
With continuing reference from
The gate structure 404 typically includes a layer of gate insulating material, (e.g., a layer of high-k dielectric material having a dielectric constant of typically 10 or greater) or silicon dioxide, and one or more conductive material layers, e.g., metal and/or polysilicon, that serve as gate electrode for the gate structure 404. The gate insulating material and the conductive material layers are not separately shown in the accompanying drawings.
A dielectric layer 410 is deposited over the gate structures 404 and the epitaxial regions 408 using a suitable deposition process. The dielectric layer 410 may be deposited in a one or a multi-step process, and a suitable planarization process may be performed to form a substantially planar top dielectric surface 412. The dielectric layer 410 is preferably a dielectric material, e.g., silicon dioxide, suitable to electrically isolate conductive features ultimately formed therein while maintaining a robust structure during the subsequent processing steps.
Top surfaces 420 of the gate structures 404 are exposed in the interconnect openings 418a and top surfaces 422 of the epitaxial regions 408 are exposed in the interconnect openings 418b. Although, the interconnect openings 418a over the gate structures 404 and the interconnect openings 418b over the epitaxial regions 408 are illustrated to have the same width in
It is recognized in this present disclosure that the dielectric layer 410 over the gate structures 404 has a thinner thickness than that over the epitaxial regions 408. As a result, it is possible to predict a shorter period of time it will take to remove the dielectric layer 410 to form the interconnect openings 418a to the gate structures 404 as compared to a longer period of time it will take to remove the dielectric layer 410 to form the interconnect openings 418b to the epitaxial regions 408. The material removing process may include a dry etching process, e.g., a reactive ion etching (ME) process or any suitable material removing process with an etch chemistry having a greater selectivity for the dielectric layer 410 than for the gate structure 404. For instance, an etch chemistry may be selected such that the material removal rate of the dielectric layer 410 is much higher than that of the gate structure 404. Accordingly, the interconnect openings 418b continue to extend to the epitaxial regions 408 while the extension of the interconnect openings 418a at the gate structures 404 will be substantially impeded due to the lower material removal rate of the gate structure material. A portion of the gate structure 404 may or may not be removed by the material removing process during the extension of the interconnect openings 418b to the epitaxial regions 408.
Although not shown in
The contact openings 436 may be formed in a one, a two or a multi-step process. In an embodiment of the disclosure, the contact openings 436 may be formed in the dielectric layer 430 by performing a first material removing process, the contact openings 436 stopping at the etch stop layer 428. A second material removing process may be performed to form the contact openings (not shown) over other portions of the semiconductor device 400, i.e., over shallow trench isolation regions. The second material removing process extends the contact openings 436 through the etch stop layer 428 to the interconnect structures 424. In another embodiment of the disclosure, the contact openings 436 may be formed over the interconnect structures 424 after forming the contact openings (not shown) over other portions of the semiconductor device 400.
The etch stop layer 428 may be selected based upon etch selectivity to one or more features of the semiconductor device 400. For instance, the first material removing process may exhibit a high etch selectivity between the dielectric layer 430 and the etch stop layer 428, such that the first material removing process removes the dielectric layer 430 without substantially removing the etch stop layer 428. The second material removing process may exhibit a high etch selectivity between the etch stop layer 428 and the dielectric layer 430, such that the second material removing process removes the etch stop layer 428 without substantially removing the dielectric layer 430. In this embodiment of the disclosure, the etch stop layer 428 is a contact etch stop layer (CESL) and may include a silicon carbonitride layer, a silicon nitride layer, a silicon carbide layer or other suitable etch stop layer having any suitable thickness.
As illustrated in
It is understood that the semiconductor devices 300 and 400 may undergo further semiconductor processing steps to form various features known in the art. For instance, a plurality of conductive vias may be formed to establish an electrical connection between the contact structures and the back-end-of-line (BEOL) regions of the semiconductor devices 300 and 400. The BEOL region typically includes a plurality of conductive lines and interconnect vias that are routed as needed across the semiconductor devices 300 and 400.
In the above detailed description, methods of forming contact structures over an active region of a semiconductor device and the resulting semiconductor devices are presented. The contact structures may be discrete contact structures or line-type contact structures formed over the gate structures in a location where the gate structures traverse across the active regions of the semiconductor device. The placements of these contact structures over an active region enable shorter electrical paths through the gate structures and thus reducing undesirable gate resistance. Reducing gate resistance is advantageous for radio frequency (RF) devices as the performance of the RF devices is sensitive to gate resistance. The disclosed methods of forming contact structures over an active region of a semiconductor device are also particularly advantageous for RF devices. The RF devices are typically fabricated in regions of the semiconductor device having wide gate pitch, e.g., at least 1.5×CPP, and adopting the disclosed methods present a simpler process flow for forming contact structures over an active region of a semiconductor device.
The terms “top”, “bottom”, “over”, “under”, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Similarly, if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in one embodiment” herein do not necessarily all refer to the same embodiment.
In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of materials, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about”.
While several exemplary embodiments have been presented in the above detailed description of the device, it should be appreciated that a number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the device in any way. Rather, the above detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes may be made in the function and arrangement of elements and method of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.
